Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30954

1

T1

23

T2

19

T3

19

auto[1]

279

1

T91

17

T70

1

T73

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30967	1			T1	23		T2	19		T3	19
auto[134217728:268435455]	5	1			T91	1		T270	1		T274	1
auto[268435456:402653183]	6	1			T156	1		T344	1		T290	1
auto[402653184:536870911]	7	1			T250	1		T344	1		T431	1
auto[536870912:671088639]	12	1			T91	1		T93	1		T156	3
auto[671088640:805306367]	11	1			T91	1		T73	1		T270	1
auto[805306368:939524095]	13	1			T91	1		T432	2		T433	1
auto[939524096:1073741823]	7	1			T91	1		T79	2		T302	1
auto[1073741824:1207959551]	13	1			T91	1		T78	1		T266	1
auto[1207959552:1342177279]	9	1			T156	2		T270	1		T433	1
auto[1342177280:1476395007]	8	1			T91	1		T432	1		T290	1
auto[1476395008:1610612735]	7	1			T302	1		T394	1		T250	1
auto[1610612736:1744830463]	7	1			T156	1		T79	1		T432	1
auto[1744830464:1879048191]	5	1			T433	1		T434	1		T395	1
auto[1879048192:2013265919]	4	1			T250	1		T432	1		T296	1
auto[2013265920:2147483647]	2	1			T344	1		T296	1		-	-
auto[2147483648:2281701375]	6	1			T91	1		T311	1		T435	1
auto[2281701376:2415919103]	6	1			T91	1		T73	1		T93	1
auto[2415919104:2550136831]	10	1			T249	1		T311	2		T433	1
auto[2550136832:2684354559]	13	1			T91	1		T156	1		T302	1
auto[2684354560:2818572287]	7	1			T91	1		T302	1		T394	1
auto[2818572288:2952790015]	9	1			T93	2		T348	1		T290	2
auto[2952790016:3087007743]	9	1			T91	3		T290	1		T291	1
auto[3087007744:3221225471]	9	1			T93	1		T156	1		T266	1
auto[3221225472:3355443199]	11	1			T91	1		T271	1		T296	3
auto[3355443200:3489660927]	8	1			T73	1		T156	1		T290	1
auto[3489660928:3623878655]	11	1			T70	1		T270	1		T344	1
auto[3623878656:3758096383]	11	1			T273	1		T348	1		T344	1
auto[3758096384:3892314111]	10	1			T93	1		T280	1		T266	1
auto[3892314112:4026531839]	13	1			T73	2		T270	1		T394	1
auto[4026531840:4160749567]	6	1			T249	1		T344	1		T433	1
auto[4160749568:4294967295]	11	1			T91	1		T73	1		T249	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30954	1			T1	23		T2	19		T3	19
auto[0:134217727]	auto[1]	13	1			T91	1		T73	1		T93	1
auto[134217728:268435455]	auto[1]	5	1			T91	1		T270	1		T274	1
auto[268435456:402653183]	auto[1]	6	1			T156	1		T344	1		T290	1
auto[402653184:536870911]	auto[1]	7	1			T250	1		T344	1		T431	1
auto[536870912:671088639]	auto[1]	12	1			T91	1		T93	1		T156	3
auto[671088640:805306367]	auto[1]	11	1			T91	1		T73	1		T270	1
auto[805306368:939524095]	auto[1]	13	1			T91	1		T432	2		T433	1
auto[939524096:1073741823]	auto[1]	7	1			T91	1		T79	2		T302	1
auto[1073741824:1207959551]	auto[1]	13	1			T91	1		T78	1		T266	1
auto[1207959552:1342177279]	auto[1]	9	1			T156	2		T270	1		T433	1
auto[1342177280:1476395007]	auto[1]	8	1			T91	1		T432	1		T290	1
auto[1476395008:1610612735]	auto[1]	7	1			T302	1		T394	1		T250	1
auto[1610612736:1744830463]	auto[1]	7	1			T156	1		T79	1		T432	1
auto[1744830464:1879048191]	auto[1]	5	1			T433	1		T434	1		T395	1
auto[1879048192:2013265919]	auto[1]	4	1			T250	1		T432	1		T296	1
auto[2013265920:2147483647]	auto[1]	2	1			T344	1		T296	1		-	-
auto[2147483648:2281701375]	auto[1]	6	1			T91	1		T311	1		T435	1
auto[2281701376:2415919103]	auto[1]	6	1			T91	1		T73	1		T93	1
auto[2415919104:2550136831]	auto[1]	10	1			T249	1		T311	2		T433	1
auto[2550136832:2684354559]	auto[1]	13	1			T91	1		T156	1		T302	1
auto[2684354560:2818572287]	auto[1]	7	1			T91	1		T302	1		T394	1
auto[2818572288:2952790015]	auto[1]	9	1			T93	2		T348	1		T290	2
auto[2952790016:3087007743]	auto[1]	9	1			T91	3		T290	1		T291	1
auto[3087007744:3221225471]	auto[1]	9	1			T93	1		T156	1		T266	1
auto[3221225472:3355443199]	auto[1]	11	1			T91	1		T271	1		T296	3
auto[3355443200:3489660927]	auto[1]	8	1			T73	1		T156	1		T290	1
auto[3489660928:3623878655]	auto[1]	11	1			T70	1		T270	1		T344	1
auto[3623878656:3758096383]	auto[1]	11	1			T273	1		T348	1		T344	1
auto[3758096384:3892314111]	auto[1]	10	1			T93	1		T280	1		T266	1
auto[3892314112:4026531839]	auto[1]	13	1			T73	2		T270	1		T394	1
auto[4026531840:4160749567]	auto[1]	6	1			T249	1		T344	1		T433	1
auto[4160749568:4294967295]	auto[1]	11	1			T91	1		T73	1		T249	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1621

1

T4

2

T14

1

T15

4

auto[1]

1750

1

T4

1

T14

2

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T4	1		T116	1		T205	2
auto[134217728:268435455]	86	1			T38	1		T60	1		T206	1
auto[268435456:402653183]	104	1			T15	2		T73	1		T60	2
auto[402653184:536870911]	99	1			T74	1		T19	1		T91	1
auto[536870912:671088639]	91	1			T15	1		T58	1		T60	1
auto[671088640:805306367]	102	1			T114	1		T71	1		T48	3
auto[805306368:939524095]	107	1			T39	1		T95	1		T252	1
auto[939524096:1073741823]	99	1			T39	1		T48	1		T60	1
auto[1073741824:1207959551]	100	1			T114	1		T73	1		T58	1
auto[1207959552:1342177279]	130	1			T4	1		T74	1		T5	2
auto[1342177280:1476395007]	101	1			T207	1		T60	2		T95	1
auto[1476395008:1610612735]	101	1			T5	1		T73	1		T48	1
auto[1610612736:1744830463]	125	1			T26	1		T126	1		T70	1
auto[1744830464:1879048191]	88	1			T14	1		T5	1		T70	1
auto[1879048192:2013265919]	102	1			T38	1		T60	1		T66	1
auto[2013265920:2147483647]	123	1			T129	1		T38	1		T92	1
auto[2147483648:2281701375]	85	1			T14	1		T129	1		T39	1
auto[2281701376:2415919103]	91	1			T38	1		T114	1		T65	2
auto[2415919104:2550136831]	104	1			T14	1		T15	1		T38	2
auto[2550136832:2684354559]	107	1			T19	1		T60	1		T101	1
auto[2684354560:2818572287]	111	1			T74	1		T5	1		T126	1
auto[2818572288:2952790015]	98	1			T18	1		T39	1		T207	1
auto[2952790016:3087007743]	101	1			T4	1		T38	1		T114	1
auto[3087007744:3221225471]	112	1			T17	1		T19	1		T39	1
auto[3221225472:3355443199]	107	1			T39	2		T71	1		T60	3
auto[3355443200:3489660927]	108	1			T19	1		T48	1		T208	1
auto[3489660928:3623878655]	115	1			T19	1		T38	1		T60	1
auto[3623878656:3758096383]	123	1			T5	1		T205	1		T92	1
auto[3758096384:3892314111]	113	1			T207	2		T60	1		T64	2
auto[3892314112:4026531839]	112	1			T5	1		T26	1		T207	1
auto[4026531840:4160749567]	120	1			T91	2		T26	1		T114	1
auto[4160749568:4294967295]	104	1			T205	1		T60	2		T209	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T205	2		T114	1		T71	1
auto[0:134217727]	auto[1]	48	1			T4	1		T116	1		T60	2
auto[134217728:268435455]	auto[0]	35	1			T50	1		T128	1		T222	1
auto[134217728:268435455]	auto[1]	51	1			T38	1		T60	1		T206	1
auto[268435456:402653183]	auto[0]	53	1			T15	2		T60	2		T93	1
auto[268435456:402653183]	auto[1]	51	1			T73	1		T94	1		T380	1
auto[402653184:536870911]	auto[0]	41	1			T19	1		T58	1		T29	1
auto[402653184:536870911]	auto[1]	58	1			T74	1		T91	1		T26	1
auto[536870912:671088639]	auto[0]	41	1			T15	1		T94	1		T50	2
auto[536870912:671088639]	auto[1]	50	1			T58	1		T60	1		T94	1
auto[671088640:805306367]	auto[0]	49	1			T114	1		T71	1		T60	2
auto[671088640:805306367]	auto[1]	53	1			T48	3		T30	1		T76	1
auto[805306368:939524095]	auto[0]	50	1			T95	1		T259	1		T256	1
auto[805306368:939524095]	auto[1]	57	1			T39	1		T252	1		T380	1
auto[939524096:1073741823]	auto[0]	47	1			T29	1		T259	1		T156	1
auto[939524096:1073741823]	auto[1]	52	1			T39	1		T48	1		T60	1
auto[1073741824:1207959551]	auto[0]	52	1			T60	1		T94	1		T6	1
auto[1073741824:1207959551]	auto[1]	48	1			T114	1		T73	1		T58	1
auto[1207959552:1342177279]	auto[0]	73	1			T4	1		T74	1		T5	2
auto[1207959552:1342177279]	auto[1]	57	1			T206	1		T27	1		T277	1
auto[1342177280:1476395007]	auto[0]	59	1			T60	2		T251	1		T256	1
auto[1342177280:1476395007]	auto[1]	42	1			T207	1		T95	1		T307	1
auto[1476395008:1610612735]	auto[0]	44	1			T60	2		T66	1		T206	1
auto[1476395008:1610612735]	auto[1]	57	1			T5	1		T73	1		T48	1
auto[1610612736:1744830463]	auto[0]	55	1			T126	1		T48	1		T95	1
auto[1610612736:1744830463]	auto[1]	70	1			T26	1		T70	1		T95	1
auto[1744830464:1879048191]	auto[0]	42	1			T14	1		T5	1		T152	1
auto[1744830464:1879048191]	auto[1]	46	1			T70	1		T208	1		T95	1
auto[1879048192:2013265919]	auto[0]	46	1			T38	1		T66	1		T94	2
auto[1879048192:2013265919]	auto[1]	56	1			T60	1		T210	1		T49	1
auto[2013265920:2147483647]	auto[0]	59	1			T129	1		T38	1		T94	1
auto[2013265920:2147483647]	auto[1]	64	1			T92	1		T70	1		T60	2
auto[2147483648:2281701375]	auto[0]	42	1			T39	1		T70	1		T71	1
auto[2147483648:2281701375]	auto[1]	43	1			T14	1		T129	1		T60	1
auto[2281701376:2415919103]	auto[0]	44	1			T114	1		T65	1		T76	1
auto[2281701376:2415919103]	auto[1]	47	1			T38	1		T65	1		T208	1
auto[2415919104:2550136831]	auto[0]	51	1			T15	1		T38	2		T92	1
auto[2415919104:2550136831]	auto[1]	53	1			T14	1		T94	1		T23	1
auto[2550136832:2684354559]	auto[0]	56	1			T60	1		T101	1		T94	1
auto[2550136832:2684354559]	auto[1]	51	1			T19	1		T138	1		T379	1
auto[2684354560:2818572287]	auto[0]	55	1			T74	1		T126	1		T28	1
auto[2684354560:2818572287]	auto[1]	56	1			T5	1		T71	1		T48	1
auto[2818572288:2952790015]	auto[0]	44	1			T39	1		T60	2		T99	1
auto[2818572288:2952790015]	auto[1]	54	1			T18	1		T207	1		T60	1
auto[2952790016:3087007743]	auto[0]	49	1			T4	1		T38	1		T114	1
auto[2952790016:3087007743]	auto[1]	52	1			T48	1		T60	1		T64	1
auto[3087007744:3221225471]	auto[0]	50	1			T19	1		T126	1		T60	1
auto[3087007744:3221225471]	auto[1]	62	1			T17	1		T39	1		T5	1
auto[3221225472:3355443199]	auto[0]	47	1			T39	1		T71	1		T60	1
auto[3221225472:3355443199]	auto[1]	60	1			T39	1		T60	2		T102	1
auto[3355443200:3489660927]	auto[0]	52	1			T19	1		T208	1		T101	1
auto[3355443200:3489660927]	auto[1]	56	1			T48	1		T23	1		T380	1
auto[3489660928:3623878655]	auto[0]	63	1			T19	1		T38	1		T60	1
auto[3489660928:3623878655]	auto[1]	52	1			T210	1		T49	1		T256	1
auto[3623878656:3758096383]	auto[0]	52	1			T5	1		T92	1		T28	1
auto[3623878656:3758096383]	auto[1]	71	1			T205	1		T60	3		T64	1
auto[3758096384:3892314111]	auto[0]	55	1			T207	1		T66	1		T379	1
auto[3758096384:3892314111]	auto[1]	58	1			T207	1		T60	1		T64	2
auto[3892314112:4026531839]	auto[0]	48	1			T5	1		T114	1		T71	1
auto[3892314112:4026531839]	auto[1]	64	1			T26	1		T207	1		T29	1
auto[4026531840:4160749567]	auto[0]	62	1			T91	2		T114	1		T58	1
auto[4026531840:4160749567]	auto[1]	58	1			T26	1		T379	1		T259	1
auto[4160749568:4294967295]	auto[0]	51	1			T60	1		T98	1		T259	1
auto[4160749568:4294967295]	auto[1]	53	1			T205	1		T60	1		T209	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T4

3

T14

2

T15

2

auto[1]

1755

1

T14

1

T15

2

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T38	1		T92	1		T114	1
auto[134217728:268435455]	98	1			T126	1		T60	2		T76	1
auto[268435456:402653183]	101	1			T74	1		T19	1		T91	1
auto[402653184:536870911]	107	1			T14	1		T39	1		T71	1
auto[536870912:671088639]	93	1			T38	1		T60	1		T65	1
auto[671088640:805306367]	80	1			T129	1		T207	1		T60	4
auto[805306368:939524095]	109	1			T4	1		T207	1		T65	1
auto[939524096:1073741823]	129	1			T74	2		T207	1		T71	1
auto[1073741824:1207959551]	106	1			T14	1		T19	1		T38	1
auto[1207959552:1342177279]	96	1			T19	1		T39	1		T114	1
auto[1342177280:1476395007]	99	1			T4	1		T5	1		T205	1
auto[1476395008:1610612735]	97	1			T4	1		T60	1		T94	3
auto[1610612736:1744830463]	107	1			T15	1		T91	1		T205	1
auto[1744830464:1879048191]	114	1			T129	1		T26	1		T92	1
auto[1879048192:2013265919]	101	1			T38	1		T39	2		T58	1
auto[2013265920:2147483647]	109	1			T207	1		T48	2		T60	2
auto[2147483648:2281701375]	101	1			T15	1		T205	1		T60	3
auto[2281701376:2415919103]	115	1			T14	1		T39	1		T114	2
auto[2415919104:2550136831]	93	1			T114	1		T71	1		T60	1
auto[2550136832:2684354559]	117	1			T5	1		T114	1		T28	1
auto[2684354560:2818572287]	103	1			T38	1		T91	1		T60	3
auto[2818572288:2952790015]	116	1			T39	1		T116	1		T5	1
auto[2952790016:3087007743]	103	1			T18	1		T38	1		T39	1
auto[3087007744:3221225471]	108	1			T15	1		T17	1		T38	1
auto[3221225472:3355443199]	129	1			T38	1		T5	1		T126	1
auto[3355443200:3489660927]	105	1			T15	1		T208	1		T94	3
auto[3489660928:3623878655]	102	1			T5	1		T73	1		T48	1
auto[3623878656:3758096383]	106	1			T70	1		T60	2		T65	1
auto[3758096384:3892314111]	110	1			T19	1		T26	1		T48	1
auto[3892314112:4026531839]	98	1			T19	1		T92	1		T71	1
auto[4026531840:4160749567]	103	1			T26	1		T205	1		T70	2
auto[4160749568:4294967295]	101	1			T114	1		T60	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T38	1		T92	1		T114	1
auto[0:134217727]	auto[1]	69	1			T48	1		T60	1		T208	2
auto[134217728:268435455]	auto[0]	43	1			T126	1		T76	1		T374	1
auto[134217728:268435455]	auto[1]	55	1			T60	2		T156	1		T199	1
auto[268435456:402653183]	auto[0]	48	1			T74	1		T19	1		T60	1
auto[268435456:402653183]	auto[1]	53	1			T91	1		T60	1		T94	1
auto[402653184:536870911]	auto[0]	42	1			T39	1		T71	1		T60	1
auto[402653184:536870911]	auto[1]	65	1			T14	1		T94	1		T256	1
auto[536870912:671088639]	auto[0]	42	1			T38	1		T95	1		T76	1
auto[536870912:671088639]	auto[1]	51	1			T60	1		T65	1		T252	1
auto[671088640:805306367]	auto[0]	40	1			T60	3		T259	1		T256	1
auto[671088640:805306367]	auto[1]	40	1			T129	1		T207	1		T60	1
auto[805306368:939524095]	auto[0]	58	1			T4	1		T66	1		T138	1
auto[805306368:939524095]	auto[1]	51	1			T207	1		T65	1		T252	1
auto[939524096:1073741823]	auto[0]	56	1			T74	1		T71	1		T48	1
auto[939524096:1073741823]	auto[1]	73	1			T74	1		T207	1		T95	1
auto[1073741824:1207959551]	auto[0]	50	1			T14	1		T19	1		T38	1
auto[1073741824:1207959551]	auto[1]	56	1			T48	2		T60	1		T77	1
auto[1207959552:1342177279]	auto[0]	40	1			T39	1		T114	1		T71	1
auto[1207959552:1342177279]	auto[1]	56	1			T19	1		T73	1		T60	2
auto[1342177280:1476395007]	auto[0]	44	1			T4	1		T66	1		T101	1
auto[1342177280:1476395007]	auto[1]	55	1			T5	1		T205	1		T58	1
auto[1476395008:1610612735]	auto[0]	43	1			T4	1		T94	2		T6	1
auto[1476395008:1610612735]	auto[1]	54	1			T60	1		T94	1		T307	1
auto[1610612736:1744830463]	auto[0]	57	1			T15	1		T91	1		T205	1
auto[1610612736:1744830463]	auto[1]	50	1			T73	1		T64	1		T374	1
auto[1744830464:1879048191]	auto[0]	55	1			T92	1		T66	1		T93	1
auto[1744830464:1879048191]	auto[1]	59	1			T129	1		T26	1		T71	1
auto[1879048192:2013265919]	auto[0]	52	1			T38	1		T39	2		T58	1
auto[1879048192:2013265919]	auto[1]	49	1			T60	1		T29	1		T94	1
auto[2013265920:2147483647]	auto[0]	54	1			T206	1		T93	1		T259	1
auto[2013265920:2147483647]	auto[1]	55	1			T207	1		T48	2		T60	2
auto[2147483648:2281701375]	auto[0]	50	1			T15	1		T205	1		T60	2
auto[2147483648:2281701375]	auto[1]	51	1			T60	1		T138	1		T379	1
auto[2281701376:2415919103]	auto[0]	49	1			T14	1		T114	2		T126	1
auto[2281701376:2415919103]	auto[1]	66	1			T39	1		T58	1		T60	3
auto[2415919104:2550136831]	auto[0]	43	1			T114	1		T60	1		T251	1
auto[2415919104:2550136831]	auto[1]	50	1			T71	1		T49	1		T94	1
auto[2550136832:2684354559]	auto[0]	58	1			T5	1		T114	1		T28	1
auto[2550136832:2684354559]	auto[1]	59	1			T48	1		T60	1		T49	1
auto[2684354560:2818572287]	auto[0]	46	1			T91	1		T76	1		T94	1
auto[2684354560:2818572287]	auto[1]	57	1			T38	1		T60	3		T64	1
auto[2818572288:2952790015]	auto[0]	49	1			T5	1		T58	1		T60	2
auto[2818572288:2952790015]	auto[1]	67	1			T39	1		T116	1		T26	1
auto[2952790016:3087007743]	auto[0]	52	1			T18	1		T38	1		T5	1
auto[2952790016:3087007743]	auto[1]	51	1			T39	1		T207	1		T30	1
auto[3087007744:3221225471]	auto[0]	56	1			T38	1		T5	1		T60	2
auto[3087007744:3221225471]	auto[1]	52	1			T15	1		T17	1		T64	1
auto[3221225472:3355443199]	auto[0]	51	1			T5	1		T126	1		T28	1
auto[3221225472:3355443199]	auto[1]	78	1			T38	1		T95	1		T93	1
auto[3355443200:3489660927]	auto[0]	60	1			T94	2		T259	1		T269	1
auto[3355443200:3489660927]	auto[1]	45	1			T15	1		T208	1		T94	1
auto[3489660928:3623878655]	auto[0]	48	1			T50	1		T304	1		T284	1
auto[3489660928:3623878655]	auto[1]	54	1			T5	1		T73	1		T48	1
auto[3623878656:3758096383]	auto[0]	57	1			T60	1		T65	1		T206	1
auto[3623878656:3758096383]	auto[1]	49	1			T70	1		T60	1		T23	1
auto[3758096384:3892314111]	auto[0]	57	1			T60	2		T101	1		T275	1
auto[3758096384:3892314111]	auto[1]	53	1			T19	1		T26	1		T48	1
auto[3892314112:4026531839]	auto[0]	55	1			T19	1		T92	1		T71	1
auto[3892314112:4026531839]	auto[1]	43	1			T64	1		T209	1		T206	1
auto[4026531840:4160749567]	auto[0]	56	1			T70	1		T48	1		T29	1
auto[4026531840:4160749567]	auto[1]	47	1			T26	1		T205	1		T70	1
auto[4160749568:4294967295]	auto[0]	59	1			T114	1		T60	1		T76	1
auto[4160749568:4294967295]	auto[1]	42	1			T29	1		T206	1		T252	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T4

3

T14

2

T15

3

auto[1]

1756

1

T14

1

T15

1

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T74	1		T48	1		T60	1
auto[134217728:268435455]	105	1			T26	1		T58	1		T60	1
auto[268435456:402653183]	105	1			T129	1		T205	1		T58	1
auto[402653184:536870911]	108	1			T205	1		T114	1		T71	1
auto[536870912:671088639]	92	1			T207	1		T126	1		T71	1
auto[671088640:805306367]	116	1			T14	1		T19	1		T116	1
auto[805306368:939524095]	105	1			T5	1		T60	4		T210	1
auto[939524096:1073741823]	111	1			T26	1		T48	1		T65	1
auto[1073741824:1207959551]	117	1			T4	2		T19	1		T208	1
auto[1207959552:1342177279]	92	1			T15	1		T60	1		T98	1
auto[1342177280:1476395007]	119	1			T18	1		T74	1		T38	1
auto[1476395008:1610612735]	98	1			T14	1		T129	1		T60	3
auto[1610612736:1744830463]	119	1			T38	1		T71	1		T48	1
auto[1744830464:1879048191]	102	1			T15	1		T19	1		T5	1
auto[1879048192:2013265919]	104	1			T38	1		T114	1		T71	1
auto[2013265920:2147483647]	123	1			T15	1		T38	1		T5	1
auto[2147483648:2281701375]	98	1			T5	1		T92	1		T48	1
auto[2281701376:2415919103]	129	1			T74	1		T60	3		T65	1
auto[2415919104:2550136831]	89	1			T39	1		T95	1		T94	3
auto[2550136832:2684354559]	111	1			T5	1		T26	1		T92	1
auto[2684354560:2818572287]	107	1			T15	1		T114	1		T48	1
auto[2818572288:2952790015]	98	1			T14	1		T19	1		T39	1
auto[2952790016:3087007743]	107	1			T70	1		T208	1		T210	1
auto[3087007744:3221225471]	72	1			T39	1		T5	1		T91	1
auto[3221225472:3355443199]	106	1			T17	1		T39	1		T114	1
auto[3355443200:3489660927]	96	1			T38	1		T39	1		T60	2
auto[3489660928:3623878655]	105	1			T4	1		T114	1		T73	1
auto[3623878656:3758096383]	112	1			T19	1		T60	2		T95	1
auto[3758096384:3892314111]	131	1			T207	1		T71	1		T48	1
auto[3892314112:4026531839]	90	1			T39	1		T126	1		T28	1
auto[4026531840:4160749567]	98	1			T38	2		T39	1		T207	1
auto[4160749568:4294967295]	94	1			T38	1		T70	1		T29	1