Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32991

1

T1

35

T2

20

T3

21

auto[1]

275

1

T46

8

T119

1

T135

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32998	1			T1	35		T2	20		T3	21
auto[134217728:268435455]	8	1			T361	1		T441	1		T387	2
auto[268435456:402653183]	7	1			T135	1		T420	1		T137	1
auto[402653184:536870911]	5	1			T46	1		T307	1		T387	2
auto[536870912:671088639]	8	1			T135	1		T420	1		T297	1
auto[671088640:805306367]	4	1			T441	1		T428	1		T371	1
auto[805306368:939524095]	8	1			T135	1		T420	2		T137	1
auto[939524096:1073741823]	6	1			T46	1		T138	1		T442	1
auto[1073741824:1207959551]	15	1			T46	1		T137	1		T138	1
auto[1207959552:1342177279]	9	1			T136	1		T391	1		T443	1
auto[1342177280:1476395007]	5	1			T135	1		T442	1		T294	1
auto[1476395008:1610612735]	14	1			T138	1		T284	1		T444	2
auto[1610612736:1744830463]	7	1			T137	1		T138	1		T442	1
auto[1744830464:1879048191]	11	1			T420	1		T297	2		T348	1
auto[1879048192:2013265919]	10	1			T137	1		T138	1		T427	1
auto[2013265920:2147483647]	9	1			T420	1		T138	1		T442	1
auto[2147483648:2281701375]	5	1			T443	1		T441	1		T398	2
auto[2281701376:2415919103]	12	1			T420	1		T138	1		T442	2
auto[2415919104:2550136831]	7	1			T46	1		T420	1		T137	1
auto[2550136832:2684354559]	8	1			T427	1		T442	1		T294	2
auto[2684354560:2818572287]	13	1			T297	1		T391	1		T361	1
auto[2818572288:2952790015]	11	1			T46	1		T135	1		T136	1
auto[2952790016:3087007743]	8	1			T444	1		T441	1		T387	1
auto[3087007744:3221225471]	10	1			T46	1		T135	1		T420	2
auto[3221225472:3355443199]	9	1			T420	1		T137	1		T284	1
auto[3355443200:3489660927]	11	1			T46	1		T420	1		T137	2
auto[3489660928:3623878655]	6	1			T391	1		T328	2		T441	1
auto[3623878656:3758096383]	7	1			T387	2		T445	1		T446	2
auto[3758096384:3892314111]	7	1			T135	1		T136	1		T442	1
auto[3892314112:4026531839]	10	1			T420	1		T391	1		T284	1
auto[4026531840:4160749567]	9	1			T297	1		T443	1		T442	1
auto[4160749568:4294967295]	9	1			T119	1		T420	2		T328	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32991	1			T1	35		T2	20		T3	21
auto[0:134217727]	auto[1]	7	1			T46	1		T361	1		T294	1
auto[134217728:268435455]	auto[1]	8	1			T361	1		T441	1		T387	2
auto[268435456:402653183]	auto[1]	7	1			T135	1		T420	1		T137	1
auto[402653184:536870911]	auto[1]	5	1			T46	1		T307	1		T387	2
auto[536870912:671088639]	auto[1]	8	1			T135	1		T420	1		T297	1
auto[671088640:805306367]	auto[1]	4	1			T441	1		T428	1		T371	1
auto[805306368:939524095]	auto[1]	8	1			T135	1		T420	2		T137	1
auto[939524096:1073741823]	auto[1]	6	1			T46	1		T138	1		T442	1
auto[1073741824:1207959551]	auto[1]	15	1			T46	1		T137	1		T138	1
auto[1207959552:1342177279]	auto[1]	9	1			T136	1		T391	1		T443	1
auto[1342177280:1476395007]	auto[1]	5	1			T135	1		T442	1		T294	1
auto[1476395008:1610612735]	auto[1]	14	1			T138	1		T284	1		T444	2
auto[1610612736:1744830463]	auto[1]	7	1			T137	1		T138	1		T442	1
auto[1744830464:1879048191]	auto[1]	11	1			T420	1		T297	2		T348	1
auto[1879048192:2013265919]	auto[1]	10	1			T137	1		T138	1		T427	1
auto[2013265920:2147483647]	auto[1]	9	1			T420	1		T138	1		T442	1
auto[2147483648:2281701375]	auto[1]	5	1			T443	1		T441	1		T398	2
auto[2281701376:2415919103]	auto[1]	12	1			T420	1		T138	1		T442	2
auto[2415919104:2550136831]	auto[1]	7	1			T46	1		T420	1		T137	1
auto[2550136832:2684354559]	auto[1]	8	1			T427	1		T442	1		T294	2
auto[2684354560:2818572287]	auto[1]	13	1			T297	1		T391	1		T361	1
auto[2818572288:2952790015]	auto[1]	11	1			T46	1		T135	1		T136	1
auto[2952790016:3087007743]	auto[1]	8	1			T444	1		T441	1		T387	1
auto[3087007744:3221225471]	auto[1]	10	1			T46	1		T135	1		T420	2
auto[3221225472:3355443199]	auto[1]	9	1			T420	1		T137	1		T284	1
auto[3355443200:3489660927]	auto[1]	11	1			T46	1		T420	1		T137	2
auto[3489660928:3623878655]	auto[1]	6	1			T391	1		T328	2		T441	1
auto[3623878656:3758096383]	auto[1]	7	1			T387	2		T445	1		T446	2
auto[3758096384:3892314111]	auto[1]	7	1			T135	1		T136	1		T442	1
auto[3892314112:4026531839]	auto[1]	10	1			T420	1		T391	1		T284	1
auto[4026531840:4160749567]	auto[1]	9	1			T297	1		T443	1		T442	1
auto[4160749568:4294967295]	auto[1]	9	1			T119	1		T420	2		T328	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1762

1

T5

3

T15

3

T16

1

auto[1]

1793

1

T5

2

T16

3

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T26	1		T27	2		T50	1
auto[134217728:268435455]	104	1			T15	1		T36	2		T19	1
auto[268435456:402653183]	108	1			T38	1		T46	1		T26	2
auto[402653184:536870911]	114	1			T5	1		T19	1		T26	2
auto[536870912:671088639]	116	1			T5	1		T16	1		T18	1
auto[671088640:805306367]	117	1			T38	1		T26	1		T27	1
auto[805306368:939524095]	110	1			T16	1		T27	1		T41	1
auto[939524096:1073741823]	127	1			T38	1		T46	1		T50	1
auto[1073741824:1207959551]	116	1			T19	1		T49	1		T224	1
auto[1207959552:1342177279]	117	1			T19	1		T94	1		T49	1
auto[1342177280:1476395007]	100	1			T38	1		T46	1		T26	1
auto[1476395008:1610612735]	112	1			T16	1		T18	1		T95	1
auto[1610612736:1744830463]	118	1			T27	1		T265	1		T95	1
auto[1744830464:1879048191]	124	1			T113	1		T48	2		T94	1
auto[1879048192:2013265919]	118	1			T36	1		T46	1		T48	1
auto[2013265920:2147483647]	113	1			T26	1		T27	2		T50	1
auto[2147483648:2281701375]	123	1			T15	1		T18	1		T38	1
auto[2281701376:2415919103]	90	1			T16	1		T27	1		T41	1
auto[2415919104:2550136831]	108	1			T119	1		T94	2		T224	1
auto[2550136832:2684354559]	102	1			T27	1		T119	1		T233	1
auto[2684354560:2818572287]	112	1			T15	1		T107	1		T265	1
auto[2818572288:2952790015]	122	1			T46	1		T27	1		T48	1
auto[2952790016:3087007743]	101	1			T5	1		T38	1		T46	1
auto[3087007744:3221225471]	104	1			T57	1		T23	1		T224	1
auto[3221225472:3355443199]	101	1			T5	1		T26	1		T48	1
auto[3355443200:3489660927]	107	1			T18	1		T27	2		T227	1
auto[3489660928:3623878655]	116	1			T226	1		T70	1		T136	3
auto[3623878656:3758096383]	104	1			T5	1		T93	1		T53	1
auto[3758096384:3892314111]	124	1			T119	1		T48	1		T222	1
auto[3892314112:4026531839]	109	1			T26	2		T48	1		T94	1
auto[4026531840:4160749567]	105	1			T41	1		T92	1		T85	1
auto[4160749568:4294967295]	111	1			T17	1		T38	2		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T26	1		T27	1		T50	1
auto[0:134217727]	auto[1]	54	1			T27	1		T94	1		T226	1
auto[134217728:268435455]	auto[0]	52	1			T15	1		T19	1		T113	1
auto[134217728:268435455]	auto[1]	52	1			T36	2		T92	1		T228	1
auto[268435456:402653183]	auto[0]	52	1			T38	1		T26	2		T27	1
auto[268435456:402653183]	auto[1]	56	1			T46	1		T224	1		T135	1
auto[402653184:536870911]	auto[0]	65	1			T19	1		T27	1		T226	1
auto[402653184:536870911]	auto[1]	49	1			T5	1		T26	2		T27	1
auto[536870912:671088639]	auto[0]	65	1			T18	1		T26	1		T226	1
auto[536870912:671088639]	auto[1]	51	1			T5	1		T16	1		T53	1
auto[671088640:805306367]	auto[0]	61	1			T38	1		T27	1		T107	1
auto[671088640:805306367]	auto[1]	56	1			T26	1		T119	1		T48	1
auto[805306368:939524095]	auto[0]	45	1			T27	1		T41	1		T225	1
auto[805306368:939524095]	auto[1]	65	1			T16	1		T89	1		T59	2
auto[939524096:1073741823]	auto[0]	65	1			T38	1		T46	1		T48	1
auto[939524096:1073741823]	auto[1]	62	1			T50	1		T70	1		T232	1
auto[1073741824:1207959551]	auto[0]	59	1			T49	1		T107	1		T136	1
auto[1073741824:1207959551]	auto[1]	57	1			T19	1		T224	1		T265	1
auto[1207959552:1342177279]	auto[0]	53	1			T19	1		T49	1		T224	1
auto[1207959552:1342177279]	auto[1]	64	1			T94	1		T146	1		T53	1
auto[1342177280:1476395007]	auto[0]	51	1			T46	1		T92	1		T146	1
auto[1342177280:1476395007]	auto[1]	49	1			T38	1		T26	1		T136	1
auto[1476395008:1610612735]	auto[0]	54	1			T18	1		T95	1		T146	1
auto[1476395008:1610612735]	auto[1]	58	1			T16	1		T53	1		T59	1
auto[1610612736:1744830463]	auto[0]	56	1			T265	1		T95	1		T6	1
auto[1610612736:1744830463]	auto[1]	62	1			T27	1		T53	2		T6	1
auto[1744830464:1879048191]	auto[0]	50	1			T113	1		T48	2		T94	1
auto[1744830464:1879048191]	auto[1]	74	1			T135	1		T228	1		T53	1
auto[1879048192:2013265919]	auto[0]	50	1			T48	1		T49	1		T107	1
auto[1879048192:2013265919]	auto[1]	68	1			T36	1		T46	1		T23	2
auto[2013265920:2147483647]	auto[0]	54	1			T27	1		T50	1		T135	1
auto[2013265920:2147483647]	auto[1]	59	1			T26	1		T27	1		T41	1
auto[2147483648:2281701375]	auto[0]	75	1			T15	1		T18	1		T113	1
auto[2147483648:2281701375]	auto[1]	48	1			T38	1		T26	1		T27	1
auto[2281701376:2415919103]	auto[0]	47	1			T16	1		T107	1		T85	1
auto[2281701376:2415919103]	auto[1]	43	1			T27	1		T41	1		T70	1
auto[2415919104:2550136831]	auto[0]	58	1			T94	1		T92	1		T29	1
auto[2415919104:2550136831]	auto[1]	50	1			T119	1		T94	1		T224	1
auto[2550136832:2684354559]	auto[0]	46	1			T233	1		T53	1		T65	1
auto[2550136832:2684354559]	auto[1]	56	1			T27	1		T119	1		T53	1
auto[2684354560:2818572287]	auto[0]	53	1			T15	1		T107	1		T59	1
auto[2684354560:2818572287]	auto[1]	59	1			T265	1		T274	2		T53	1
auto[2818572288:2952790015]	auto[0]	67	1			T46	1		T27	1		T48	1
auto[2818572288:2952790015]	auto[1]	55	1			T136	1		T53	3		T217	1
auto[2952790016:3087007743]	auto[0]	43	1			T5	1		T46	1		T26	1
auto[2952790016:3087007743]	auto[1]	58	1			T38	1		T224	1		T136	1
auto[3087007744:3221225471]	auto[0]	45	1			T93	1		T215	1		T54	1
auto[3087007744:3221225471]	auto[1]	59	1			T57	1		T23	1		T224	1
auto[3221225472:3355443199]	auto[0]	48	1			T5	1		T48	1		T71	1
auto[3221225472:3355443199]	auto[1]	53	1			T26	1		T94	1		T232	2
auto[3355443200:3489660927]	auto[0]	53	1			T6	2		T59	2		T7	1
auto[3355443200:3489660927]	auto[1]	54	1			T18	1		T27	2		T227	1
auto[3489660928:3623878655]	auto[0]	58	1			T226	1		T70	1		T93	1
auto[3489660928:3623878655]	auto[1]	58	1			T136	3		T223	1		T87	1
auto[3623878656:3758096383]	auto[0]	49	1			T5	1		T93	1		T59	1
auto[3623878656:3758096383]	auto[1]	55	1			T53	1		T59	1		T60	1
auto[3758096384:3892314111]	auto[0]	68	1			T48	1		T49	1		T70	1
auto[3758096384:3892314111]	auto[1]	56	1			T119	1		T222	1		T92	1
auto[3892314112:4026531839]	auto[0]	59	1			T48	1		T94	1		T9	1
auto[3892314112:4026531839]	auto[1]	50	1			T26	2		T305	1		T447	1
auto[4026531840:4160749567]	auto[0]	54	1			T6	1		T60	1		T66	1
auto[4026531840:4160749567]	auto[1]	51	1			T41	1		T92	1		T85	1
auto[4160749568:4294967295]	auto[0]	59	1			T38	1		T27	1		T226	1
auto[4160749568:4294967295]	auto[1]	52	1			T17	1		T38	1		T113	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T5

2

T15

3

T16

2

auto[1]

1795

1

T5

3

T16

2

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T18	1		T26	1		T27	1
auto[134217728:268435455]	101	1			T36	1		T26	1		T27	1
auto[268435456:402653183]	132	1			T16	1		T46	1		T26	1
auto[402653184:536870911]	85	1			T94	1		T53	2		T9	1
auto[536870912:671088639]	113	1			T26	1		T57	1		T48	1
auto[671088640:805306367]	103	1			T38	1		T27	1		T48	1
auto[805306368:939524095]	117	1			T5	2		T27	1		T48	1
auto[939524096:1073741823]	131	1			T27	1		T224	1		T135	1
auto[1073741824:1207959551]	119	1			T5	1		T38	1		T27	1
auto[1207959552:1342177279]	111	1			T19	1		T46	1		T27	1
auto[1342177280:1476395007]	117	1			T15	1		T38	1		T27	3
auto[1476395008:1610612735]	117	1			T38	1		T26	1		T119	1
auto[1610612736:1744830463]	104	1			T26	1		T53	1		T6	2
auto[1744830464:1879048191]	106	1			T46	1		T50	1		T135	1
auto[1879048192:2013265919]	118	1			T38	1		T26	2		T48	2
auto[2013265920:2147483647]	107	1			T224	1		T53	1		T59	4
auto[2147483648:2281701375]	100	1			T5	1		T26	1		T27	1
auto[2281701376:2415919103]	100	1			T36	1		T38	1		T26	1
auto[2415919104:2550136831]	102	1			T38	1		T27	1		T50	1
auto[2550136832:2684354559]	102	1			T18	2		T48	1		T23	2
auto[2684354560:2818572287]	110	1			T18	1		T19	1		T113	1
auto[2818572288:2952790015]	115	1			T15	1		T19	1		T46	1
auto[2952790016:3087007743]	109	1			T5	1		T38	1		T51	1
auto[3087007744:3221225471]	130	1			T19	1		T46	2		T94	1
auto[3221225472:3355443199]	110	1			T17	1		T36	1		T50	1
auto[3355443200:3489660927]	111	1			T16	1		T113	1		T92	1
auto[3489660928:3623878655]	106	1			T26	1		T27	1		T48	1
auto[3623878656:3758096383]	112	1			T15	1		T27	1		T113	1
auto[3758096384:3892314111]	118	1			T119	1		T107	1		T225	1
auto[3892314112:4026531839]	120	1			T16	1		T41	1		T70	1
auto[4026531840:4160749567]	125	1			T27	1		T49	1		T107	1
auto[4160749568:4294967295]	114	1			T16	1		T26	2		T226	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	37	1			T18	1		T226	1		T41	1
auto[0:134217727]	auto[1]	54	1			T26	1		T27	1		T57	1
auto[134217728:268435455]	auto[0]	51	1			T26	1		T27	1		T94	1
auto[134217728:268435455]	auto[1]	50	1			T36	1		T23	1		T265	1
auto[268435456:402653183]	auto[0]	65	1			T16	1		T46	1		T48	1
auto[268435456:402653183]	auto[1]	67	1			T26	1		T27	1		T51	1
auto[402653184:536870911]	auto[0]	42	1			T53	2		T9	1		T59	1
auto[402653184:536870911]	auto[1]	43	1			T94	1		T6	1		T137	1
auto[536870912:671088639]	auto[0]	55	1			T48	1		T94	2		T146	1
auto[536870912:671088639]	auto[1]	58	1			T26	1		T57	1		T232	1
auto[671088640:805306367]	auto[0]	52	1			T27	1		T48	1		T94	1
auto[671088640:805306367]	auto[1]	51	1			T38	1		T94	1		T70	1
auto[805306368:939524095]	auto[0]	56	1			T5	1		T27	1		T70	1
auto[805306368:939524095]	auto[1]	61	1			T5	1		T48	1		T92	1
auto[939524096:1073741823]	auto[0]	63	1			T27	1		T107	1		T92	1
auto[939524096:1073741823]	auto[1]	68	1			T224	1		T135	1		T92	1
auto[1073741824:1207959551]	auto[0]	61	1			T38	1		T27	1		T70	1
auto[1073741824:1207959551]	auto[1]	58	1			T5	1		T70	1		T233	1
auto[1207959552:1342177279]	auto[0]	51	1			T19	1		T46	1		T27	1
auto[1207959552:1342177279]	auto[1]	60	1			T48	1		T226	1		T23	1
auto[1342177280:1476395007]	auto[0]	52	1			T15	1		T27	1		T226	1
auto[1342177280:1476395007]	auto[1]	65	1			T38	1		T27	2		T232	1
auto[1476395008:1610612735]	auto[0]	44	1			T38	1		T224	1		T265	1
auto[1476395008:1610612735]	auto[1]	73	1			T26	1		T119	1		T136	2
auto[1610612736:1744830463]	auto[0]	59	1			T26	1		T6	1		T59	1
auto[1610612736:1744830463]	auto[1]	45	1			T53	1		T6	1		T54	2
auto[1744830464:1879048191]	auto[0]	49	1			T46	1		T50	1		T95	1
auto[1744830464:1879048191]	auto[1]	57	1			T135	1		T274	1		T53	1
auto[1879048192:2013265919]	auto[0]	53	1			T38	1		T48	2		T23	1
auto[1879048192:2013265919]	auto[1]	65	1			T26	2		T23	1		T41	1
auto[2013265920:2147483647]	auto[0]	45	1			T59	1		T60	1		T327	1
auto[2013265920:2147483647]	auto[1]	62	1			T224	1		T53	1		T59	3
auto[2147483648:2281701375]	auto[0]	54	1			T49	1		T224	1		T70	1
auto[2147483648:2281701375]	auto[1]	46	1			T5	1		T26	1		T27	1
auto[2281701376:2415919103]	auto[0]	49	1			T26	1		T113	1		T70	1
auto[2281701376:2415919103]	auto[1]	51	1			T36	1		T38	1		T119	1
auto[2415919104:2550136831]	auto[0]	51	1			T38	1		T27	1		T70	1
auto[2415919104:2550136831]	auto[1]	51	1			T50	1		T70	1		T53	1
auto[2550136832:2684354559]	auto[0]	49	1			T48	1		T28	1		T59	2
auto[2550136832:2684354559]	auto[1]	53	1			T18	2		T23	2		T232	1
auto[2684354560:2818572287]	auto[0]	55	1			T18	1		T19	1		T107	1
auto[2684354560:2818572287]	auto[1]	55	1			T113	1		T119	1		T136	1
auto[2818572288:2952790015]	auto[0]	59	1			T15	1		T19	1		T53	1
auto[2818572288:2952790015]	auto[1]	56	1			T46	1		T26	1		T27	1
auto[2952790016:3087007743]	auto[0]	57	1			T5	1		T38	1		T51	1
auto[2952790016:3087007743]	auto[1]	52	1			T53	1		T89	1		T59	1
auto[3087007744:3221225471]	auto[0]	59	1			T46	1		T53	1		T317	1
auto[3087007744:3221225471]	auto[1]	71	1			T19	1		T46	1		T94	1
auto[3221225472:3355443199]	auto[0]	61	1			T50	1		T71	1		T29	1
auto[3221225472:3355443199]	auto[1]	49	1			T17	1		T36	1		T224	1
auto[3355443200:3489660927]	auto[0]	68	1			T113	1		T92	1		T95	1
auto[3355443200:3489660927]	auto[1]	43	1			T16	1		T6	1		T391	1
auto[3489660928:3623878655]	auto[0]	56	1			T26	1		T48	1		T70	1
auto[3489660928:3623878655]	auto[1]	50	1			T27	1		T49	1		T146	1
auto[3623878656:3758096383]	auto[0]	59	1			T15	1		T48	1		T226	1
auto[3623878656:3758096383]	auto[1]	53	1			T27	1		T113	1		T225	1
auto[3758096384:3892314111]	auto[0]	61	1			T107	1		T93	1		T29	1
auto[3758096384:3892314111]	auto[1]	57	1			T119	1		T225	1		T53	2
auto[3892314112:4026531839]	auto[0]	62	1			T16	1		T93	1		T60	1
auto[3892314112:4026531839]	auto[1]	58	1			T41	1		T70	1		T225	1
auto[4026531840:4160749567]	auto[0]	64	1			T49	1		T107	1		T53	1
auto[4026531840:4160749567]	auto[1]	61	1			T27	1		T265	1		T53	1
auto[4160749568:4294967295]	auto[0]	62	1			T26	1		T95	1		T52	1
auto[4160749568:4294967295]	auto[1]	52	1			T16	1		T26	1		T226	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1750

1

T5

3

T15

3

T16

1

auto[1]

1806

1

T5

2

T16

3

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T19	1		T46	1		T226	1
auto[134217728:268435455]	111	1			T38	1		T46	1		T27	1
auto[268435456:402653183]	100	1			T16	1		T46	1		T26	1
auto[402653184:536870911]	118	1			T36	1		T113	1		T48	1
auto[536870912:671088639]	107	1			T5	1		T26	3		T113	1
auto[671088640:805306367]	100	1			T38	1		T27	1		T226	1
auto[805306368:939524095]	105	1			T36	1		T26	2		T94	2
auto[939524096:1073741823]	117	1			T50	1		T107	2		T92	1
auto[1073741824:1207959551]	106	1			T26	1		T49	1		T70	1
auto[1207959552:1342177279]	105	1			T15	1		T36	1		T70	1
auto[1342177280:1476395007]	117	1			T27	1		T48	1		T224	1
auto[1476395008:1610612735]	109	1			T38	1		T26	1		T27	2
auto[1610612736:1744830463]	110	1			T5	1		T18	1		T26	1
auto[1744830464:1879048191]	101	1			T119	1		T94	1		T53	2
auto[1879048192:2013265919]	119	1			T16	1		T19	1		T46	1
auto[2013265920:2147483647]	122	1			T26	2		T27	1		T224	1
auto[2147483648:2281701375]	111	1			T15	1		T38	1		T27	2
auto[2281701376:2415919103]	118	1			T38	1		T50	1		T92	3
auto[2415919104:2550136831]	112	1			T17	1		T48	2		T136	1
auto[2550136832:2684354559]	104	1			T27	1		T146	1		T53	4
auto[2684354560:2818572287]	123	1			T26	1		T27	1		T226	1
auto[2818572288:2952790015]	105	1			T38	1		T119	1		T224	1
auto[2952790016:3087007743]	99	1			T113	1		T49	1		T71	1
auto[3087007744:3221225471]	119	1			T16	1		T46	1		T48	1
auto[3221225472:3355443199]	111	1			T18	1		T26	1		T27	2
auto[3355443200:3489660927]	106	1			T38	1		T46	1		T27	1
auto[3489660928:3623878655]	121	1			T5	1		T16	1		T27	1
auto[3623878656:3758096383]	129	1			T38	1		T19	1		T23	1
auto[3758096384:3892314111]	110	1			T5	1		T27	2		T57	1
auto[3892314112:4026531839]	119	1			T5	1		T18	1		T26	1
auto[4026531840:4160749567]	112	1			T15	1		T19	1		T94	1
auto[4160749568:4294967295]	122	1			T18	1		T27	1		T48	1