Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3104

1

T5

5

T15

1

T16

4

auto[1]

286

1

T46

5

T135

10

T136

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T46	1		T27	1		T94	1
auto[134217728:268435455]	125	1			T48	1		T135	1		T70	2
auto[268435456:402653183]	117	1			T18	1		T38	1		T19	1
auto[402653184:536870911]	103	1			T5	1		T46	1		T27	3
auto[536870912:671088639]	99	1			T5	1		T26	1		T27	1
auto[671088640:805306367]	98	1			T15	1		T16	1		T265	1
auto[805306368:939524095]	120	1			T38	1		T46	1		T27	1
auto[939524096:1073741823]	103	1			T94	1		T23	1		T224	1
auto[1073741824:1207959551]	112	1			T18	1		T38	4		T26	1
auto[1207959552:1342177279]	109	1			T48	1		T224	1		T136	1
auto[1342177280:1476395007]	96	1			T5	1		T50	2		T48	1
auto[1476395008:1610612735]	94	1			T226	1		T224	1		T41	1
auto[1610612736:1744830463]	102	1			T16	1		T26	1		T27	1
auto[1744830464:1879048191]	101	1			T16	1		T46	2		T57	1
auto[1879048192:2013265919]	113	1			T27	1		T92	1		T136	1
auto[2013265920:2147483647]	126	1			T26	1		T119	2		T48	1
auto[2147483648:2281701375]	108	1			T38	1		T46	1		T26	1
auto[2281701376:2415919103]	107	1			T46	1		T113	1		T226	1
auto[2415919104:2550136831]	110	1			T27	2		T94	2		T92	1
auto[2550136832:2684354559]	102	1			T36	1		T26	2		T48	3
auto[2684354560:2818572287]	85	1			T26	2		T27	2		T135	1
auto[2818572288:2952790015]	102	1			T17	1		T18	2		T46	1
auto[2952790016:3087007743]	112	1			T46	1		T26	1		T27	1
auto[3087007744:3221225471]	93	1			T23	1		T92	1		T70	1
auto[3221225472:3355443199]	102	1			T26	1		T27	1		T113	1
auto[3355443200:3489660927]	120	1			T16	1		T36	2		T38	1
auto[3489660928:3623878655]	111	1			T46	1		T23	2		T51	1
auto[3623878656:3758096383]	106	1			T5	2		T19	1		T119	1
auto[3758096384:3892314111]	106	1			T19	1		T26	1		T107	1
auto[3892314112:4026531839]	112	1			T26	2		T48	1		T70	1
auto[4026531840:4160749567]	100	1			T135	1		T53	2		T6	1
auto[4160749568:4294967295]	101	1			T27	1		T48	1		T226	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T27	1		T94	1		T222	1
auto[0:134217727]	auto[1]	10	1			T46	1		T138	1		T297	1
auto[134217728:268435455]	auto[0]	118	1			T48	1		T70	2		T136	1
auto[134217728:268435455]	auto[1]	7	1			T135	1		T420	1		T442	1
auto[268435456:402653183]	auto[0]	107	1			T18	1		T38	1		T19	1
auto[268435456:402653183]	auto[1]	10	1			T46	1		T420	1		T328	1
auto[402653184:536870911]	auto[0]	93	1			T5	1		T46	1		T27	3
auto[402653184:536870911]	auto[1]	10	1			T443	1		T269	1		T444	1
auto[536870912:671088639]	auto[0]	90	1			T5	1		T26	1		T27	1
auto[536870912:671088639]	auto[1]	9	1			T137	1		T443	2		T284	1
auto[671088640:805306367]	auto[0]	94	1			T15	1		T16	1		T265	1
auto[671088640:805306367]	auto[1]	4	1			T428	1		T449	1		T454	1
auto[805306368:939524095]	auto[0]	111	1			T38	1		T27	1		T113	2
auto[805306368:939524095]	auto[1]	9	1			T46	1		T135	1		T138	1
auto[939524096:1073741823]	auto[0]	97	1			T94	1		T23	1		T224	1
auto[939524096:1073741823]	auto[1]	6	1			T135	1		T443	1		T442	1
auto[1073741824:1207959551]	auto[0]	103	1			T18	1		T38	4		T26	1
auto[1073741824:1207959551]	auto[1]	9	1			T297	1		T442	1		T444	1
auto[1207959552:1342177279]	auto[0]	100	1			T48	1		T224	1		T136	1
auto[1207959552:1342177279]	auto[1]	9	1			T137	2		T297	2		T391	1
auto[1342177280:1476395007]	auto[0]	89	1			T5	1		T50	2		T48	1
auto[1342177280:1476395007]	auto[1]	7	1			T136	1		T137	2		T138	1
auto[1476395008:1610612735]	auto[0]	91	1			T226	1		T224	1		T41	1
auto[1476395008:1610612735]	auto[1]	3	1			T420	1		T391	1		T371	1
auto[1610612736:1744830463]	auto[0]	91	1			T16	1		T26	1		T27	1
auto[1610612736:1744830463]	auto[1]	11	1			T135	1		T136	1		T420	1
auto[1744830464:1879048191]	auto[0]	93	1			T16	1		T46	1		T57	1
auto[1744830464:1879048191]	auto[1]	8	1			T46	1		T442	2		T294	1
auto[1879048192:2013265919]	auto[0]	93	1			T27	1		T92	1		T136	1
auto[1879048192:2013265919]	auto[1]	20	1			T279	1		T391	3		T427	1
auto[2013265920:2147483647]	auto[0]	115	1			T26	1		T119	2		T48	1
auto[2013265920:2147483647]	auto[1]	11	1			T135	1		T420	1		T297	1
auto[2147483648:2281701375]	auto[0]	97	1			T38	1		T46	1		T26	1
auto[2147483648:2281701375]	auto[1]	11	1			T420	1		T137	1		T269	2
auto[2281701376:2415919103]	auto[0]	101	1			T46	1		T113	1		T226	1
auto[2281701376:2415919103]	auto[1]	6	1			T443	1		T446	2		T426	1
auto[2415919104:2550136831]	auto[0]	100	1			T27	2		T94	2		T92	1
auto[2415919104:2550136831]	auto[1]	10	1			T391	1		T444	1		T441	1
auto[2550136832:2684354559]	auto[0]	92	1			T36	1		T26	2		T48	3
auto[2550136832:2684354559]	auto[1]	10	1			T135	1		T420	2		T443	1
auto[2684354560:2818572287]	auto[0]	76	1			T26	2		T27	2		T135	1
auto[2684354560:2818572287]	auto[1]	9	1			T137	1		T297	1		T348	1
auto[2818572288:2952790015]	auto[0]	96	1			T17	1		T18	2		T46	1
auto[2818572288:2952790015]	auto[1]	6	1			T442	1		T307	1		T448	1
auto[2952790016:3087007743]	auto[0]	104	1			T26	1		T27	1		T94	1
auto[2952790016:3087007743]	auto[1]	8	1			T46	1		T135	1		T391	1
auto[3087007744:3221225471]	auto[0]	83	1			T23	1		T92	1		T70	1
auto[3087007744:3221225471]	auto[1]	10	1			T443	1		T269	1		T442	1
auto[3221225472:3355443199]	auto[0]	94	1			T26	1		T27	1		T113	1
auto[3221225472:3355443199]	auto[1]	8	1			T420	1		T391	1		T284	1
auto[3355443200:3489660927]	auto[0]	113	1			T16	1		T36	2		T38	1
auto[3355443200:3489660927]	auto[1]	7	1			T135	1		T443	1		T387	1
auto[3489660928:3623878655]	auto[0]	101	1			T46	1		T23	2		T51	1
auto[3489660928:3623878655]	auto[1]	10	1			T297	2		T443	1		T441	1
auto[3623878656:3758096383]	auto[0]	93	1			T5	2		T19	1		T119	1
auto[3623878656:3758096383]	auto[1]	13	1			T420	2		T297	1		T391	1
auto[3758096384:3892314111]	auto[0]	95	1			T19	1		T26	1		T107	1
auto[3758096384:3892314111]	auto[1]	11	1			T420	1		T443	1		T269	1
auto[3892314112:4026531839]	auto[0]	104	1			T26	2		T48	1		T70	1
auto[3892314112:4026531839]	auto[1]	8	1			T420	1		T391	1		T428	1
auto[4026531840:4160749567]	auto[0]	92	1			T53	2		T6	1		T89	1
auto[4026531840:4160749567]	auto[1]	8	1			T135	1		T137	1		T297	1
auto[4160749568:4294967295]	auto[0]	93	1			T27	1		T48	1		T226	2
auto[4160749568:4294967295]	auto[1]	8	1			T135	1		T420	1		T391	1