Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2947

1

T4

3

T14

3

T15

3

auto[1]

258

1

T91

8

T70

3

T73

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T4	1		T60	2		T252	1
auto[134217728:268435455]	99	1			T15	1		T114	1		T126	1
auto[268435456:402653183]	119	1			T14	1		T38	1		T39	1
auto[402653184:536870911]	113	1			T5	1		T91	1		T26	1
auto[536870912:671088639]	106	1			T38	2		T71	1		T73	1
auto[671088640:805306367]	108	1			T17	1		T129	1		T60	1
auto[805306368:939524095]	102	1			T91	1		T205	2		T60	2
auto[939524096:1073741823]	109	1			T129	1		T39	1		T5	1
auto[1073741824:1207959551]	91	1			T38	1		T207	1		T73	1
auto[1207959552:1342177279]	101	1			T5	1		T91	1		T26	1
auto[1342177280:1476395007]	108	1			T48	2		T58	1		T60	1
auto[1476395008:1610612735]	95	1			T19	1		T60	2		T93	1
auto[1610612736:1744830463]	98	1			T39	1		T73	1		T29	1
auto[1744830464:1879048191]	90	1			T18	1		T38	1		T70	1
auto[1879048192:2013265919]	122	1			T91	1		T73	1		T95	2
auto[2013265920:2147483647]	99	1			T19	1		T71	1		T60	1
auto[2147483648:2281701375]	99	1			T114	1		T60	2		T64	2
auto[2281701376:2415919103]	100	1			T91	1		T207	1		T126	1
auto[2415919104:2550136831]	103	1			T91	2		T48	1		T60	2
auto[2550136832:2684354559]	100	1			T91	2		T205	1		T58	1
auto[2684354560:2818572287]	102	1			T116	1		T71	1		T48	1
auto[2818572288:2952790015]	88	1			T38	1		T70	1		T73	1
auto[2952790016:3087007743]	82	1			T207	1		T126	1		T60	1
auto[3087007744:3221225471]	101	1			T4	1		T14	1		T114	1
auto[3221225472:3355443199]	101	1			T19	1		T48	1		T60	1
auto[3355443200:3489660927]	93	1			T39	1		T5	1		T114	1
auto[3489660928:3623878655]	85	1			T15	1		T39	1		T60	1
auto[3623878656:3758096383]	103	1			T14	1		T39	1		T5	1
auto[3758096384:3892314111]	104	1			T15	1		T26	1		T205	1
auto[3892314112:4026531839]	90	1			T38	1		T64	2		T93	1
auto[4026531840:4160749567]	90	1			T39	1		T91	1		T114	1
auto[4160749568:4294967295]	108	1			T4	1		T19	2		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	91	1			T4	1		T60	2		T252	1
auto[0:134217727]	auto[1]	5	1			T156	1		T290	1		T369	1
auto[134217728:268435455]	auto[0]	93	1			T15	1		T114	1		T126	1
auto[134217728:268435455]	auto[1]	6	1			T70	1		T273	1		T344	1
auto[268435456:402653183]	auto[0]	109	1			T14	1		T38	1		T39	1
auto[268435456:402653183]	auto[1]	10	1			T93	1		T280	2		T433	1
auto[402653184:536870911]	auto[0]	106	1			T5	1		T26	1		T207	2
auto[402653184:536870911]	auto[1]	7	1			T91	1		T271	1		T344	1
auto[536870912:671088639]	auto[0]	96	1			T38	2		T71	1		T65	1
auto[536870912:671088639]	auto[1]	10	1			T73	1		T78	1		T432	1
auto[671088640:805306367]	auto[0]	103	1			T17	1		T129	1		T60	1
auto[671088640:805306367]	auto[1]	5	1			T156	1		T78	1		T353	2
auto[805306368:939524095]	auto[0]	97	1			T205	2		T60	2		T94	2
auto[805306368:939524095]	auto[1]	5	1			T91	1		T78	2		T369	1
auto[939524096:1073741823]	auto[0]	102	1			T129	1		T39	1		T5	1
auto[939524096:1073741823]	auto[1]	7	1			T91	1		T70	1		T302	1
auto[1073741824:1207959551]	auto[0]	82	1			T38	1		T207	1		T58	1
auto[1073741824:1207959551]	auto[1]	9	1			T73	1		T302	2		T270	1
auto[1207959552:1342177279]	auto[0]	93	1			T5	1		T26	1		T28	1
auto[1207959552:1342177279]	auto[1]	8	1			T91	1		T266	1		T443	1
auto[1342177280:1476395007]	auto[0]	97	1			T48	2		T58	1		T60	1
auto[1342177280:1476395007]	auto[1]	11	1			T93	2		T156	1		T78	1
auto[1476395008:1610612735]	auto[0]	91	1			T19	1		T60	2		T93	1
auto[1476395008:1610612735]	auto[1]	4	1			T290	1		T310	1		T369	1
auto[1610612736:1744830463]	auto[0]	86	1			T39	1		T73	1		T29	1
auto[1610612736:1744830463]	auto[1]	12	1			T78	1		T302	1		T344	1
auto[1744830464:1879048191]	auto[0]	81	1			T18	1		T38	1		T70	1
auto[1744830464:1879048191]	auto[1]	9	1			T73	1		T76	1		T432	1
auto[1879048192:2013265919]	auto[0]	118	1			T91	1		T73	1		T95	2
auto[1879048192:2013265919]	auto[1]	4	1			T271	1		T348	1		T344	1
auto[2013265920:2147483647]	auto[0]	93	1			T19	1		T71	1		T60	1
auto[2013265920:2147483647]	auto[1]	6	1			T249	1		T78	1		T348	1
auto[2147483648:2281701375]	auto[0]	93	1			T114	1		T60	2		T64	2
auto[2147483648:2281701375]	auto[1]	6	1			T156	1		T310	1		T352	1
auto[2281701376:2415919103]	auto[0]	90	1			T91	1		T207	1		T126	1
auto[2281701376:2415919103]	auto[1]	10	1			T70	1		T156	2		T348	1
auto[2415919104:2550136831]	auto[0]	98	1			T91	1		T48	1		T60	2
auto[2415919104:2550136831]	auto[1]	5	1			T91	1		T78	1		T290	1
auto[2550136832:2684354559]	auto[0]	93	1			T205	1		T58	1		T210	1
auto[2550136832:2684354559]	auto[1]	7	1			T91	2		T311	1		T296	1
auto[2684354560:2818572287]	auto[0]	92	1			T116	1		T71	1		T48	1
auto[2684354560:2818572287]	auto[1]	10	1			T64	1		T93	1		T273	1
auto[2818572288:2952790015]	auto[0]	81	1			T38	1		T70	1		T49	1
auto[2818572288:2952790015]	auto[1]	7	1			T73	1		T271	1		T274	1
auto[2952790016:3087007743]	auto[0]	76	1			T207	1		T126	1		T60	1
auto[2952790016:3087007743]	auto[1]	6	1			T156	1		T250	1		T280	1
auto[3087007744:3221225471]	auto[0]	91	1			T4	1		T14	1		T114	1
auto[3087007744:3221225471]	auto[1]	10	1			T64	1		T344	1		T296	2
auto[3221225472:3355443199]	auto[0]	89	1			T19	1		T48	1		T60	1
auto[3221225472:3355443199]	auto[1]	12	1			T64	1		T78	1		T270	1
auto[3355443200:3489660927]	auto[0]	83	1			T39	1		T5	1		T114	1
auto[3355443200:3489660927]	auto[1]	10	1			T311	2		T266	1		T290	1
auto[3489660928:3623878655]	auto[0]	81	1			T15	1		T39	1		T60	1
auto[3489660928:3623878655]	auto[1]	4	1			T79	1		T250	1		T329	1
auto[3623878656:3758096383]	auto[0]	93	1			T14	1		T39	1		T5	1
auto[3623878656:3758096383]	auto[1]	10	1			T156	1		T311	1		T344	1
auto[3758096384:3892314111]	auto[0]	91	1			T15	1		T26	1		T205	1
auto[3758096384:3892314111]	auto[1]	13	1			T73	1		T93	1		T270	1
auto[3892314112:4026531839]	auto[0]	79	1			T38	1		T64	1		T76	1
auto[3892314112:4026531839]	auto[1]	11	1			T64	1		T93	1		T270	1
auto[4026531840:4160749567]	auto[0]	85	1			T39	1		T114	1		T60	1
auto[4026531840:4160749567]	auto[1]	5	1			T91	1		T73	1		T280	1
auto[4160749568:4294967295]	auto[0]	94	1			T4	1		T19	2		T38	1
auto[4160749568:4294967295]	auto[1]	14	1			T78	1		T348	2		T344	2