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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1616 1 T4 2 T14 2 T15 4
auto[1] 1756 1 T4 1 T14 1 T17 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 110 1 T18 1 T19 2 T38 3
auto[134217728:268435455] 109 1 T19 1 T39 1 T70 1
auto[268435456:402653183] 107 1 T19 1 T38 1 T205 1
auto[402653184:536870911] 107 1 T92 1 T114 1 T73 1
auto[536870912:671088639] 109 1 T26 1 T58 1 T101 1
auto[671088640:805306367] 119 1 T74 1 T116 1 T91 1
auto[805306368:939524095] 107 1 T17 1 T38 1 T39 1
auto[939524096:1073741823] 96 1 T39 1 T5 1 T91 1
auto[1073741824:1207959551] 120 1 T129 1 T48 1 T60 2
auto[1207959552:1342177279] 95 1 T58 1 T60 2 T66 1
auto[1342177280:1476395007] 96 1 T39 1 T126 1 T60 4
auto[1476395008:1610612735] 100 1 T14 1 T5 1 T92 1
auto[1610612736:1744830463] 97 1 T14 1 T19 1 T60 3
auto[1744830464:1879048191] 117 1 T58 1 T60 2 T65 1
auto[1879048192:2013265919] 126 1 T26 1 T205 1 T60 1
auto[2013265920:2147483647] 84 1 T15 1 T39 1 T207 1
auto[2147483648:2281701375] 97 1 T4 1 T15 1 T129 1
auto[2281701376:2415919103] 104 1 T15 1 T5 1 T207 1
auto[2415919104:2550136831] 90 1 T5 2 T207 1 T48 1
auto[2550136832:2684354559] 103 1 T91 1 T28 1 T64 1
auto[2684354560:2818572287] 104 1 T205 1 T71 1 T73 1
auto[2818572288:2952790015] 105 1 T126 1 T94 4 T259 1
auto[2952790016:3087007743] 104 1 T74 2 T38 1 T60 2
auto[3087007744:3221225471] 112 1 T71 1 T48 1 T60 3
auto[3221225472:3355443199] 109 1 T4 1 T70 1 T73 1
auto[3355443200:3489660927] 100 1 T114 1 T70 1 T48 1
auto[3489660928:3623878655] 110 1 T114 1 T60 2 T94 2
auto[3623878656:3758096383] 92 1 T4 1 T14 1 T38 1
auto[3758096384:3892314111] 118 1 T38 1 T39 1 T26 1
auto[3892314112:4026531839] 100 1 T15 1 T5 1 T60 4
auto[4026531840:4160749567] 117 1 T5 1 T126 1 T48 1
auto[4160749568:4294967295] 108 1 T39 1 T114 1 T60 5


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 56 1 T19 2 T38 3 T60 2
auto[0:134217727] auto[1] 54 1 T18 1 T207 1 T60 1
auto[134217728:268435455] auto[0] 49 1 T19 1 T101 1 T20 1
auto[134217728:268435455] auto[1] 60 1 T39 1 T70 1 T58 1
auto[268435456:402653183] auto[0] 55 1 T38 1 T60 1 T65 1
auto[268435456:402653183] auto[1] 52 1 T19 1 T205 1 T208 1
auto[402653184:536870911] auto[0] 50 1 T92 1 T114 1 T251 1
auto[402653184:536870911] auto[1] 57 1 T73 1 T48 1 T29 1
auto[536870912:671088639] auto[0] 42 1 T58 1 T101 1 T94 1
auto[536870912:671088639] auto[1] 67 1 T26 1 T23 1 T269 1
auto[671088640:805306367] auto[0] 61 1 T91 1 T205 1 T114 1
auto[671088640:805306367] auto[1] 58 1 T74 1 T116 1 T138 1
auto[805306368:939524095] auto[0] 54 1 T38 1 T207 1 T71 2
auto[805306368:939524095] auto[1] 53 1 T17 1 T39 1 T60 1
auto[939524096:1073741823] auto[0] 48 1 T39 1 T5 1 T91 1
auto[939524096:1073741823] auto[1] 48 1 T26 1 T60 1 T102 1
auto[1073741824:1207959551] auto[0] 52 1 T60 1 T65 1 T208 1
auto[1073741824:1207959551] auto[1] 68 1 T129 1 T48 1 T60 1
auto[1207959552:1342177279] auto[0] 47 1 T60 1 T101 1 T134 1
auto[1207959552:1342177279] auto[1] 48 1 T58 1 T60 1 T66 1
auto[1342177280:1476395007] auto[0] 44 1 T39 1 T126 1 T60 1
auto[1342177280:1476395007] auto[1] 52 1 T60 3 T206 1 T210 1
auto[1476395008:1610612735] auto[0] 57 1 T14 1 T5 1 T92 1
auto[1476395008:1610612735] auto[1] 43 1 T49 1 T24 1 T436 1
auto[1610612736:1744830463] auto[0] 37 1 T93 1 T94 1 T6 1
auto[1610612736:1744830463] auto[1] 60 1 T14 1 T19 1 T60 3
auto[1744830464:1879048191] auto[0] 58 1 T65 1 T95 1 T20 1
auto[1744830464:1879048191] auto[1] 59 1 T58 1 T60 2 T101 1
auto[1879048192:2013265919] auto[0] 61 1 T205 1 T60 1 T66 1
auto[1879048192:2013265919] auto[1] 65 1 T26 1 T95 1 T94 1
auto[2013265920:2147483647] auto[0] 37 1 T15 1 T39 1 T28 1
auto[2013265920:2147483647] auto[1] 47 1 T207 1 T48 1 T23 1
auto[2147483648:2281701375] auto[0] 40 1 T4 1 T15 1 T114 1
auto[2147483648:2281701375] auto[1] 57 1 T129 1 T259 1 T77 1
auto[2281701376:2415919103] auto[0] 54 1 T15 1 T5 1 T60 1
auto[2281701376:2415919103] auto[1] 50 1 T207 1 T64 1 T94 1
auto[2415919104:2550136831] auto[0] 46 1 T5 1 T277 1 T222 1
auto[2415919104:2550136831] auto[1] 44 1 T5 1 T207 1 T48 1
auto[2550136832:2684354559] auto[0] 55 1 T28 1 T64 1 T50 1
auto[2550136832:2684354559] auto[1] 48 1 T91 1 T29 1 T49 1
auto[2684354560:2818572287] auto[0] 44 1 T205 1 T71 1 T60 1
auto[2684354560:2818572287] auto[1] 60 1 T73 1 T48 1 T60 1
auto[2818572288:2952790015] auto[0] 49 1 T126 1 T94 2 T259 1
auto[2818572288:2952790015] auto[1] 56 1 T94 2 T150 1 T156 1
auto[2952790016:3087007743] auto[0] 50 1 T74 2 T38 1 T76 1
auto[2952790016:3087007743] auto[1] 54 1 T60 2 T65 1 T206 1
auto[3087007744:3221225471] auto[0] 56 1 T29 1 T102 1 T94 1
auto[3087007744:3221225471] auto[1] 56 1 T71 1 T48 1 T60 3
auto[3221225472:3355443199] auto[0] 58 1 T58 1 T65 1 T76 2
auto[3221225472:3355443199] auto[1] 51 1 T4 1 T70 1 T73 1
auto[3355443200:3489660927] auto[0] 47 1 T114 1 T60 2 T138 1
auto[3355443200:3489660927] auto[1] 53 1 T70 1 T48 1 T208 1
auto[3489660928:3623878655] auto[0] 55 1 T114 1 T60 2 T94 1
auto[3489660928:3623878655] auto[1] 55 1 T94 1 T307 1 T6 1
auto[3623878656:3758096383] auto[0] 42 1 T4 1 T14 1 T5 1
auto[3623878656:3758096383] auto[1] 50 1 T38 1 T48 2 T249 1
auto[3758096384:3892314111] auto[0] 58 1 T38 1 T39 1 T60 1
auto[3758096384:3892314111] auto[1] 60 1 T26 1 T71 1 T64 1
auto[3892314112:4026531839] auto[0] 50 1 T15 1 T60 1 T49 1
auto[3892314112:4026531839] auto[1] 50 1 T5 1 T60 3 T29 1
auto[4026531840:4160749567] auto[0] 53 1 T5 1 T48 1 T206 1
auto[4026531840:4160749567] auto[1] 64 1 T126 1 T209 1 T95 1
auto[4160749568:4294967295] auto[0] 51 1 T114 1 T60 3 T94 1
auto[4160749568:4294967295] auto[1] 57 1 T39 1 T60 2 T94 2

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