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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6830 1 T4 6 T14 6 T15 5
auto[1] 257 1 T91 3 T70 1 T73 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2835 1 T4 4 T14 3 T15 2
auto[134217728:268435455] 145 1 T19 1 T129 1 T92 1
auto[268435456:402653183] 160 1 T39 1 T5 1 T91 1
auto[402653184:536870911] 134 1 T5 1 T26 2 T207 1
auto[536870912:671088639] 151 1 T19 1 T39 1 T205 1
auto[671088640:805306367] 145 1 T15 1 T18 1 T38 2
auto[805306368:939524095] 145 1 T38 1 T39 1 T5 1
auto[939524096:1073741823] 145 1 T38 1 T39 1 T26 1
auto[1073741824:1207959551] 127 1 T207 1 T71 1 T58 1
auto[1207959552:1342177279] 126 1 T129 1 T38 1 T39 1
auto[1342177280:1476395007] 124 1 T38 1 T26 1 T207 1
auto[1476395008:1610612735] 137 1 T17 1 T19 1 T207 1
auto[1610612736:1744830463] 151 1 T4 1 T38 1 T5 1
auto[1744830464:1879048191] 152 1 T38 1 T91 1 T114 2
auto[1879048192:2013265919] 129 1 T129 1 T91 1 T48 2
auto[2013265920:2147483647] 128 1 T14 1 T205 1 T70 1
auto[2147483648:2281701375] 133 1 T60 1 T95 1 T30 1
auto[2281701376:2415919103] 120 1 T14 1 T15 1 T5 1
auto[2415919104:2550136831] 141 1 T38 1 T114 2 T58 1
auto[2550136832:2684354559] 132 1 T38 1 T26 1 T73 1
auto[2684354560:2818572287] 139 1 T14 1 T116 1 T71 1
auto[2818572288:2952790015] 142 1 T19 1 T5 1 T91 1
auto[2952790016:3087007743] 124 1 T38 1 T126 1 T58 1
auto[3087007744:3221225471] 135 1 T19 1 T39 1 T73 1
auto[3221225472:3355443199] 121 1 T39 1 T26 1 T70 1
auto[3355443200:3489660927] 128 1 T4 1 T71 1 T60 1
auto[3489660928:3623878655] 121 1 T38 1 T71 1 T60 1
auto[3623878656:3758096383] 123 1 T15 1 T19 1 T207 1
auto[3758096384:3892314111] 150 1 T38 2 T126 1 T70 1
auto[3892314112:4026531839] 131 1 T19 1 T114 1 T28 1
auto[4026531840:4160749567] 146 1 T39 2 T26 1 T114 2
auto[4160749568:4294967295] 167 1 T26 2 T48 1 T60 6


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2828 1 T4 4 T14 3 T15 2
auto[0:134217727] auto[1] 7 1 T93 1 T249 1 T271 2
auto[134217728:268435455] auto[0] 135 1 T19 1 T129 1 T92 1
auto[134217728:268435455] auto[1] 10 1 T394 1 T432 1 T274 1
auto[268435456:402653183] auto[0] 153 1 T39 1 T5 1 T26 1
auto[268435456:402653183] auto[1] 7 1 T91 1 T344 1 T280 1
auto[402653184:536870911] auto[0] 129 1 T5 1 T26 2 T207 1
auto[402653184:536870911] auto[1] 5 1 T437 1 T315 1 T438 1
auto[536870912:671088639] auto[0] 143 1 T19 1 T39 1 T205 1
auto[536870912:671088639] auto[1] 8 1 T432 1 T290 1 T296 1
auto[671088640:805306367] auto[0] 135 1 T15 1 T18 1 T38 2
auto[671088640:805306367] auto[1] 10 1 T78 2 T302 1 T250 1
auto[805306368:939524095] auto[0] 132 1 T38 1 T39 1 T5 1
auto[805306368:939524095] auto[1] 13 1 T64 2 T93 1 T249 2
auto[939524096:1073741823] auto[0] 134 1 T38 1 T39 1 T26 1
auto[939524096:1073741823] auto[1] 11 1 T156 1 T79 1 T348 1
auto[1073741824:1207959551] auto[0] 119 1 T207 1 T71 1 T58 1
auto[1073741824:1207959551] auto[1] 8 1 T250 1 T266 1 T434 1
auto[1207959552:1342177279] auto[0] 116 1 T129 1 T38 1 T39 1
auto[1207959552:1342177279] auto[1] 10 1 T91 1 T73 1 T394 1
auto[1342177280:1476395007] auto[0] 118 1 T38 1 T26 1 T207 1
auto[1342177280:1476395007] auto[1] 6 1 T64 1 T432 1 T315 1
auto[1476395008:1610612735] auto[0] 133 1 T17 1 T19 1 T207 1
auto[1476395008:1610612735] auto[1] 4 1 T93 1 T302 1 T270 1
auto[1610612736:1744830463] auto[0] 141 1 T4 1 T38 1 T5 1
auto[1610612736:1744830463] auto[1] 10 1 T290 2 T434 1 T369 4
auto[1744830464:1879048191] auto[0] 145 1 T38 1 T91 1 T114 2
auto[1744830464:1879048191] auto[1] 7 1 T348 1 T432 1 T280 1
auto[1879048192:2013265919] auto[0] 124 1 T129 1 T91 1 T48 2
auto[1879048192:2013265919] auto[1] 5 1 T280 1 T266 1 T296 1
auto[2013265920:2147483647] auto[0] 120 1 T14 1 T205 1 T70 1
auto[2013265920:2147483647] auto[1] 8 1 T250 1 T432 1 T266 1
auto[2147483648:2281701375] auto[0] 128 1 T60 1 T95 1 T30 1
auto[2147483648:2281701375] auto[1] 5 1 T156 1 T310 1 T439 1
auto[2281701376:2415919103] auto[0] 114 1 T14 1 T15 1 T5 1
auto[2281701376:2415919103] auto[1] 6 1 T78 2 T344 1 T280 1
auto[2415919104:2550136831] auto[0] 138 1 T38 1 T114 2 T58 1
auto[2415919104:2550136831] auto[1] 3 1 T344 1 T280 1 T431 1
auto[2550136832:2684354559] auto[0] 128 1 T38 1 T26 1 T73 1
auto[2550136832:2684354559] auto[1] 4 1 T79 1 T394 1 T326 1
auto[2684354560:2818572287] auto[0] 134 1 T14 1 T116 1 T71 1
auto[2684354560:2818572287] auto[1] 5 1 T78 1 T394 1 T435 3
auto[2818572288:2952790015] auto[0] 127 1 T19 1 T5 1 T73 1
auto[2818572288:2952790015] auto[1] 15 1 T91 1 T73 2 T271 1
auto[2952790016:3087007743] auto[0] 113 1 T38 1 T126 1 T58 1
auto[2952790016:3087007743] auto[1] 11 1 T93 1 T271 1 T344 1
auto[3087007744:3221225471] auto[0] 128 1 T19 1 T39 1 T48 1
auto[3087007744:3221225471] auto[1] 7 1 T73 1 T271 1 T311 1
auto[3221225472:3355443199] auto[0] 108 1 T39 1 T26 1 T60 2
auto[3221225472:3355443199] auto[1] 13 1 T70 1 T344 1 T290 1
auto[3355443200:3489660927] auto[0] 122 1 T4 1 T71 1 T60 1
auto[3355443200:3489660927] auto[1] 6 1 T432 1 T274 1 T437 1
auto[3489660928:3623878655] auto[0] 110 1 T38 1 T71 1 T60 1
auto[3489660928:3623878655] auto[1] 11 1 T271 1 T311 1 T270 2
auto[3623878656:3758096383] auto[0] 115 1 T15 1 T19 1 T207 1
auto[3623878656:3758096383] auto[1] 8 1 T93 1 T249 1 T79 1
auto[3758096384:3892314111] auto[0] 142 1 T38 2 T126 1 T70 1
auto[3758096384:3892314111] auto[1] 8 1 T270 1 T433 1 T434 1
auto[3892314112:4026531839] auto[0] 123 1 T19 1 T114 1 T28 1
auto[3892314112:4026531839] auto[1] 8 1 T93 2 T249 1 T78 1
auto[4026531840:4160749567] auto[0] 139 1 T39 2 T26 1 T114 2
auto[4026531840:4160749567] auto[1] 7 1 T271 1 T432 1 T290 1
auto[4160749568:4294967295] auto[0] 156 1 T26 2 T48 1 T60 6
auto[4160749568:4294967295] auto[1] 11 1 T302 1 T344 1 T432 1

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