KMAC/MASKED Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.661m 4.998ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.170s 323.324us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.250s 131.634us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 20.640s 3.718ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 11.220s 540.681us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.280s 106.672us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.250s 131.634us 20 20 100.00
kmac_csr_aliasing 11.220s 540.681us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.760s 11.351us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.390s 27.411us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 58.293m 403.670ms 49 50 98.00
V2 burst_write kmac_burst_write 28.358m 15.646ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 43.062m 426.305ms 50 50 100.00
kmac_test_vectors_sha3_256 40.669m 1.351s 50 50 100.00
kmac_test_vectors_sha3_384 34.689m 641.487ms 50 50 100.00
kmac_test_vectors_sha3_512 25.381m 325.679ms 49 50 98.00
kmac_test_vectors_shake_128 1.970h 3.733s 49 50 98.00
kmac_test_vectors_shake_256 1.673h 3.044s 48 50 96.00
kmac_test_vectors_kmac 7.020s 238.607us 49 50 98.00
kmac_test_vectors_kmac_xof 7.270s 270.735us 50 50 100.00
V2 sideload kmac_sideload 9.181m 91.446ms 50 50 100.00
V2 app kmac_app 7.580m 13.939ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 6.102m 12.742ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 6.897m 72.148ms 49 50 98.00
V2 error kmac_error 8.393m 82.523ms 48 50 96.00
V2 key_error kmac_key_error 8.910s 4.931ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 45.950s 6.027ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 23.230s 1.074ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.188m 13.989ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 26.510s 3.661ms 50 50 100.00
V2 stress_all kmac_stress_all 49.593m 60.786ms 46 50 92.00
V2 intr_test kmac_intr_test 0.880s 34.536us 50 50 100.00
V2 alert_test kmac_alert_test 0.920s 26.086us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.640s 137.163us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.640s 137.163us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.170s 323.324us 5 5 100.00
kmac_csr_rw 1.250s 131.634us 20 20 100.00
kmac_csr_aliasing 11.220s 540.681us 5 5 100.00
kmac_same_csr_outstanding 2.920s 708.263us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.170s 323.324us 5 5 100.00
kmac_csr_rw 1.250s 131.634us 20 20 100.00
kmac_csr_aliasing 11.220s 540.681us 5 5 100.00
kmac_same_csr_outstanding 2.920s 708.263us 20 20 100.00
V2 TOTAL 1037 1050 98.76
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.150s 193.959us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.150s 193.959us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.150s 193.959us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.150s 193.959us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 5.960s 358.540us 19 20 95.00
V2S tl_intg_err kmac_sec_cm 1.820m 33.814ms 5 5 100.00
kmac_tl_intg_err 5.370s 271.546us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.370s 271.546us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 26.510s 3.661ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.661m 4.998ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 9.181m 91.446ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.150s 193.959us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.820m 33.814ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.820m 33.814ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.820m 33.814ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.661m 4.998ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 26.510s 3.661ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.820m 33.814ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.405m 147.141ms 8 10 80.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.661m 4.998ms 50 50 100.00
V2S TOTAL 72 75 96.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 48.328m 376.983ms 37 50 74.00
V3 TOTAL 37 50 74.00
TOTAL 1261 1290 97.75

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 17 68.00
V2S 5 5 3 60.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.06 98.40 93.36 99.93 94.55 96.03 98.87 98.31

Failure Buckets

Past Results