e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.661m | 4.998ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 323.324us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.250s | 131.634us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 20.640s | 3.718ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 11.220s | 540.681us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.280s | 106.672us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 131.634us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 11.220s | 540.681us | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.760s | 11.351us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.390s | 27.411us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 58.293m | 403.670ms | 49 | 50 | 98.00 |
V2 | burst_write | kmac_burst_write | 28.358m | 15.646ms | 50 | 50 | 100.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 43.062m | 426.305ms | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 40.669m | 1.351s | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 34.689m | 641.487ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 25.381m | 325.679ms | 49 | 50 | 98.00 | ||
kmac_test_vectors_shake_128 | 1.970h | 3.733s | 49 | 50 | 98.00 | ||
kmac_test_vectors_shake_256 | 1.673h | 3.044s | 48 | 50 | 96.00 | ||
kmac_test_vectors_kmac | 7.020s | 238.607us | 49 | 50 | 98.00 | ||
kmac_test_vectors_kmac_xof | 7.270s | 270.735us | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 9.181m | 91.446ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 7.580m | 13.939ms | 50 | 50 | 100.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 6.102m | 12.742ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 6.897m | 72.148ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 8.393m | 82.523ms | 48 | 50 | 96.00 |
V2 | key_error | kmac_key_error | 8.910s | 4.931ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 45.950s | 6.027ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 23.230s | 1.074ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.188m | 13.989ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 26.510s | 3.661ms | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 49.593m | 60.786ms | 46 | 50 | 92.00 |
V2 | intr_test | kmac_intr_test | 0.880s | 34.536us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.920s | 26.086us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.640s | 137.163us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.640s | 137.163us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 323.324us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 131.634us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.220s | 540.681us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.920s | 708.263us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 323.324us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 131.634us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.220s | 540.681us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.920s | 708.263us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1037 | 1050 | 98.76 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.150s | 193.959us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.150s | 193.959us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.150s | 193.959us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.150s | 193.959us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.960s | 358.540us | 19 | 20 | 95.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.820m | 33.814ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.370s | 271.546us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.370s | 271.546us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 26.510s | 3.661ms | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.661m | 4.998ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 9.181m | 91.446ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.150s | 193.959us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.820m | 33.814ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.820m | 33.814ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.820m | 33.814ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.661m | 4.998ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 26.510s | 3.661ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.820m | 33.814ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.405m | 147.141ms | 8 | 10 | 80.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.661m | 4.998ms | 50 | 50 | 100.00 |
V2S | TOTAL | 72 | 75 | 96.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 48.328m | 376.983ms | 37 | 50 | 74.00 |
V3 | TOTAL | 37 | 50 | 74.00 | |||
TOTAL | 1261 | 1290 | 97.75 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 17 | 68.00 |
V2S | 5 | 5 | 3 | 60.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.06 | 98.40 | 93.36 | 99.93 | 94.55 | 96.03 | 98.87 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 9 failures:
0.kmac_stress_all_with_rand_reset.1355266626
Line 448, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21549116690 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 21549116690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.kmac_stress_all_with_rand_reset.2750763332
Line 1256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90837314253 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 90837314253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 6 failures:
Test kmac_stress_all has 2 failures.
2.kmac_stress_all.2371221074
Line 437, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log
UVM_ERROR @ 27403901774 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 27403901774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.kmac_stress_all.2357619894
Line 326, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
UVM_ERROR @ 13376451559 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 13376451559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 2 failures.
28.kmac_test_vectors_shake_256.2649083688
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 27144965 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 27144965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_test_vectors_shake_256.2951439909
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 38628097 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 38628097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_512 has 1 failures.
29.kmac_test_vectors_sha3_512.3703919527
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 25399577 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 25399577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
47.kmac_test_vectors_kmac.4060434138
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 46787784 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 46787784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 5 failures:
Test kmac_stress_all_with_rand_reset has 2 failures.
9.kmac_stress_all_with_rand_reset.1359115369
Line 356, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11317318676 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 11317318676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.kmac_stress_all_with_rand_reset.3322166985
Line 636, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 52095780065 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 52095780065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 2 failures.
16.kmac_stress_all.2956433867
Line 473, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log
UVM_FATAL @ 192498137083 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 192498137083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.kmac_stress_all.1054709519
Line 608, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest/run.log
UVM_FATAL @ 290492651698 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 290492651698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
20.kmac_error.1521740826
Line 350, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log
UVM_FATAL @ 10059128639 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10059128639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 4 failures:
Test kmac_mubi has 2 failures.
3.kmac_mubi.2411392058
Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mubi/latest/run.log
UVM_FATAL @ 12158364777 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (11 [0xb] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 12158364777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.kmac_mubi.1447396611
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_mubi/latest/run.log
UVM_FATAL @ 1468576381 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (249 [0xf9] vs 184 [0xb8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1468576381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
35.kmac_entropy_refresh.2804669680
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 19152817872 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (189 [0xbd] vs 222 [0xde]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 19152817872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
40.kmac_stress_all_with_rand_reset.244940871
Line 574, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 223881040243 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (149 [0x95] vs 57 [0x39]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 223881040243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
Test kmac_long_msg_and_output has 1 failures.
8.kmac_long_msg_and_output.838316062
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
Job ID: smart:de5d1b49-cadc-4604-ab8f-b01639281c57
Test kmac_test_vectors_shake_128 has 1 failures.
30.kmac_test_vectors_shake_128.4051362022
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:bbe9b898-2d6f-48cc-ad4f-6b63d7f10874
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
16.kmac_error.36462167
Line 336, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
has 1 failures:
16.kmac_shadow_reg_errors_with_csr_rw.752693651
Line 247, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 67354635 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2839176607 [0xa93a659f] vs 0 [0x0]) Regname: kmac_reg_block.prefix_7 reset value: 0x0
UVM_INFO @ 67354635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 1 failures:
43.kmac_stress_all_with_rand_reset.1805893045
Line 959, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 80121989203 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.kmac_entropy_refresh_vseq.kmac_app_seq.host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 80121989203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---