83db9403d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.503m | 4.214ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.200s | 58.825us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.280s | 58.342us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.780s | 4.683ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 11.120s | 562.813us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.480s | 440.184us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.280s | 58.342us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 11.120s | 562.813us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.800s | 15.750us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.490s | 56.442us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 58.390m | 517.766ms | 49 | 50 | 98.00 |
| V2 | burst_write | kmac_burst_write | 25.302m | 78.777ms | 48 | 50 | 96.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 43.904m | 405.244ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 41.054m | 728.768ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 32.964m | 297.839ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 24.302m | 203.966ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.863h | 1.305s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.557h | 233.156ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 7.410s | 2.870ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.560s | 1.300ms | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 9.171m | 62.127ms | 49 | 50 | 98.00 |
| V2 | app | kmac_app | 7.533m | 25.710ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.291m | 102.829ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.641m | 72.329ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 8.750m | 60.147ms | 48 | 50 | 96.00 |
| V2 | key_error | kmac_key_error | 8.200s | 4.819ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 45.020s | 1.678ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 51.410s | 3.025ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.212m | 27.785ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 59.730s | 7.497ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 1.176h | 169.327ms | 48 | 50 | 96.00 |
| V2 | intr_test | kmac_intr_test | 0.900s | 21.476us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.940s | 85.534us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.440s | 118.888us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.440s | 118.888us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.200s | 58.825us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.280s | 58.342us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.120s | 562.813us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.900s | 257.262us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.200s | 58.825us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.280s | 58.342us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.120s | 562.813us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.900s | 257.262us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1039 | 1050 | 98.95 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.550s | 1.158ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.550s | 1.158ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.550s | 1.158ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.550s | 1.158ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.480s | 730.632us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.147m | 37.261ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 6.250s | 1.087ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.250s | 1.087ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 59.730s | 7.497ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.503m | 4.214ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.171m | 62.127ms | 49 | 50 | 98.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.550s | 1.158ms | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.147m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.147m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.147m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.503m | 4.214ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 59.730s | 7.497ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.147m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.759m | 19.321ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.503m | 4.214ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 58.634m | 323.984ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 31 | 50 | 62.00 | |||
| TOTAL | 1259 | 1290 | 97.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.32 | 98.40 | 93.36 | 99.93 | 96.36 | 96.03 | 98.87 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 13 failures:
7.kmac_stress_all_with_rand_reset.2355897814
Line 442, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8569467170 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 8569467170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.kmac_stress_all_with_rand_reset.3078673119
Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3933103847 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 3933103847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 9 failures:
Test kmac_stress_all_with_rand_reset has 6 failures.
2.kmac_stress_all_with_rand_reset.938731782
Line 685, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 73818804643 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 73818804643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.kmac_stress_all_with_rand_reset.2493797229
Line 423, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 26931275228 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 26931275228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test kmac_stress_all has 1 failures.
20.kmac_stress_all.1571907431
Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest/run.log
UVM_FATAL @ 19058029046 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 19058029046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 2 failures.
41.kmac_error.2057617847
Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_error/latest/run.log
UVM_FATAL @ 10400752581 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10400752581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.kmac_error.1030802213
Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_error/latest/run.log
UVM_FATAL @ 10027715644 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10027715644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test kmac_sideload has 1 failures.
8.kmac_sideload.3156693701
Line 338, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_sideload/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 2 failures.
9.kmac_burst_write.322910395
Line 331, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.kmac_burst_write.4013285755
Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_app_with_partial_data has 1 failures.
4.kmac_app_with_partial_data.3813232657
Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 7047225197 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (49 [0x31] vs 36 [0x24]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 7047225197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
23.kmac_entropy_refresh.191657292
Line 252, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 1034118990 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (83 [0x53] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1034118990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
Test kmac_stress_all has 1 failures.
23.kmac_stress_all.3033477869
Line 540, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
UVM_ERROR @ 62186391695 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 62186391695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_smoke has 1 failures.
34.kmac_smoke.746458733
Line 243, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_smoke/latest/run.log
UVM_ERROR @ 64082942 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 64082942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
15.kmac_key_error.1809447174
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_key_error/latest/run.log
UVM_ERROR @ 2039418624 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 2039418624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
19.kmac_long_msg_and_output.3618616364
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest/run.log
Job ID: smart:3aef12c2-8ae0-4765-8fdf-2f1870f1eecb