KMAC/MASKED Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.456m	8.158ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	29.690us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	61.921us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.930s	5.627ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.070s	1.742ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.370s	225.846us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	61.921us	20	20	100.00
		kmac_csr_aliasing	11.070s	1.742ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.860s	51.896us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	38.671us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.691m	125.486ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.517m	17.333ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.209m	95.546ms	50	50	100.00
		kmac_test_vectors_sha3_256	46.104m	1.581s	50	50	100.00
		kmac_test_vectors_sha3_384	34.431m	783.142ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.804m	353.895ms	49	50	98.00
		kmac_test_vectors_shake_128	1.986h	888.326ms	50	50	100.00
		kmac_test_vectors_shake_256	1.656h	220.168ms	50	50	100.00
		kmac_test_vectors_kmac	8.100s	694.477us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.300s	537.430us	50	50	100.00
V2	sideload	kmac_sideload	8.753m	85.813ms	50	50	100.00
V2	app	kmac_app	6.433m	21.555ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.802m	63.312ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.792m	8.605ms	48	50	96.00
V2	error	kmac_error	8.426m	61.924ms	50	50	100.00
V2	key_error	kmac_key_error	7.230s	4.785ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.770s	8.545ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.300s	774.656us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.121m	17.233ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	28.250s	3.208ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.013h	941.412ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.880s	16.614us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	58.262us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.230s	218.575us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.230s	218.575us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	29.690us	5	5	100.00
		kmac_csr_rw	1.260s	61.921us	20	20	100.00
		kmac_csr_aliasing	11.070s	1.742ms	5	5	100.00
		kmac_same_csr_outstanding	3.000s	139.613us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	29.690us	5	5	100.00
		kmac_csr_rw	1.260s	61.921us	20	20	100.00
		kmac_csr_aliasing	11.070s	1.742ms	5	5	100.00
		kmac_same_csr_outstanding	3.000s	139.613us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	995.432us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	995.432us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	995.432us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	995.432us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.590s	544.326us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.353m	5.098ms	5	5	100.00
		kmac_tl_intg_err	5.980s	2.522ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.980s	2.522ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	28.250s	3.208ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.456m	8.158ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.753m	85.813ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	995.432us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.353m	5.098ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.353m	5.098ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.353m	5.098ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.456m	8.158ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	28.250s	3.208ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.353m	5.098ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.016m	11.563ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.456m	8.158ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.346h	499.691ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1262	1290	97.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	98.40	93.36	99.93	95.45	96.03	98.87	98.17

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 13 failures:

Test kmac_stress_all_with_rand_reset has 13 failures.

4.kmac_stress_all_with_rand_reset.2370809364
Line 433, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34192254369 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 34192254369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_stress_all_with_rand_reset.975788565
Line 727, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23710432948 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 23710432948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

19.kmac_stress_all_with_rand_reset.2754940568
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16648678172 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (48 [0x30] vs 250 [0xfa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16648678172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

34.kmac_stress_all.2325366879
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all/latest/run.log

  UVM_FATAL @ 44352505230 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (190 [0xbe] vs 96 [0x60]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 44352505230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

44.kmac_app.2841206658
Line 284, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_app/latest/run.log

  UVM_FATAL @ 24200810995 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (147 [0x93] vs 6 [0x6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 24200810995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_app.1720752492
Line 280, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_app/latest/run.log

  UVM_FATAL @ 1194606747 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (45 [0x2d] vs 27 [0x1b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1194606747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 1 failures.

46.kmac_entropy_refresh.3854532042
Line 292, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 20616421258 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 235 [0xeb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20616421258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:

Test kmac_stress_all has 2 failures.

2.kmac_stress_all.2746587205
Line 507, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_FATAL @ 47932932575 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 47932932575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_stress_all.2030738288
Line 596, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log

  UVM_FATAL @ 349614378725 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 349614378725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 2 failures.

15.kmac_stress_all_with_rand_reset.2069777369
Line 310, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 20165191692 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 20165191692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_stress_all_with_rand_reset.3127574463
Line 1217, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 157120138152 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 157120138152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_burst_write has 2 failures.

21.kmac_burst_write.1361875907
Line 370, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_burst_write.4222177016
Line 412, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.3322341696
    Line 551, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17989263639 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (255 [0xff] vs 226 [0xe2]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 17989263639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'rand_valid_o' has 1 failures:

Test kmac_entropy_refresh has 1 failures.

12.kmac_entropy_refresh.2202337669
Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest/run.log

      Offending 'rand_valid_o'
  UVM_ERROR @ 4894451603 ps: (kmac_entropy.sv:503) [ASSERT FAILED] ConsumeNotAseertWhenNotReady_M
  UVM_INFO @ 4894451603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 34.kmac_test_vectors_sha3_512.1752352374
    Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 188140481 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 188140481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```