KMAC/MASKED Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.512m 29.849ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.180s 100.836us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.250s 43.629us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 21.390s 5.130ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 12.980s 8.259ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.410s 28.880us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.250s 43.629us 20 20 100.00
kmac_csr_aliasing 12.980s 8.259ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.780s 35.327us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.610s 158.302us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 54.654m 88.345ms 50 50 100.00
V2 burst_write kmac_burst_write 24.713m 58.334ms 48 50 96.00
V2 test_vectors kmac_test_vectors_sha3_224 51.047m 1.406s 50 50 100.00
kmac_test_vectors_sha3_256 43.544m 1.606s 49 50 98.00
kmac_test_vectors_sha3_384 32.843m 582.095ms 50 50 100.00
kmac_test_vectors_sha3_512 23.676m 60.889ms 50 50 100.00
kmac_test_vectors_shake_128 1.880h 274.082ms 50 50 100.00
kmac_test_vectors_shake_256 1.634h 1.358s 49 50 98.00
kmac_test_vectors_kmac 7.430s 505.165us 50 50 100.00
kmac_test_vectors_kmac_xof 7.400s 2.480ms 50 50 100.00
V2 sideload kmac_sideload 8.621m 61.360ms 50 50 100.00
V2 app kmac_app 6.955m 21.046ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 6.736m 36.991ms 9 10 90.00
V2 entropy_refresh kmac_entropy_refresh 7.235m 35.801ms 49 50 98.00
V2 error kmac_error 8.778m 76.771ms 50 50 100.00
V2 key_error kmac_key_error 8.230s 2.870ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 54.040s 8.725ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 49.160s 561.570us 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.422m 15.409ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 36.480s 669.937us 50 50 100.00
V2 stress_all kmac_stress_all 50.435m 34.696ms 48 50 96.00
V2 intr_test kmac_intr_test 0.870s 26.647us 50 50 100.00
V2 alert_test kmac_alert_test 0.980s 41.579us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.430s 279.647us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.430s 279.647us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.180s 100.836us 5 5 100.00
kmac_csr_rw 1.250s 43.629us 20 20 100.00
kmac_csr_aliasing 12.980s 8.259ms 5 5 100.00
kmac_same_csr_outstanding 2.820s 245.384us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.180s 100.836us 5 5 100.00
kmac_csr_rw 1.250s 43.629us 20 20 100.00
kmac_csr_aliasing 12.980s 8.259ms 5 5 100.00
kmac_same_csr_outstanding 2.820s 245.384us 20 20 100.00
V2 TOTAL 1042 1050 99.24
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.010s 78.401us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.010s 78.401us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.010s 78.401us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.010s 78.401us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 5.520s 793.650us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.950m 9.480ms 5 5 100.00
kmac_tl_intg_err 5.730s 520.100us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.730s 520.100us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 36.480s 669.937us 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.512m 29.849ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 8.621m 61.360ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.010s 78.401us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.950m 9.480ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.950m 9.480ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.950m 9.480ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.512m 29.849ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 36.480s 669.937us 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.950m 9.480ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.411m 11.893ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.512m 29.849ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.034h 83.501ms 35 50 70.00
V3 TOTAL 35 50 70.00
TOTAL 1267 1290 98.22

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 19 76.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.06 98.40 93.36 99.93 94.55 96.03 98.87 98.31

Failure Buckets

Past Results