213e792ea
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.512m | 29.849ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.180s | 100.836us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.250s | 43.629us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 21.390s | 5.130ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 12.980s | 8.259ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.410s | 28.880us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 43.629us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 12.980s | 8.259ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.780s | 35.327us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.610s | 158.302us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 54.654m | 88.345ms | 50 | 50 | 100.00 |
V2 | burst_write | kmac_burst_write | 24.713m | 58.334ms | 48 | 50 | 96.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 51.047m | 1.406s | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 43.544m | 1.606s | 49 | 50 | 98.00 | ||
kmac_test_vectors_sha3_384 | 32.843m | 582.095ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 23.676m | 60.889ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.880h | 274.082ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_256 | 1.634h | 1.358s | 49 | 50 | 98.00 | ||
kmac_test_vectors_kmac | 7.430s | 505.165us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 7.400s | 2.480ms | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 8.621m | 61.360ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 6.955m | 21.046ms | 50 | 50 | 100.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 6.736m | 36.991ms | 9 | 10 | 90.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 7.235m | 35.801ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 8.778m | 76.771ms | 50 | 50 | 100.00 |
V2 | key_error | kmac_key_error | 8.230s | 2.870ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 54.040s | 8.725ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 49.160s | 561.570us | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.422m | 15.409ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 36.480s | 669.937us | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 50.435m | 34.696ms | 48 | 50 | 96.00 |
V2 | intr_test | kmac_intr_test | 0.870s | 26.647us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.980s | 41.579us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.430s | 279.647us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.430s | 279.647us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.180s | 100.836us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 43.629us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 12.980s | 8.259ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.820s | 245.384us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.180s | 100.836us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 43.629us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 12.980s | 8.259ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.820s | 245.384us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1042 | 1050 | 99.24 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.010s | 78.401us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.010s | 78.401us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.010s | 78.401us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.010s | 78.401us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.520s | 793.650us | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.950m | 9.480ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.730s | 520.100us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.730s | 520.100us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 36.480s | 669.937us | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.512m | 29.849ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 8.621m | 61.360ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.010s | 78.401us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.950m | 9.480ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.950m | 9.480ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.950m | 9.480ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.512m | 29.849ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 36.480s | 669.937us | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.950m | 9.480ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.411m | 11.893ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.512m | 29.849ms | 50 | 50 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.034h | 83.501ms | 35 | 50 | 70.00 |
V3 | TOTAL | 35 | 50 | 70.00 | |||
TOTAL | 1267 | 1290 | 98.22 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 19 | 76.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.06 | 98.40 | 93.36 | 99.93 | 94.55 | 96.03 | 98.87 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 13 failures:
0.kmac_stress_all_with_rand_reset.1394603769
Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31887622369 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 31887622369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_stress_all_with_rand_reset.2960351082
Line 272, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96223500 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
UVM_INFO @ 96223500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 4 failures:
Test kmac_stress_all_with_rand_reset has 2 failures.
6.kmac_stress_all_with_rand_reset.1190071140
Line 1598, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 303796290838 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 303796290838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.kmac_stress_all_with_rand_reset.1407419246
Line 338, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25511386808 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 25511386808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 2 failures.
8.kmac_stress_all.2524208477
Line 485, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log
UVM_FATAL @ 27981643336 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 27981643336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_stress_all.2991715284
Line 514, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log
UVM_FATAL @ 224307399120 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 224307399120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 3 failures:
Test kmac_app_with_partial_data has 1 failures.
1.kmac_app_with_partial_data.1564899152
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 2 failures.
13.kmac_burst_write.2529236058
Line 359, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.kmac_burst_write.2541142548
Line 364, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 2 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
13.kmac_test_vectors_sha3_256.396199060
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 70400418 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 70400418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
17.kmac_test_vectors_shake_256.3661297360
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 55832170 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 55832170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 1 failures:
22.kmac_entropy_refresh.3305187104
Line 267, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 1030409891 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (5 [0x5] vs 53 [0x35]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1030409891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---