KMAC/MASKED Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.439m	23.552ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	41.891us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.310s	128.387us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.470s	14.891ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.470s	1.751ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.540s	118.555us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.310s	128.387us	20	20	100.00
		kmac_csr_aliasing	11.470s	1.751ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	41.346us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	132.513us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.593m	127.704ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.720m	62.189ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.467m	131.007ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.457m	96.260ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.120m	291.568ms	49	50	98.00
		kmac_test_vectors_sha3_512	27.819m	962.266ms	50	50	100.00
		kmac_test_vectors_shake_128	1.852h	1.613s	50	50	100.00
		kmac_test_vectors_shake_256	1.554h	231.051ms	50	50	100.00
		kmac_test_vectors_kmac	8.090s	722.297us	50	50	100.00
		kmac_test_vectors_kmac_xof	8.390s	3.514ms	50	50	100.00
V2	sideload	kmac_sideload	9.013m	15.704ms	50	50	100.00
V2	app	kmac_app	6.841m	53.507ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.170m	200.000ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.016m	15.059ms	48	50	96.00
V2	error	kmac_error	8.426m	28.310ms	48	50	96.00
V2	key_error	kmac_key_error	9.010s	12.318ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.400s	6.845ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.240s	684.539us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.820s	13.569ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.290s	722.237us	50	50	100.00
V2	stress_all	kmac_stress_all	1.107h	735.058ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	23.956us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	127.324us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.240s	105.655us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.240s	105.655us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	41.891us	5	5	100.00
		kmac_csr_rw	1.310s	128.387us	20	20	100.00
		kmac_csr_aliasing	11.470s	1.751ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	260.264us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	41.891us	5	5	100.00
		kmac_csr_rw	1.310s	128.387us	20	20	100.00
		kmac_csr_aliasing	11.470s	1.751ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	260.264us	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.170s	182.251us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.170s	182.251us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.170s	182.251us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.170s	182.251us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.310s	1.067ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.953m	34.421ms	5	5	100.00
		kmac_tl_intg_err	6.130s	1.361ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.130s	1.361ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.290s	722.237us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.439m	23.552ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.013m	15.704ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.170s	182.251us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.953m	34.421ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.953m	34.421ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.953m	34.421ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.439m	23.552ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.290s	722.237us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.953m	34.421ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.316m	63.139ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.439m	23.552ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.012h	366.110ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1267	1290	98.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.06	98.40	93.36	99.93	94.55	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:

Test kmac_stress_all_with_rand_reset has 9 failures.

4.kmac_stress_all_with_rand_reset.1226488148
Line 1576, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 78808781411 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 78808781411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_stress_all_with_rand_reset.1430158889
Line 339, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17789300379 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17789300379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test kmac_burst_write has 3 failures.

3.kmac_burst_write.76612853
Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.kmac_burst_write.3181299592
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.2841275612
Line 394, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

41.kmac_entropy_refresh.1062329937
Line 368, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:

Test kmac_error has 2 failures.

13.kmac_error.2106183615
Line 289, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_error/latest/run.log

  UVM_FATAL @ 10101170652 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10101170652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.kmac_error.1738812918
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_error/latest/run.log

  UVM_FATAL @ 10025361687 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10025361687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 2 failures.

16.kmac_stress_all_with_rand_reset.1825893262
Line 670, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 61359072812 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 61359072812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_stress_all_with_rand_reset.2588984006
Line 359, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14376079039 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 14376079039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

0.kmac_stress_all.1750902977
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5977745946 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (173 [0xad] vs 13 [0xd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5977745946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.kmac_stress_all.3729289121
Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4370280498 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (193 [0xc1] vs 219 [0xdb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4370280498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

7.kmac_entropy_refresh.1542113724
Line 364, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 18060564387 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (146 [0x92] vs 113 [0x71]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18060564387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 11.kmac_test_vectors_sha3_224.202674291
    Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  49317105 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  49317105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 24.kmac_test_vectors_sha3_384.3013057827
    Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  36377505 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  36377505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```