Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	96167830	1			T17	5		T67	5		T1	1
all_values[1]	96167830	1			T17	5		T67	5		T1	1
all_values[2]	96167830	1			T17	5		T67	5		T1	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308640

1

T17

12

T67

12

T1

3

auto[1]

288194850

1

T17

3

T67

3

T11

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287018040

1

T17

9

T67

9

T1

3

auto[1]

1485450

1

T17

6

T67

6

T11

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	125390	1			T17	3		T67	3		T1	1
all_values[0]	auto[0]	auto[1]	2320	1			T20	4		T30	28		T32	2
all_values[0]	auto[1]	auto[0]	95547290	1			T20	107523		T21	459333		T22	6326
all_values[0]	auto[1]	auto[1]	492830	1			T17	2		T67	2		T11	2
all_values[1]	auto[0]	auto[0]	158690	1			T17	3		T67	3		T1	1
all_values[1]	auto[0]	auto[1]	1290	1			T17	1		T67	1		T11	1
all_values[1]	auto[1]	auto[0]	95513990	1			T20	107526		T21	459331		T22	6256
all_values[1]	auto[1]	auto[1]	493860	1			T17	1		T67	1		T11	1
all_values[2]	auto[0]	auto[0]	19620	1			T17	3		T67	3		T1	1
all_values[2]	auto[0]	auto[1]	1330	1			T17	2		T67	2		T11	2
all_values[2]	auto[1]	auto[0]	95653060	1			T20	107525		T21	459328		T22	6256
all_values[2]	auto[1]	auto[1]	493820	1			T20	357		T21	3385		T22	55