Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.41	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	5	16	76.19
Crosses	8	3	5	62.50

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	4	5	55.56	100	1	1	0
mode	3	1	2	66.67	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	3	4	57.14	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	250	1			T31	5		T51	5		T52	5
auto[CmdProcess]	50	1			T31	1		T51	1		T52	1
auto[CmdManualRun]	200	1			T31	4		T51	4		T52	4
auto[CmdDone]	900	1			T31	18		T51	18		T52	18

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Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	4	5	55.56

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrSwPushedMsgFifo]	0	1	1
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T46	1		T54	1		T55	1
auto[ErrSwIssuedCmdInAppActive]	50	1			T31	1		T51	1		T52	1
auto[ErrUnexpectedModeStrength]	450	1			T31	9		T51	9		T52	9
auto[ErrIncorrectFunctionName]	250	1			T31	5		T51	5		T52	5
auto[ErrSwCmdSequence]	650	1			T31	13		T51	13		T52	13

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Sha3]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Shake]

200

1

T31

4

T51

4

T52

4

auto[CShake]

1200

1

T31

24

T51

24

T52

24

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	100	1			T31	2		T51	2		T52	2
auto[L224]	400	1			T31	8		T51	8		T52	8
auto[L256]	500	1			T31	9		T46	1		T51	9
auto[L384]	250	1			T31	5		T51	5		T52	5
auto[L512]	200	1			T31	4		T51	4		T52	4

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

50

1

T31

1

T51

1

T52

1

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	3	4	57.14

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha3_128_cfgs	0	1	1
shake_224_invalid_cfg	0	1	1
shake_384_invalid_cfg	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
shake_512_invalid_cfg	50	1			T31	1		T51	1		T52	1
cshake_224_invalid_cfg	200	1			T31	4		T51	4		T52	4
cshake_384_invalid_cfg	150	1			T31	3		T51	3		T52	3
cshake_512_invalid_cfg	50	1			T31	1		T51	1		T52	1