Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10350 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 8250 1 T21 38 T30 10 T32 12
len_5001_7500 11200 1 T20 33 T21 36 T30 14
len_2501_5000 8900 1 T20 34 T21 36 T30 3
len_1025_2500 5450 1 T20 20 T21 22 T30 6
len_769_1024 4210 1 T20 4 T21 4 T22 9
len_513_768 5720 1 T20 3 T21 4 T22 11
len_257_512 19500 1 T20 4 T21 52 T22 9
len_0_256 257590 1 T20 148 T21 2017 T22 10
len_keccak_block_sizes[72] 710 1 T20 2 T21 3 T22 1
len_keccak_block_sizes[104] 650 1 T21 3 T23 2 T33 1
len_keccak_block_sizes[136] 510 1 T21 3 T23 2 T34 3
len_keccak_block_sizes[144] 400 1 T21 3 T23 2 T34 3
len_keccak_block_sizes[168] 350 1 T21 3 T34 3 T35 3
len_1 700 1 T20 2 T21 3 T23 2
len_0 900 1 T20 2 T21 3 T30 1

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