Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	96167830	1			T17	5		T67	5		T1	1
all_pins[1]	96167830	1			T17	5		T67	5		T1	1
all_pins[2]	96167830	1			T17	5		T67	5		T1	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	244402780	1			T17	13		T67	13		T1	3
values[0x1]	44100710	1			T17	2		T67	2		T11	2
transitions[0x0=>0x1]	43660870	1			T17	2		T67	2		T11	2
transitions[0x1=>0x0]	43660870	1			T17	2		T67	2		T11	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95675000	1			T17	3		T67	3		T1	1
all_pins[0]	values[0x1]	492830	1			T17	2		T67	2		T11	2
all_pins[0]	transitions[0x0=>0x1]	217040	1			T17	2		T67	2		T11	2
all_pins[0]	transitions[0x1=>0x0]	42902580	1			T20	48492		T21	206496		T22	2450
all_pins[1]	values[0x0]	52989460	1			T17	5		T67	5		T1	1
all_pins[1]	values[0x1]	43178370	1			T20	48802		T21	207823		T22	2499
all_pins[1]	transitions[0x0=>0x1]	43016740	1			T20	48802		T21	207823		T22	2499
all_pins[1]	transitions[0x1=>0x0]	267880	1			T30	3763		T31	638		T51	638
all_pins[2]	values[0x0]	95738320	1			T17	5		T67	5		T1	1
all_pins[2]	values[0x1]	429510	1			T30	6315		T31	639		T51	639
all_pins[2]	transitions[0x0=>0x1]	427090	1			T30	6276		T31	639		T51	639
all_pins[2]	transitions[0x1=>0x0]	490410	1			T17	2		T67	2		T11	2