Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8919780 |
1 |
|
|
T20 |
3936 |
|
T21 |
47900 |
|
T22 |
6997 |
auto[1] |
8919780 |
1 |
|
|
T20 |
3936 |
|
T21 |
47900 |
|
T22 |
6997 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
17617060 |
1 |
|
|
T20 |
7872 |
|
T21 |
93928 |
|
T22 |
13934 |
triple_byte_access |
74360 |
1 |
|
|
T21 |
620 |
|
T22 |
22 |
|
T30 |
120 |
halfword_access |
76320 |
1 |
|
|
T21 |
632 |
|
T22 |
20 |
|
T30 |
136 |
byte_access |
71820 |
1 |
|
|
T21 |
620 |
|
T22 |
18 |
|
T30 |
102 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
8808530 |
1 |
|
|
T20 |
3936 |
|
T21 |
46964 |
|
T22 |
6967 |
auto[0] |
triple_byte_access |
37180 |
1 |
|
|
T21 |
310 |
|
T22 |
11 |
|
T30 |
60 |
auto[0] |
halfword_access |
38160 |
1 |
|
|
T21 |
316 |
|
T22 |
10 |
|
T30 |
68 |
auto[0] |
byte_access |
35910 |
1 |
|
|
T21 |
310 |
|
T22 |
9 |
|
T30 |
51 |
auto[1] |
word_access |
8808530 |
1 |
|
|
T20 |
3936 |
|
T21 |
46964 |
|
T22 |
6967 |
auto[1] |
triple_byte_access |
37180 |
1 |
|
|
T21 |
310 |
|
T22 |
11 |
|
T30 |
60 |
auto[1] |
halfword_access |
38160 |
1 |
|
|
T21 |
316 |
|
T22 |
10 |
|
T30 |
68 |
auto[1] |
byte_access |
35910 |
1 |
|
|
T21 |
310 |
|
T22 |
9 |
|
T30 |
51 |