Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	9	9	50.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	9	9	50.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	200	1			T17	4		T67	4		T11	4
all_values[1]	200	1			T17	4		T67	4		T11	4
all_values[2]	200	1			T17	4		T67	4		T11	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T17

8

T67

8

T11

8

auto[1]

200

1

T17

4

T67

4

T11

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250

1

T17

5

T67

5

T11

5

auto[1]

350

1

T17

7

T67

7

T11

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300

1

T17

6

T67

6

T11

6

auto[1]

300

1

T17

6

T67

6

T11

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	9	9	50.00	9
Automatically Generated Cross Bins	18	9	9	50.00	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[all_values[2]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[1]]	[auto[0]]	[auto[0]]	[auto[0]]	0	1	1
[all_values[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[2]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[2]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

50

1

T17

1

T67

1

T11

1

all_values[0]

auto[1]

auto[0]

auto[1]

50

1

T17

1

T67

1

T11

1

all_values[0]

auto[1]

auto[1]

auto[1]

100

1

T17

2

T67

2

T11

2

all_values[1]

auto[0]

auto[0]

auto[1]

50

1

T17

1

T67

1

T11

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T17

1

T67

1

T11

1

all_values[1]

auto[1]

auto[0]

auto[1]

50

1

T17

1

T67

1

T11

1

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T17

1

T67

1

T11

1

all_values[2]

auto[0]

auto[0]

auto[0]

150

1

T17

3

T67

3

T11

3

all_values[2]

auto[1]

auto[0]

auto[1]

50

1

T17

1

T67

1

T11

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal