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 LINE       70
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Not Covered
1	1	Covered	T17,T18,T19

 LINE       82
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T27,T28,T29
1	0	Covered	T3,T5,T7

 LINE       89
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T17,T18,T19
0	0	1	Covered	T27,T28,T29
0	1	0	Covered	T3,T5,T7
1	0	0	Covered	T3,T5,T7

 LINE       139
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[1024:1535]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2))
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       139
 SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2)
                 ------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       178
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T17,T18,T19
0	0	1	Covered	T3,T5,T7
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       178
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T17,T18,T19
1	1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (cfg_shadowed_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T5,T7
1	1	Covered	T18,T19,T66

 LINE       1303
 EXPRESSION (entropy_period_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1390
 EXPRESSION (entropy_refresh_threshold_shadowed_we & cfg_regwen_qs)
             ------------------1------------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T71,T3,T13
1	1	Covered	T18,T19,T66

 LINE       1540
 EXPRESSION (key_share0_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1564
 EXPRESSION (key_share0_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1588
 EXPRESSION (key_share0_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1612
 EXPRESSION (key_share0_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1636
 EXPRESSION (key_share0_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1660
 EXPRESSION (key_share0_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1684
 EXPRESSION (key_share0_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1708
 EXPRESSION (key_share0_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1732
 EXPRESSION (key_share0_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1756
 EXPRESSION (key_share0_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1780
 EXPRESSION (key_share0_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1804
 EXPRESSION (key_share0_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1828
 EXPRESSION (key_share0_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1852
 EXPRESSION (key_share0_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1876
 EXPRESSION (key_share0_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1900
 EXPRESSION (key_share0_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T19,T66,T69

 LINE       1924
 EXPRESSION (key_share1_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1948
 EXPRESSION (key_share1_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1972
 EXPRESSION (key_share1_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       1996
 EXPRESSION (key_share1_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2020
 EXPRESSION (key_share1_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2044
 EXPRESSION (key_share1_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2068
 EXPRESSION (key_share1_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2092
 EXPRESSION (key_share1_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2116
 EXPRESSION (key_share1_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2140
 EXPRESSION (key_share1_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2164
 EXPRESSION (key_share1_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2188
 EXPRESSION (key_share1_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2212
 EXPRESSION (key_share1_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2236
 EXPRESSION (key_share1_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2260
 EXPRESSION (key_share1_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2284
 EXPRESSION (key_share1_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2304
 EXPRESSION (key_len_we & cfg_regwen_qs)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2336
 EXPRESSION (prefix_0_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2368
 EXPRESSION (prefix_1_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2400
 EXPRESSION (prefix_2_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2432
 EXPRESSION (prefix_3_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2464
 EXPRESSION (prefix_4_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2496
 EXPRESSION (prefix_5_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2528
 EXPRESSION (prefix_6_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2560
 EXPRESSION (prefix_7_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2592
 EXPRESSION (prefix_8_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2624
 EXPRESSION (prefix_9_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T14,T105,T106
1	1	Covered	T18,T19,T66

 LINE       2656
 EXPRESSION (prefix_10_we & cfg_regwen_qs)
             ------1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T14,T5
1	1	Covered	T18,T19,T66

 LINE       2716
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2717
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2718
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2719
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2720
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_REGWEN_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2721
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_SHADOWED_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2722
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2723
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2724
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_PERIOD_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2725
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2726
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2727
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2728
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2729
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2730
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2731
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2732
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2733
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2734
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2735
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2736
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2737
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2738
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2739
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2740
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2741
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2742
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2743
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2744
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2745
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2746
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2747
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2748
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2749
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2750
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2751
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2752
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2753
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2754
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2755
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2756
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2757
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2758
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2759
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2760
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2761
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2762
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2763
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2764
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_LEN_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2765
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2766
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2767
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2768
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2769
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2770
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2771
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2772
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2773
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_8_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2774
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_9_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2775
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_10_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2776
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T19,T66

 LINE       2779
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       2779
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19