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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.63 98.10 88.18 99.93 80.00 95.24 96.52 90.42


Total test records in report: 1240
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T1013 /workspace/coverage/default/24.kmac_test_vectors_kmac.64696666908427446714017170906164593974591671791741526538132269677797908342526 Nov 22 02:03:17 PM PST 23 Nov 22 02:03:24 PM PST 23 322955517 ps
T1014 /workspace/coverage/default/26.kmac_test_vectors_kmac.104729926896262508225490334216585711942860202285944420592856039382387807757002 Nov 22 02:03:59 PM PST 23 Nov 22 02:04:05 PM PST 23 322955517 ps
T1015 /workspace/coverage/default/0.kmac_test_vectors_sha3_224.65054844949978902745330875871639659586852645681425863886557668051756767067406 Nov 22 02:00:24 PM PST 23 Nov 22 02:37:41 PM PST 23 117329894454 ps
T1016 /workspace/coverage/default/14.kmac_entropy_mode_error.55804624693663986088626767682915816115752951817949749042801915976579918146323 Nov 22 02:01:37 PM PST 23 Nov 22 02:01:39 PM PST 23 64850439 ps
T1017 /workspace/coverage/default/15.kmac_error.33930922948119559295267287464014168687602213164674872581987735679827398338359 Nov 22 02:02:26 PM PST 23 Nov 22 02:04:57 PM PST 23 8137821569 ps
T1018 /workspace/coverage/default/6.kmac_test_vectors_sha3_512.114345249155044903483810848874440083207120556114708726110129132319783766888766 Nov 22 02:00:44 PM PST 23 Nov 22 02:21:41 PM PST 23 57499426673 ps
T1019 /workspace/coverage/default/19.kmac_key_error.93919157755293945679920689780330331301346333518661094340903487301464610511511 Nov 22 02:02:25 PM PST 23 Nov 22 02:02:38 PM PST 23 1579963318 ps
T1020 /workspace/coverage/default/6.kmac_test_vectors_shake_256.44614287468227355205726856527520984617387446701936065707749343318972599987462 Nov 22 02:01:01 PM PST 23 Nov 22 03:19:33 PM PST 23 270085708112 ps
T1021 /workspace/coverage/default/11.kmac_test_vectors_shake_128.18517468967129525434595084286511774959369671818558260241436983599264964852155 Nov 22 02:01:35 PM PST 23 Nov 22 03:31:55 PM PST 23 320694338954 ps
T1022 /workspace/coverage/default/32.kmac_alert_test.113406217171834815833158161922630142094221675884233062315581156218529308881327 Nov 22 02:03:58 PM PST 23 Nov 22 02:03:59 PM PST 23 21118646 ps
T1023 /workspace/coverage/default/13.kmac_test_vectors_sha3_512.71816735103802963454346693038248552227730428034461338858523182042960707972876 Nov 22 02:01:36 PM PST 23 Nov 22 02:21:03 PM PST 23 57499426673 ps
T1024 /workspace/coverage/default/15.kmac_test_vectors_sha3_224.66352432871697250829607293451391043128457257118349359285581584581357599783374 Nov 22 02:02:05 PM PST 23 Nov 22 02:37:23 PM PST 23 117329894454 ps
T1025 /workspace/coverage/default/17.kmac_test_vectors_shake_128.62904065350550924519365178134227587034659996896578826159687141160892436649004 Nov 22 02:02:24 PM PST 23 Nov 22 03:32:18 PM PST 23 320694338954 ps
T1026 /workspace/coverage/default/42.kmac_smoke.70603591031159146482880002064580124618934032560577665373548825513647762608541 Nov 22 02:04:59 PM PST 23 Nov 22 02:05:27 PM PST 23 1925406983 ps
T1027 /workspace/coverage/default/31.kmac_app.65321744702552315638262343921609945623506048437710699066190622467131226022156 Nov 22 02:04:00 PM PST 23 Nov 22 02:05:39 PM PST 23 6076748772 ps
T1028 /workspace/coverage/default/6.kmac_mubi.59302826861439788760549856541461622403277450381489685321722337832582655916051 Nov 22 02:01:04 PM PST 23 Nov 22 02:03:19 PM PST 23 7712378544 ps
T1029 /workspace/coverage/default/28.kmac_test_vectors_shake_128.103591056376325754447279370914759399184263787945684611043041000579845207207430 Nov 22 02:03:19 PM PST 23 Nov 22 03:32:18 PM PST 23 320694338954 ps
T1030 /workspace/coverage/default/25.kmac_test_vectors_kmac.26517646748542462282705155461433580320583415143262403244733255131800713876860 Nov 22 02:03:15 PM PST 23 Nov 22 02:03:22 PM PST 23 322955517 ps
T1031 /workspace/coverage/default/49.kmac_burst_write.59913976186274742502549599584478431929370263928967827770457725963275222100899 Nov 22 02:05:56 PM PST 23 Nov 22 02:12:43 PM PST 23 14830000174 ps
T1032 /workspace/coverage/default/44.kmac_sideload.27828665373972677967488799166267966820323873754850286456739012544418496087668 Nov 22 02:05:02 PM PST 23 Nov 22 02:07:21 PM PST 23 7628111361 ps
T1033 /workspace/coverage/default/0.kmac_app_with_partial_data.57303001816859950092444872393111707378857339784708989966829103818797654063953 Nov 22 02:00:16 PM PST 23 Nov 22 02:02:10 PM PST 23 7277596308 ps
T1034 /workspace/coverage/default/23.kmac_sideload.10441872226981301004472429958067768885163369653243976525664645293219189903549 Nov 22 02:02:35 PM PST 23 Nov 22 02:05:00 PM PST 23 7628111361 ps
T1035 /workspace/coverage/default/40.kmac_error.33577015979346329661520559460310751148110712530763239809503778418481105739556 Nov 22 02:05:08 PM PST 23 Nov 22 02:07:34 PM PST 23 8137821569 ps
T1036 /workspace/coverage/default/17.kmac_long_msg_and_output.64569304193840722045014805764237714634936012910864778161807737600531067914830 Nov 22 02:02:04 PM PST 23 Nov 22 02:18:09 PM PST 23 50513696845 ps
T1037 /workspace/coverage/default/34.kmac_app.101237192334215413800611447653047121759841016236226107816274164912134189647353 Nov 22 02:04:25 PM PST 23 Nov 22 02:06:04 PM PST 23 6076748772 ps
T1038 /workspace/coverage/default/14.kmac_test_vectors_sha3_512.60904760365184667208820689919126014594302093847663567295147718698041351237255 Nov 22 02:02:25 PM PST 23 Nov 22 02:20:52 PM PST 23 57499426673 ps
T1039 /workspace/coverage/default/4.kmac_sideload.6657127320597036887413059537451316518248370763568022548911648788646398450652 Nov 22 02:00:46 PM PST 23 Nov 22 02:03:01 PM PST 23 7628111361 ps
T1040 /workspace/coverage/default/3.kmac_entropy_ready_error.8438792253029797862376262682763507150102285192030233245136275658182855963200 Nov 22 02:00:36 PM PST 23 Nov 22 02:00:59 PM PST 23 3179093382 ps
T1041 /workspace/coverage/default/13.kmac_test_vectors_sha3_224.83133282147035623017750913432728937231842559445577594885076374960990938772542 Nov 22 02:01:20 PM PST 23 Nov 22 02:37:26 PM PST 23 117329894454 ps
T1042 /workspace/coverage/default/33.kmac_lc_escalation.104495542883498161001778827245038637703772686776863393500358961689962087002834 Nov 22 02:04:20 PM PST 23 Nov 22 02:04:22 PM PST 23 72761090 ps
T1043 /workspace/coverage/default/35.kmac_smoke.8021363634677247630270652483746750958604522330970993793725382018093082755352 Nov 22 02:04:18 PM PST 23 Nov 22 02:04:45 PM PST 23 1925406983 ps
T1044 /workspace/coverage/default/21.kmac_test_vectors_sha3_256.49351899833630829235290131965295691135586887234582626864475645974714329979805 Nov 22 02:02:27 PM PST 23 Nov 22 02:34:00 PM PST 23 106843317633 ps
T1045 /workspace/coverage/default/37.kmac_test_vectors_sha3_256.57699602048031187411526222734784680613057398181992254174171059629943273081343 Nov 22 02:04:52 PM PST 23 Nov 22 02:38:08 PM PST 23 106843317633 ps
T1046 /workspace/coverage/default/39.kmac_test_vectors_shake_256.86808360132515960619044817606977928434982413879769133909439111054893682989186 Nov 22 02:05:01 PM PST 23 Nov 22 03:22:58 PM PST 23 270085708112 ps
T1047 /workspace/coverage/default/30.kmac_app.12413223715151893586219838244361432923183769080182711311649841650917006400104 Nov 22 02:03:33 PM PST 23 Nov 22 02:05:12 PM PST 23 6076748772 ps
T1048 /workspace/coverage/default/18.kmac_sideload.63543773539196658011801339716930203143062094155951910806354943464469310597279 Nov 22 02:02:35 PM PST 23 Nov 22 02:05:06 PM PST 23 7628111361 ps
T1049 /workspace/coverage/default/2.kmac_burst_write.87694249529616787798894122534064359406468408754274698534393738217300305557463 Nov 22 02:00:30 PM PST 23 Nov 22 02:07:14 PM PST 23 14830000174 ps
T1050 /workspace/coverage/default/8.kmac_lc_escalation.25138385192817306575957159053396989398161850504793634317048771184544166100901 Nov 22 02:01:18 PM PST 23 Nov 22 02:01:21 PM PST 23 72761090 ps
T1051 /workspace/coverage/default/34.kmac_test_vectors_sha3_512.91357629433933213952703470490239722864934808332101949008933424566210956450853 Nov 22 02:04:15 PM PST 23 Nov 22 02:24:02 PM PST 23 57499426673 ps
T1052 /workspace/coverage/default/9.kmac_app_with_partial_data.66358537652388119279815788610777615461220692810881195173250615756676227376583 Nov 22 02:01:36 PM PST 23 Nov 22 02:03:34 PM PST 23 7277596308 ps
T1053 /workspace/coverage/default/9.kmac_entropy_mode_error.8096426045582459224570096886178246825056585141706287653292017345598391074892 Nov 22 02:01:55 PM PST 23 Nov 22 02:01:57 PM PST 23 64850439 ps
T1054 /workspace/coverage/default/1.kmac_test_vectors_sha3_512.103191942391158940263444826534927858878827635229795648460934187340087477183650 Nov 22 02:00:11 PM PST 23 Nov 22 02:19:44 PM PST 23 57499426673 ps
T1055 /workspace/coverage/default/13.kmac_smoke.83802578044350264221288717895182786047003549747685916080672183485334578278198 Nov 22 02:01:21 PM PST 23 Nov 22 02:01:48 PM PST 23 1925406983 ps
T1056 /workspace/coverage/default/23.kmac_long_msg_and_output.115012814311910008435623072623552554051421813763974257640409107429326483883173 Nov 22 02:02:25 PM PST 23 Nov 22 02:17:00 PM PST 23 50513696845 ps
T1057 /workspace/coverage/default/20.kmac_entropy_refresh.108396075678909554311706711285852715285327344079330863294549113331581973411942 Nov 22 02:02:25 PM PST 23 Nov 22 02:04:20 PM PST 23 7238810904 ps
T1058 /workspace/coverage/default/6.kmac_sideload.55962279194567352542142040767280083725443759636521691439094797272895055755590 Nov 22 02:00:43 PM PST 23 Nov 22 02:02:55 PM PST 23 7628111361 ps
T1059 /workspace/coverage/default/15.kmac_test_vectors_shake_256.30853395061923072746126146710948952500797700554108264349821547268211204441942 Nov 22 02:02:27 PM PST 23 Nov 22 03:18:54 PM PST 23 270085708112 ps
T1060 /workspace/coverage/default/45.kmac_app.3708680926617744406435743667345949613203061879721275544227215305092157401459 Nov 22 02:05:15 PM PST 23 Nov 22 02:06:55 PM PST 23 6076748772 ps
T1061 /workspace/coverage/default/34.kmac_test_vectors_shake_256.50603539303930465128103518495663916913496549350502356901717662567153318894785 Nov 22 02:04:17 PM PST 23 Nov 22 03:21:47 PM PST 23 270085708112 ps
T1062 /workspace/coverage/default/24.kmac_sideload.57340318191938898057224294789285346138991037818989437132593356972909103568552 Nov 22 02:02:36 PM PST 23 Nov 22 02:05:04 PM PST 23 7628111361 ps
T1063 /workspace/coverage/default/32.kmac_lc_escalation.94270784247475666438472615778349495791400466122427000738738911103424740262679 Nov 22 02:03:57 PM PST 23 Nov 22 02:04:00 PM PST 23 72761090 ps
T1064 /workspace/coverage/default/8.kmac_sideload.36146429970272760444502925015940296728022647187441340486395440943271985535332 Nov 22 02:01:44 PM PST 23 Nov 22 02:04:08 PM PST 23 7628111361 ps
T1065 /workspace/coverage/default/39.kmac_stress_all.27258291421402082288438664636790638091969297629508554338229969857560091375008 Nov 22 02:05:04 PM PST 23 Nov 22 02:20:41 PM PST 23 47207151869 ps
T1066 /workspace/coverage/default/22.kmac_error.3501047760975063900726893516155612978266276286106547437453559281939497146676 Nov 22 02:02:37 PM PST 23 Nov 22 02:05:17 PM PST 23 8137821569 ps
T1067 /workspace/coverage/default/38.kmac_lc_escalation.26642961137733550062035241993426784438825691132958721982869052941746952214475 Nov 22 02:05:08 PM PST 23 Nov 22 02:05:10 PM PST 23 72761090 ps
T1068 /workspace/coverage/default/18.kmac_test_vectors_shake_128.43005578789540338286467051611853923269500818995401449469052462577604949323762 Nov 22 02:02:23 PM PST 23 Nov 22 03:32:03 PM PST 23 320694338954 ps
T1069 /workspace/coverage/default/37.kmac_error.60314898858146723585462754258373842796566596799154391170280356544293797306277 Nov 22 02:04:49 PM PST 23 Nov 22 02:07:13 PM PST 23 8137821569 ps
T1070 /workspace/coverage/default/11.kmac_test_vectors_sha3_256.20051845631556377690459751387622086118437479792400903431268939347608594460097 Nov 22 02:01:34 PM PST 23 Nov 22 02:32:30 PM PST 23 106843317633 ps
T1071 /workspace/coverage/default/40.kmac_test_vectors_sha3_512.90111042315147284294235401282165919129067191361557955404684667273166848803350 Nov 22 02:05:02 PM PST 23 Nov 22 02:25:24 PM PST 23 57499426673 ps
T1072 /workspace/coverage/default/27.kmac_app.70940940385961645964412908784215349434992058957400515892560774363994605984923 Nov 22 02:03:16 PM PST 23 Nov 22 02:05:00 PM PST 23 6076748772 ps
T1073 /workspace/coverage/default/17.kmac_app.32309112145768977106785584291050851227822704140961620663170160256878223869246 Nov 22 02:02:25 PM PST 23 Nov 22 02:04:12 PM PST 23 6076748772 ps
T1074 /workspace/coverage/default/5.kmac_edn_timeout_error.93111850507545649105501450629064679752574978822940635716108846563153563293300 Nov 22 02:01:35 PM PST 23 Nov 22 02:01:37 PM PST 23 62261174 ps
T1075 /workspace/coverage/default/21.kmac_alert_test.85782203523251822929945940167354304184759032503813877997201323824361584226918 Nov 22 02:02:23 PM PST 23 Nov 22 02:02:30 PM PST 23 21118646 ps
T1076 /workspace/coverage/default/22.kmac_burst_write.72527283865445126715217176816259824508035458187123507345714417794238202940138 Nov 22 02:02:36 PM PST 23 Nov 22 02:09:13 PM PST 23 14830000174 ps
T1077 /workspace/coverage/default/3.kmac_smoke.84622389732971611738417649343910693179875321561476742609029215456578041113092 Nov 22 02:00:32 PM PST 23 Nov 22 02:00:59 PM PST 23 1925406983 ps
T1078 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.40739350351516934854256587606100688883228600274585260757701723848197728360527 Nov 22 12:36:03 PM PST 23 Nov 22 12:36:06 PM PST 23 32814981 ps
T1079 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.28232372419518080189199219121897750615014142007502402621728154490637697718255 Nov 22 12:36:00 PM PST 23 Nov 22 12:36:05 PM PST 23 88046682 ps
T1080 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2465324130457616379238754871840688193816803629560183566987408862948268550883 Nov 22 12:36:18 PM PST 23 Nov 22 12:36:21 PM PST 23 22940060 ps
T1081 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.73601360855568274457031916409814121221948617045778496835502851632517073278681 Nov 22 12:35:58 PM PST 23 Nov 22 12:36:02 PM PST 23 96832326 ps
T96 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.98261070319950849862495440590433767185773778049005107464698900317941060139497 Nov 22 12:35:44 PM PST 23 Nov 22 12:35:47 PM PST 23 46939868 ps
T1082 /workspace/coverage/cover_reg_top/40.kmac_intr_test.74641778537573868720593223885272599652125005313457770508494172894027130568925 Nov 22 12:36:23 PM PST 23 Nov 22 12:36:25 PM PST 23 22940060 ps
T1083 /workspace/coverage/cover_reg_top/31.kmac_intr_test.39982911572956128871782899984270489312349438405254283434048539825679921731868 Nov 22 12:36:18 PM PST 23 Nov 22 12:36:20 PM PST 23 22940060 ps
T1084 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.22720864490989946177368709139390954432292374423834794237930344333764565903897 Nov 22 12:35:35 PM PST 23 Nov 22 12:35:38 PM PST 23 30368572 ps
T1085 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.40771404646091614701599602408559034905282936820221647400972734752715070039964 Nov 22 12:35:42 PM PST 23 Nov 22 12:35:50 PM PST 23 403472730 ps
T1086 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.63111675898600943616213042793878149810557330245465293450184100049031591569717 Nov 22 12:35:51 PM PST 23 Nov 22 12:35:54 PM PST 23 32814981 ps
T1087 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.93355486951508716668665863985298795865421826955772898302135997467363860405725 Nov 22 12:35:42 PM PST 23 Nov 22 12:35:49 PM PST 23 403472730 ps
T1088 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.65555262043464885027579781745484017471139203489860404480119831292353913062834 Nov 22 12:35:37 PM PST 23 Nov 22 12:35:40 PM PST 23 30368572 ps
T1089 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.78420349646872477519737586962864115916069224071824992660716521581026760430298 Nov 22 12:35:50 PM PST 23 Nov 22 12:35:53 PM PST 23 38832790 ps
T8 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.28822257408153204955153501530154084022867125047551308220061958045525446512006 Nov 22 12:35:18 PM PST 23 Nov 22 12:35:23 PM PST 23 193117270 ps
T1090 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.70830863530655750882540077187113323625201974932894935622605620886652950307942 Nov 22 12:35:27 PM PST 23 Nov 22 12:35:28 PM PST 23 16922251 ps
T1091 /workspace/coverage/cover_reg_top/42.kmac_intr_test.82981450641881044527639429027726851440710180479810894876174609585333879455273 Nov 22 12:36:17 PM PST 23 Nov 22 12:36:20 PM PST 23 22940060 ps
T1092 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.71333648595451870697986927586838969445905656122824987629656728612817933201407 Nov 22 12:36:01 PM PST 23 Nov 22 12:36:05 PM PST 23 38832790 ps
T1093 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.16715529615209379075402199826226067168062499212359606406472577335980028022143 Nov 22 12:35:46 PM PST 23 Nov 22 12:35:49 PM PST 23 88046682 ps
T1094 /workspace/coverage/cover_reg_top/7.kmac_intr_test.90052494982635806687532614742817296321021985683535064378094379074596630709659 Nov 22 12:35:36 PM PST 23 Nov 22 12:35:39 PM PST 23 22940060 ps
T1095 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.89752465663984800966439526146591447774956845163586625292464723409223938172043 Nov 22 12:35:39 PM PST 23 Nov 22 12:35:42 PM PST 23 32814981 ps
T9 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.84856397804777485531617342009177037981926411194006390651485788910048726518159 Nov 22 12:36:03 PM PST 23 Nov 22 12:36:08 PM PST 23 193117270 ps
T1096 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.88246809063607131597711104555182294798641144890840313882459837888553385247696 Nov 22 12:35:20 PM PST 23 Nov 22 12:35:23 PM PST 23 88046682 ps
T1097 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.56670309931240001979179610129688973426369895943171743793479561702550683528742 Nov 22 12:35:47 PM PST 23 Nov 22 12:35:53 PM PST 23 96832326 ps
T1098 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.19933083479819976323780779755632441702317537261332506959266715820180678857030 Nov 22 12:35:22 PM PST 23 Nov 22 12:35:34 PM PST 23 934950621 ps
T1099 /workspace/coverage/cover_reg_top/20.kmac_intr_test.93152063837508361700990652821676709937038532858637952310975739667810438333952 Nov 22 12:36:16 PM PST 23 Nov 22 12:36:17 PM PST 23 22940060 ps
T97 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.22597260635212838661679430474041326334753656512580133070580548444178805819570 Nov 22 12:35:24 PM PST 23 Nov 22 12:35:26 PM PST 23 46939868 ps
T1100 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.54432085209513643741970051459632380381170632021451099651998826076643608265847 Nov 22 12:35:31 PM PST 23 Nov 22 12:35:37 PM PST 23 32814981 ps
T1101 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.5868319998346958443870902956649978451124572565077380861886854347263140087511 Nov 22 12:35:46 PM PST 23 Nov 22 12:35:49 PM PST 23 96832326 ps
T1102 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.57776249288565011829265044954230537790008187850579511226842414988159021925785 Nov 22 12:35:54 PM PST 23 Nov 22 12:35:56 PM PST 23 38832790 ps
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T1186 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.10695789199554132931823968034113169036334902836070252049769489740510309297088 Nov 22 12:35:52 PM PST 23 Nov 22 12:35:55 PM PST 23 96832326 ps
T1187 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.49883758909343833243637593572690180352050444548474613299336418492957422671487 Nov 22 12:36:04 PM PST 23 Nov 22 12:36:06 PM PST 23 38832790 ps
T1188 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.38704430205905332229451996355456742453511223800118814920553198996627548745046 Nov 22 12:35:52 PM PST 23 Nov 22 12:35:56 PM PST 23 193117270 ps
T1189 /workspace/coverage/cover_reg_top/35.kmac_intr_test.105999159715522700253833087881089333359256187832684183545820541249669581863488 Nov 22 12:36:24 PM PST 23 Nov 22 12:36:26 PM PST 23 22940060 ps
T1190 /workspace/coverage/cover_reg_top/32.kmac_intr_test.110431962046427735073815854228237124076611765653944294101729511915620789790450 Nov 22 12:36:25 PM PST 23 Nov 22 12:36:27 PM PST 23 22940060 ps
T1191 /workspace/coverage/cover_reg_top/23.kmac_intr_test.1954697805367638033590485941445064811066749610072700626667772837690479323401 Nov 22 12:36:03 PM PST 23 Nov 22 12:36:06 PM PST 23 22940060 ps
T1192 /workspace/coverage/cover_reg_top/17.kmac_intr_test.62323082027859977090872477872655719717769664780301300806142050344797935001996 Nov 22 12:35:58 PM PST 23 Nov 22 12:36:01 PM PST 23 22940060 ps
T1193 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.102018638890666998616469971555913004800144168805165982906884048200493258252639 Nov 22 12:35:52 PM PST 23 Nov 22 12:35:54 PM PST 23 30368572 ps
T1194 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.109230501357822276761583969080239366065035219631932267228162510861550512610072 Nov 22 12:35:49 PM PST 23 Nov 22 12:35:53 PM PST 23 96832326 ps
T1195 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.50206140901788179664425155382583937215618042880466915495669103669338290423936 Nov 22 12:35:36 PM PST 23 Nov 22 12:35:39 PM PST 23 88046682 ps
T1196 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.70674164774389970187206565599617776918755807010721738688004447169780159928966 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:01 PM PST 23 30368572 ps
T1197 /workspace/coverage/cover_reg_top/47.kmac_intr_test.38317335782487673276448503186024537967227168740860170407720450093448314585095 Nov 22 12:36:21 PM PST 23 Nov 22 12:36:23 PM PST 23 22940060 ps
T1198 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.37410692360708953162926763328792564451774378644534250933104126184214385673009 Nov 22 12:35:31 PM PST 23 Nov 22 12:35:37 PM PST 23 88046682 ps
T1199 /workspace/coverage/cover_reg_top/39.kmac_intr_test.104628357603652408456221340462763438137454879244372097864816472016808208291035 Nov 22 12:36:28 PM PST 23 Nov 22 12:36:30 PM PST 23 22940060 ps
T1200 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.35136628543914152208262835103891682572652387021739515196482058821283894325256 Nov 22 12:35:55 PM PST 23 Nov 22 12:36:02 PM PST 23 193117270 ps
T1201 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.11571485960351588577285071701038321641579799402217594088531387123990586336101 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:01 PM PST 23 38832790 ps
T99 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.79223228074306128699415414275018969308659897032204827183613686497863046575953 Nov 22 12:35:34 PM PST 23 Nov 22 12:35:37 PM PST 23 46939868 ps
T1202 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.111133577686643614570057501277965502233086297426474812806034459130942060936024 Nov 22 12:36:10 PM PST 23 Nov 22 12:36:13 PM PST 23 96832326 ps
T1203 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2460163896353595665861793550239651154559882906390490172657502351500353848992 Nov 22 12:35:56 PM PST 23 Nov 22 12:36:01 PM PST 23 30368572 ps
T1204 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.109653702811625536802517802115795549577684621297666163226082005338259215650425 Nov 22 12:35:22 PM PST 23 Nov 22 12:35:24 PM PST 23 32814981 ps
T1205 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.109770371100005006118579025266666524106726631195453509790894536260860405458468 Nov 22 12:35:54 PM PST 23 Nov 22 12:35:57 PM PST 23 30368572 ps
T1206 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.102224403945236619780718911364287234042770914335976579808195602234440666456872 Nov 22 12:35:26 PM PST 23 Nov 22 12:35:38 PM PST 23 934950621 ps
T1207 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.52847216774527413830995532685592476290383116550305637219769019794894255253493 Nov 22 12:35:22 PM PST 23 Nov 22 12:35:24 PM PST 23 29368580 ps
T1208 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.77209444563764348536294137041274514647119645554077256998865491936121613044748 Nov 22 12:35:27 PM PST 23 Nov 22 12:35:31 PM PST 23 193117270 ps
T1209 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.32473041462813673667721257357217481785731737961038386639462481447578717752588 Nov 22 12:36:10 PM PST 23 Nov 22 12:36:12 PM PST 23 88046682 ps
T1210 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.106194833758208318522319269360604688015785527094754570449863716190961471132409 Nov 22 12:35:38 PM PST 23 Nov 22 12:35:44 PM PST 23 193117270 ps
T1211 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.17719263704276398144669831062862628652955181200504470236559030082451604394702 Nov 22 12:35:37 PM PST 23 Nov 22 12:35:41 PM PST 23 32814981 ps
T1212 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.85391350083220136755004677679016150144909285946096436937225992961388731727516 Nov 22 12:35:47 PM PST 23 Nov 22 12:35:51 PM PST 23 96832326 ps
T1213 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.53957500139585702611415649816536883494570301559914807603692968224085976623001 Nov 22 12:35:21 PM PST 23 Nov 22 12:35:34 PM PST 23 934950621 ps
T1214 /workspace/coverage/cover_reg_top/1.kmac_intr_test.110653178880602959553012968553223950249381351947310265781027837984847456406016 Nov 22 12:35:46 PM PST 23 Nov 22 12:35:48 PM PST 23 22940060 ps
T1215 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.62404356933309992116892285344380780437285381731453148542015863870758307891554 Nov 22 12:35:21 PM PST 23 Nov 22 12:35:24 PM PST 23 16922251 ps
T1216 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.30336896691159536253145040558105943488880408187012161748688440788126819965190 Nov 22 12:35:45 PM PST 23 Nov 22 12:35:58 PM PST 23 934950621 ps
T1217 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.81559427994451144031749245305046256757848743581990221138110371340028285992247 Nov 22 12:36:06 PM PST 23 Nov 22 12:36:08 PM PST 23 30368572 ps
T1218 /workspace/coverage/cover_reg_top/41.kmac_intr_test.53389919907562500055918172095911491136931336113972598349702209769698921749625 Nov 22 12:36:19 PM PST 23 Nov 22 12:36:21 PM PST 23 22940060 ps
T1219 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.45031461850779788727587499885585505544382714782514885392134354800379805857836 Nov 22 12:35:32 PM PST 23 Nov 22 12:35:39 PM PST 23 193117270 ps
T1220 /workspace/coverage/cover_reg_top/11.kmac_intr_test.17884200366029692362931884763799714371646347460181923301000636313472048162723 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:01 PM PST 23 22940060 ps
T1221 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.114126658306622401584085227920583951011374503231392745727662867561539674844257 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:01 PM PST 23 88046682 ps
T1222 /workspace/coverage/cover_reg_top/36.kmac_intr_test.19144963162824094354760633453822698343894746055483761615642357012855285610285 Nov 22 12:37:06 PM PST 23 Nov 22 12:37:08 PM PST 23 22940060 ps
T1223 /workspace/coverage/cover_reg_top/19.kmac_intr_test.89623119058319672327066196408024114959706724977860530675726111668074576805346 Nov 22 12:36:04 PM PST 23 Nov 22 12:36:06 PM PST 23 22940060 ps
T1224 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.49586069668220300647807915840458647018944994168516405310532321014409338241365 Nov 22 12:35:41 PM PST 23 Nov 22 12:35:45 PM PST 23 193117270 ps
T1225 /workspace/coverage/cover_reg_top/26.kmac_intr_test.84163835384272598449542752629079835849714142374986392205034281367224642491504 Nov 22 12:36:21 PM PST 23 Nov 22 12:36:24 PM PST 23 22940060 ps
T1226 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.63033842289252704851069599009108603715585976788909967833621230234028691933466 Nov 22 12:35:58 PM PST 23 Nov 22 12:36:02 PM PST 23 103242989 ps
T1227 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.57402379745078910170474492397329093384609494090531562433303761379794111065533 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:02 PM PST 23 96832326 ps
T1228 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.16508775115308783817480135367872415109392769608865497107393501356801605923825 Nov 22 12:35:35 PM PST 23 Nov 22 12:35:38 PM PST 23 30368572 ps
T1229 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.88316657271889017182786359306514135314160192064176584409891025625119403488770 Nov 22 12:36:05 PM PST 23 Nov 22 12:36:07 PM PST 23 38832790 ps
T1230 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.91354364200257416653195607407010735067522039747466928813158589817642982836414 Nov 22 12:36:08 PM PST 23 Nov 22 12:36:10 PM PST 23 32814981 ps
T1231 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.75919409709861720753180791720651838366521954039089094580910512957831708275246 Nov 22 12:35:52 PM PST 23 Nov 22 12:35:55 PM PST 23 103242989 ps
T1232 /workspace/coverage/cover_reg_top/16.kmac_intr_test.83677155034001855308829422018858489379549279999955565156592657650758777686847 Nov 22 12:35:56 PM PST 23 Nov 22 12:36:01 PM PST 23 22940060 ps
T1233 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.73281542264270560665702443230239313452327423600924570164757661729982616584334 Nov 22 12:35:46 PM PST 23 Nov 22 12:35:51 PM PST 23 103242989 ps
T1234 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.69615596488814182892972365625726758319441392657194153065432129734534222867182 Nov 22 12:35:44 PM PST 23 Nov 22 12:35:48 PM PST 23 96832326 ps
T1235 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.48367736479839219060476753265426525265037244875476241600086600722991982032119 Nov 22 12:35:35 PM PST 23 Nov 22 12:35:38 PM PST 23 103242989 ps
T1236 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.21428353593286476125420826388399445395718782011915284247193375787786392189338 Nov 22 12:35:41 PM PST 23 Nov 22 12:35:45 PM PST 23 193117270 ps
T1237 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.47332913898201569309113485619775747735889272641623672876013197431928645190646 Nov 22 12:35:57 PM PST 23 Nov 22 12:36:01 PM PST 23 30368572 ps
T1238 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.23427353190882902429894841489219316329452583211346423264673013865016630468558 Nov 22 12:35:43 PM PST 23 Nov 22 12:35:48 PM PST 23 193117270 ps
T1239 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.11794146338056204453610957262156496954432617198069585315293064297621439764205 Nov 22 12:35:56 PM PST 23 Nov 22 12:36:01 PM PST 23 96832326 ps
T1240 /workspace/coverage/cover_reg_top/22.kmac_intr_test.114469326964369343513319559147603217458102123348122472680526188861176022409402 Nov 22 12:36:08 PM PST 23 Nov 22 12:36:10 PM PST 23 22940060 ps

Test location /workspace/coverage/default/9.kmac_stress_all.45454827385490766864513993109623418136429669004274097620247561262327395018805
Short name T30
Test name
Test status
Simulation time 47207151869 ps
CPU time 871.69 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:16:09 PM PST 23
Peak memory 339844 kb
Host smart-2c06ed7a-e5ab-45eb-b20a-bbda7004a60c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=45454827385490766864513993109623418136429669004274097620247561262327395018805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_str
ess_all.45454827385490766864513993109623418136429669004274097620247561262327395018805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.42545936114022009804604287253911888968396790420634102182601022629705950905982
Short name T17
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:36:19 PM PST 23
Finished Nov 22 12:36:21 PM PST 23
Peak memory 216244 kb
Host smart-66aedc6b-1449-470f-b3a7-412ec1eebb97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42545936114022009804604287253911888968396790420634102182601022629705950905982 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.42545936114022009804604287253911888968396790420634102182601022629705950905982 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.34876967625943154121329361065647578274644221957046311309664191418048337645865
Short name T3
Test name
Test status
Simulation time 193117270 ps
CPU time 2.98 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:03 PM PST 23
Peak memory 216412 kb
Host smart-c74e415a-3150-4b31-a065-4e789e5971e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34876967625943154121329361065647578274644221957046311309664191418048337645865 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.34876967625943154121329361065647578274644221957046311309664191418048337645865 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.90836669703474873052916594869457983756736126301182500333042392857087314834098
Short name T22
Test name
Test status
Simulation time 7277596308 ps
CPU time 116.31 seconds
Started Nov 22 02:00:31 PM PST 23
Finished Nov 22 02:02:28 PM PST 23
Peak memory 243888 kb
Host smart-8d44c687-df51-4dc5-bc0d-b2fb8b5116f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90836669703474873052916594869457983756736126301182500333042392857087314834098 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_app_with_partial_data.90836669703474873052916594869457983756736126301182500333042392857087314834098 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.19605688805053014560679142271100473270931523808431687417764420483280270986855
Short name T27
Test name
Test status
Simulation time 6415496062 ps
CPU time 55.69 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 277304 kb
Host smart-22ef7ec9-a7cb-46bc-a419-747cb8deedbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19605688805053014560679142271100473270931523808431687417764420483280270986855 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.kmac_sec_cm.19605688805053014560679142271100473270931523808431687417764420483280270986855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.26522606477014102123744119055316403057274047672129686037878555031164641228140
Short name T2
Test name
Test status
Simulation time 103242989 ps
CPU time 2.02 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 216556 kb
Host smart-d2fd5f03-ff53-4234-a158-20dadf3d0184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26522606477014102123744119055316403057274047672129686037878555031164641228140 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.26522606477014102123744119055316403057274047672129686037878555031164641228140 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/default/16.kmac_error.767739370852537149645628556854095817880680497468843070237358051744697588215
Short name T52
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.13 seconds
Started Nov 22 02:02:03 PM PST 23
Finished Nov 22 02:04:49 PM PST 23
Peak memory 252692 kb
Host smart-55a087d3-564f-4469-8fb4-1cb6fc9ef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767739370852537149645628556854095817880680497468843070237358051744697588215 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_error.767739370852537149645628556854095817880680497468843070237358051744697588215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.84585167407653347497604949322346133070120738859355503485850733931709937021709
Short name T24
Test name
Test status
Simulation time 72761090 ps
CPU time 1.51 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 220196 kb
Host smart-bb7d7354-7ad2-4fac-bc89-3c95e0f9570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84585167407653347497604949322346133070120738859355503485850733931709937021709 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.kmac_lc_escalation.84585167407653347497604949322346133070120738859355503485850733931709937021709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.52014593084888250701179858382227935788357375203700461937908166355730376266244
Short name T14
Test name
Test status
Simulation time 96832326 ps
CPU time 1.8 seconds
Started Nov 22 12:35:36 PM PST 23
Finished Nov 22 12:35:40 PM PST 23
Peak memory 219956 kb
Host smart-1ed1dbdb-16e6-4b50-a845-8e3d30776522
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520145930848882507011798583822279357883573752037004619379081663557303
76266244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.520145930848882507011798583822279357883573752037
00461937908166355730376266244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.11921359309918307529169082585016397486150233580339758011491388884328469285695
Short name T21
Test name
Test status
Simulation time 270085708112 ps
CPU time 4596.56 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 03:19:10 PM PST 23
Peak memory 577252 kb
Host smart-50904379-1691-414a-9fa9-070b4e801fb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=11921359309918307529169082585016397486150233580339758011491388884328469285695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_test_vectors_shake_256.11921359309918307529169082585016397486150233580339758011491388884328469285695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.32066634027510088255133099515743029188341142190228736403047070948155581083745
Short name T56
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.04 seconds
Started Nov 22 02:01:52 PM PST 23
Finished Nov 22 02:02:15 PM PST 23
Peak memory 219380 kb
Host smart-b2ce7d36-f31d-4b84-9879-ec8f3c6b226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32066634027510088255133099515743029188341142190228736403047070948155581083745 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.kmac_entropy_ready_error.32066634027510088255133099515743029188341142190228736403047070948155581083745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.92974366559309488254105702325645977148678341857038435049961279785087093220043
Short name T53
Test name
Test status
Simulation time 64850439 ps
CPU time 1.22 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219044 kb
Host smart-a23976a7-3dbc-4d07-8807-11cd405d440c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=92974366559309488254105702325645977148678341857038435049961279785087093220043 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.92974366559309488254105702325645977148678341857038435049961279785087093220043 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.19933083479819976323780779755632441702317537261332506959266715820180678857030
Short name T1098
Test name
Test status
Simulation time 934950621 ps
CPU time 10.97 seconds
Started Nov 22 12:35:22 PM PST 23
Finished Nov 22 12:35:34 PM PST 23
Peak memory 216504 kb
Host smart-a5f4b4db-a3db-4e26-800d-ac5d74f86e65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933083479819976323780779755632441702317537261332506959266715820180678857030 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.19933083479819976323780779755632441702317537261332506959266715820180678857030 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.6501707511478335955069873732020807509308601075460286560414116429917510294811
Short name T68
Test name
Test status
Simulation time 46939868 ps
CPU time 1.21 seconds
Started Nov 22 12:35:24 PM PST 23
Finished Nov 22 12:35:25 PM PST 23
Peak memory 216376 kb
Host smart-3be851c4-e668-46f9-bc21-e5d267d87c4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6501707511478335955069873732020807509308601075460286560414116429917510294811 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.65017075114783359550698737320208075093086010754602865604141164299175102
94811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/1.kmac_key_error.70341659063964791022526806630172335536797417534584210853442948627355234444364
Short name T77
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.8 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 02:00:35 PM PST 23
Peak memory 219144 kb
Host smart-0a1ec56f-5bf5-4825-87e1-d21721d7e7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70341659063964791022526806630172335536797417534584210853442948627355234444364 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.kmac_key_error.70341659063964791022526806630172335536797417534584210853442948627355234444364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.25757544948154444385000242175968543090556242032839642546831967049751214089742
Short name T61
Test name
Test status
Simulation time 7238810904 ps
CPU time 113.08 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:04:40 PM PST 23
Peak memory 243860 kb
Host smart-b7539a66-b3bb-49c8-b304-4d8ba1fae520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25757544948154444385000242175968543090556242032839642546831967049751214089742 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.kmac_entropy_refresh.25757544948154444385000242175968543090556242032839642546831967049751214089742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.722826533125099362845377256312703634550765613976152094546930019945585212085
Short name T64
Test name
Test status
Simulation time 62261174 ps
CPU time 1.23 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:00:30 PM PST 23
Peak memory 219100 kb
Host smart-fe802501-ca37-4196-a967-36594063aed6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=722826533125099362845377256312703634550765613976152094546930019945585212085 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.kmac_edn_timeout_error.722826533125099362845377256312703634550765613976152094546930019945585212085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.95897437189405424261689802634442191324341001393871569660180552918381449517145
Short name T12
Test name
Test status
Simulation time 88046682 ps
CPU time 1.64 seconds
Started Nov 22 12:35:31 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216392 kb
Host smart-a2547bbb-8e52-4e3e-b262-1ebb08241905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95897437189405424261689802634442191324341001393871569660180552918381449517145
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.958974371894054242616898026344421913243410013938715696601805529183
81449517145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.kmac_alert_test.48472545343861979587059544967853831782269540867913575927933495528746702779945
Short name T73
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:00:27 PM PST 23
Finished Nov 22 02:00:29 PM PST 23
Peak memory 218904 kb
Host smart-56c2617c-013d-4152-8543-72d93f649ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48472545343861979587059544967853831782269540867913575927933495528746702779945 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.kmac_alert_test.48472545343861979587059544967853831782269540867913575927933495528746702779945 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.23156472926612619043515584703891896019946771561593765911194300044360574357336
Short name T1171
Test name
Test status
Simulation time 403472730 ps
CPU time 5.92 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:51 PM PST 23
Peak memory 216488 kb
Host smart-8bbccbad-b418-442f-9290-0569056f927c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23156472926612619043515584703891896019946771561593765911194300044360574357336 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.23156472926612619043515584703891896019946771561593765911194300044360574357336 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.80375936770982219717565512903397826555423357974918160123672282285533156033575
Short name T1105
Test name
Test status
Simulation time 29368580 ps
CPU time 1 seconds
Started Nov 22 12:35:31 PM PST 23
Finished Nov 22 12:35:36 PM PST 23
Peak memory 216228 kb
Host smart-d0af24dc-14b8-4d36-9dee-e78df523cd45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80375936770982219717565512903397826555423357974918160123672282285533156033575 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.80375936770982219717565512903397826555423357974918160123672282285533156033575 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.45037975525799007648815858975784703668550758042806918505043273973176880598203
Short name T1126
Test name
Test status
Simulation time 30368572 ps
CPU time 1.28 seconds
Started Nov 22 12:35:34 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 219904 kb
Host smart-7d4b8143-33c1-4c95-a157-2d2a173a8f4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4503797552579900764881585897578470366855075
8042806918505043273973176880598203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4503797552579900764881585
8975784703668550758042806918505043273973176880598203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.41419350976370852051202533405311182762360435100182231707294795852792338184539
Short name T1127
Test name
Test status
Simulation time 32814981 ps
CPU time 1.04 seconds
Started Nov 22 12:35:24 PM PST 23
Finished Nov 22 12:35:25 PM PST 23
Peak memory 216276 kb
Host smart-e842f765-7b3d-4a04-97a5-c59e8c8c9106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419350976370852051202533405311182762360435100182231707294795852792338184539 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.41419350976370852051202533405311182762360435100182231707294795852792338184539 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.83017056668151617760916961763683380355312663017410608024938962258782703245374
Short name T67
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:35:25 PM PST 23
Finished Nov 22 12:35:28 PM PST 23
Peak memory 216252 kb
Host smart-d00f5913-6e4d-493e-a2db-dd333a8ef475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83017056668151617760916961763683380355312663017410608024938962258782703245374 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.83017056668151617760916961763683380355312663017410608024938962258782703245374 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.49474973312012391718333785212783665393424806607438919213565748960309184325220
Short name T121
Test name
Test status
Simulation time 16922251 ps
CPU time 0.78 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:24 PM PST 23
Peak memory 216032 kb
Host smart-064d48d4-0f87-46f1-97c4-6593dbc5f329
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49474973312012391718333785212783665393424806607438919213565748960309184325220 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.49474973312012391718333785212783665393424806607438919213565748960309184325220 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.22059128352691335978213982988966821910132452589001244383062913067325742857228
Short name T1138
Test name
Test status
Simulation time 88046682 ps
CPU time 1.63 seconds
Started Nov 22 12:35:25 PM PST 23
Finished Nov 22 12:35:28 PM PST 23
Peak memory 216472 kb
Host smart-95709573-5841-4c99-8b66-aabb3e3a76a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059128352691335978213982988966821910132452589001244383062913067325742857228
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.220591283526913359782139829889668219101324525890012443830629130673
25742857228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.32485414975355800016147346994970788677016301941853534124786215787725186161515
Short name T1134
Test name
Test status
Simulation time 38832790 ps
CPU time 1.12 seconds
Started Nov 22 12:35:03 PM PST 23
Finished Nov 22 12:35:05 PM PST 23
Peak memory 216536 kb
Host smart-0169d0d7-5447-4125-bcbe-909ac6ef003b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485414975355800016147346994970788677016301941853534124786215787725186161515 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.324854149753558000161473469949707886770163019418535341247862157877251861
61515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.14113634512417452784069813040375321233212940431826743570805054210485404752486
Short name T1112
Test name
Test status
Simulation time 96832326 ps
CPU time 1.84 seconds
Started Nov 22 12:35:00 PM PST 23
Finished Nov 22 12:35:02 PM PST 23
Peak memory 219952 kb
Host smart-dc84fc21-c1d5-4918-bea9-771a3145f558
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141136345124174527840698130403753212332129404318267435708050542104854
04752486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.141136345124174527840698130403753212332129404318
26743570805054210485404752486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.48367736479839219060476753265426525265037244875476241600086600722991982032119
Short name T1235
Test name
Test status
Simulation time 103242989 ps
CPU time 2.03 seconds
Started Nov 22 12:35:35 PM PST 23
Finished Nov 22 12:35:38 PM PST 23
Peak memory 216572 kb
Host smart-db4381ca-8471-4504-9b9f-da20fb8fdb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48367736479839219060476753265426525265037244875476241600086600722991982032119 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.48367736479839219060476753265426525265037244875476241600086600722991982032119 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.56235074541662245734004040609827235620613150174520981513683534567053590450923
Short name T1103
Test name
Test status
Simulation time 193117270 ps
CPU time 2.98 seconds
Started Nov 22 12:35:30 PM PST 23
Finished Nov 22 12:35:38 PM PST 23
Peak memory 216480 kb
Host smart-5cba4c26-3d75-44b5-9f4f-f659c7b76ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56235074541662245734004040609827235620613150174520981513683534567053590450923 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.56235074541662245734004040609827235620613150174520981513683534567053590450923 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.92846190130019110466123825760112446765722196372704198714706898386899824510085
Short name T66
Test name
Test status
Simulation time 403472730 ps
CPU time 5.85 seconds
Started Nov 22 12:35:19 PM PST 23
Finished Nov 22 12:35:26 PM PST 23
Peak memory 216580 kb
Host smart-035b08c6-75fc-4d32-b86f-df352a719367
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92846190130019110466123825760112446765722196372704198714706898386899824510085 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.92846190130019110466123825760112446765722196372704198714706898386899824510085 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.53957500139585702611415649816536883494570301559914807603692968224085976623001
Short name T1213
Test name
Test status
Simulation time 934950621 ps
CPU time 10.66 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:34 PM PST 23
Peak memory 216504 kb
Host smart-e7476807-e7d7-4449-87a0-9c1000c58bd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53957500139585702611415649816536883494570301559914807603692968224085976623001 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.53957500139585702611415649816536883494570301559914807603692968224085976623001 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.52847216774527413830995532685592476290383116550305637219769019794894255253493
Short name T1207
Test name
Test status
Simulation time 29368580 ps
CPU time 1.01 seconds
Started Nov 22 12:35:22 PM PST 23
Finished Nov 22 12:35:24 PM PST 23
Peak memory 216232 kb
Host smart-fdd9fb16-ae7f-4812-895e-6405802f1a1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52847216774527413830995532685592476290383116550305637219769019794894255253493 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.52847216774527413830995532685592476290383116550305637219769019794894255253493 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.76464665580744773870963835845112052051658982724272606804113389526330709090305
Short name T1177
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 12:35:43 PM PST 23
Finished Nov 22 12:35:45 PM PST 23
Peak memory 219868 kb
Host smart-d6905457-b0ef-4cbb-81c7-888f137a520d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7646466558074477387096383584511205205165898
2724272606804113389526330709090305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.7646466558074477387096383
5845112052051658982724272606804113389526330709090305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.89752465663984800966439526146591447774956845163586625292464723409223938172043
Short name T1095
Test name
Test status
Simulation time 32814981 ps
CPU time 0.94 seconds
Started Nov 22 12:35:39 PM PST 23
Finished Nov 22 12:35:42 PM PST 23
Peak memory 216228 kb
Host smart-34aa4c47-3e24-4701-b1cf-e920d4854421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89752465663984800966439526146591447774956845163586625292464723409223938172043 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.89752465663984800966439526146591447774956845163586625292464723409223938172043 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.110653178880602959553012968553223950249381351947310265781027837984847456406016
Short name T1214
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216244 kb
Host smart-b912a7a1-d665-4e6a-849e-e7ecece9684d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110653178880602959553012968553223950249381351947310265781027837984847456406016 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.110653178880602959553012968553223950249381351947310265781027837984847456406016 +enable_masking=1
+sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.98261070319950849862495440590433767185773778049005107464698900317941060139497
Short name T96
Test name
Test status
Simulation time 46939868 ps
CPU time 1.24 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:47 PM PST 23
Peak memory 216388 kb
Host smart-c2bc6f9d-9fd5-4311-beac-63136e585e80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98261070319950849862495440590433767185773778049005107464698900317941060139497 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.9826107031995084986249544059043376718577377804900510746469890031794106
0139497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.62404356933309992116892285344380780437285381731453148542015863870758307891554
Short name T1215
Test name
Test status
Simulation time 16922251 ps
CPU time 0.76 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:24 PM PST 23
Peak memory 216244 kb
Host smart-a19758aa-7747-46fa-959b-e105226839f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62404356933309992116892285344380780437285381731453148542015863870758307891554 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.62404356933309992116892285344380780437285381731453148542015863870758307891554 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.23138913803593406196064449587368022977892896214799498352327862305395615251265
Short name T71
Test name
Test status
Simulation time 38832790 ps
CPU time 1 seconds
Started Nov 22 12:35:29 PM PST 23
Finished Nov 22 12:35:32 PM PST 23
Peak memory 216488 kb
Host smart-1e1361d7-cf47-45aa-aecf-b35c188079ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23138913803593406196064449587368022977892896214799498352327862305395615251265 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.231389138035934061960644495873680229778928962147994983523278623053956152
51265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.47675351896503643798487070223605248191750255803897624650063891724172891505386
Short name T1154
Test name
Test status
Simulation time 96832326 ps
CPU time 1.76 seconds
Started Nov 22 12:35:24 PM PST 23
Finished Nov 22 12:35:28 PM PST 23
Peak memory 219940 kb
Host smart-13ec905d-e3a5-4530-92cb-abee6063a5d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476753518965036437984870702236052481917502558038976246500638917241728
91505386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.476753518965036437984870702236052481917502558038
97624650063891724172891505386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.13015738485789009832084822575606149227963758913084261031600529289652707540321
Short name T95
Test name
Test status
Simulation time 103242989 ps
CPU time 1.97 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 216564 kb
Host smart-98937b12-d2a4-4a64-9985-153d19460a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13015738485789009832084822575606149227963758913084261031600529289652707540321 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.13015738485789009832084822575606149227963758913084261031600529289652707540321 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.45031461850779788727587499885585505544382714782514885392134354800379805857836
Short name T1219
Test name
Test status
Simulation time 193117270 ps
CPU time 2.9 seconds
Started Nov 22 12:35:32 PM PST 23
Finished Nov 22 12:35:39 PM PST 23
Peak memory 216464 kb
Host smart-ad572f89-7d09-4b24-8694-b9cd8e40579f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45031461850779788727587499885585505544382714782514885392134354800379805857836 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.45031461850779788727587499885585505544382714782514885392134354800379805857836 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.85207044469111882328953576548684361731731436880709924505553350788326506466845
Short name T72
Test name
Test status
Simulation time 30368572 ps
CPU time 1.25 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:10 PM PST 23
Peak memory 219928 kb
Host smart-8d6f9533-8754-4716-a419-d7808c9b4195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8520704446911188232895357654868436173173143
6880709924505553350788326506466845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.852070444691118823289535
76548684361731731436880709924505553350788326506466845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.17719263704276398144669831062862628652955181200504470236559030082451604394702
Short name T1211
Test name
Test status
Simulation time 32814981 ps
CPU time 1.02 seconds
Started Nov 22 12:35:37 PM PST 23
Finished Nov 22 12:35:41 PM PST 23
Peak memory 216236 kb
Host smart-6cf60d33-7f14-4d9c-8d92-0d44c790f1e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719263704276398144669831062862628652955181200504470236559030082451604394702 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.17719263704276398144669831062862628652955181200504470236559030082451604394702 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.91290760232269294195274642131719570191791790638149623762823253362768872516136
Short name T111
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216128 kb
Host smart-1dd461b9-bb02-46d7-b2c0-044f15271645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91290760232269294195274642131719570191791790638149623762823253362768872516136 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.91290760232269294195274642131719570191791790638149623762823253362768872516136 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.50206140901788179664425155382583937215618042880466915495669103669338290423936
Short name T1195
Test name
Test status
Simulation time 88046682 ps
CPU time 1.69 seconds
Started Nov 22 12:35:36 PM PST 23
Finished Nov 22 12:35:39 PM PST 23
Peak memory 216432 kb
Host smart-ad849f08-ee06-4114-8882-71949f48c59f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50206140901788179664425155382583937215618042880466915495669103669338290423936
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.50206140901788179664425155382583937215618042880466915495669103669
338290423936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.83018728282097905804962922952603468979233829416261666929027369236168228818933
Short name T1148
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216540 kb
Host smart-98dc2ed2-9962-4f10-b1f9-7ce235cc76bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83018728282097905804962922952603468979233829416261666929027369236168228818933 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.83018728282097905804962922952603468979233829416261666929027369236168228
818933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.5868319998346958443870902956649978451124572565077380861886854347263140087511
Short name T1101
Test name
Test status
Simulation time 96832326 ps
CPU time 1.84 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:49 PM PST 23
Peak memory 219964 kb
Host smart-6d2bcffb-ae1c-44ea-a1cd-541931d65adb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586831999834695844387090295664997845112457256507738086188685434726314
0087511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.586831999834695844387090295664997845112457256507
7380861886854347263140087511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.73281542264270560665702443230239313452327423600924570164757661729982616584334
Short name T1233
Test name
Test status
Simulation time 103242989 ps
CPU time 2.15 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:51 PM PST 23
Peak memory 216572 kb
Host smart-ca9d0d4d-a7b1-45bf-be3c-8bdd3e7bd8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73281542264270560665702443230239313452327423600924570164757661729982616584334 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.73281542264270560665702443230239313452327423600924570164757661729982616584334 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.49586069668220300647807915840458647018944994168516405310532321014409338241365
Short name T1224
Test name
Test status
Simulation time 193117270 ps
CPU time 2.97 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:45 PM PST 23
Peak memory 216488 kb
Host smart-9810b9d0-9320-4ed3-a373-da8c4ec0643e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49586069668220300647807915840458647018944994168516405310532321014409338241365 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.49586069668220300647807915840458647018944994168516405310532321014409338241365 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.47332913898201569309113485619775747735889272641623672876013197431928645190646
Short name T1237
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 218880 kb
Host smart-ed5bfc30-1975-45da-9b95-59d00be8235a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4733291389820156930911348561977574773588927
2641623672876013197431928645190646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.473329138982015693091134
85619775747735889272641623672876013197431928645190646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.74262086017878085250594863924984734481283716884366259467247417808466865225065
Short name T15
Test name
Test status
Simulation time 32814981 ps
CPU time 1.01 seconds
Started Nov 22 12:35:49 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 216256 kb
Host smart-c01a2cf9-94c1-4592-af46-fc28b65d83e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74262086017878085250594863924984734481283716884366259467247417808466865225065 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.74262086017878085250594863924984734481283716884366259467247417808466865225065 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.17884200366029692362931884763799714371646347460181923301000636313472048162723
Short name T1220
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 214932 kb
Host smart-c0353415-a49b-4326-b5af-53360c1c3170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17884200366029692362931884763799714371646347460181923301000636313472048162723 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.17884200366029692362931884763799714371646347460181923301000636313472048162723 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.109203099443578224554599570870242736862348829861007932034201497146791726222747
Short name T102
Test name
Test status
Simulation time 88046682 ps
CPU time 1.69 seconds
Started Nov 22 12:35:58 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 216424 kb
Host smart-da000922-a5ee-419a-be85-b0e0f8673f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109203099443578224554599570870242736862348829861007932034201497146791726222747
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1092030994435782245545995708702427368623488298610079320342014971
46791726222747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.25598642850780997869137492183955130275802052632291885234916394731333569458941
Short name T1147
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 12:35:50 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 216516 kb
Host smart-2519ff62-eb82-4a3b-9a7a-649be60acdb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25598642850780997869137492183955130275802052632291885234916394731333569458941 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.25598642850780997869137492183955130275802052632291885234916394731333569
458941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.108771727809936121032221759190564976975202187438267807364931137862469959831976
Short name T118
Test name
Test status
Simulation time 96832326 ps
CPU time 1.78 seconds
Started Nov 22 12:35:50 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 219972 kb
Host smart-e606735b-b81a-40cc-9bc8-52294d8a2b0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108771727809936121032221759190564976975202187438267807364931137862469
959831976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.1087717278099361210322217591905649769752021874
38267807364931137862469959831976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.23427353190882902429894841489219316329452583211346423264673013865016630468558
Short name T1238
Test name
Test status
Simulation time 193117270 ps
CPU time 2.95 seconds
Started Nov 22 12:35:43 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216488 kb
Host smart-ea88fb12-e943-4bc6-90bf-ce5dfea6cfe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23427353190882902429894841489219316329452583211346423264673013865016630468558 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.23427353190882902429894841489219316329452583211346423264673013865016630468558 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2460163896353595665861793550239651154559882906390490172657502351500353848992
Short name T1203
Test name
Test status
Simulation time 30368572 ps
CPU time 1.39 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 218224 kb
Host smart-1231dc62-1587-4d81-a308-ed5edc0c0c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460163896353595665861793550239651154559882
906390490172657502351500353848992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2460163896353595665861793
550239651154559882906390490172657502351500353848992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.38692216689513165737424735390601072382372672718518029585710997712003966707109
Short name T1123
Test name
Test status
Simulation time 32814981 ps
CPU time 1.03 seconds
Started Nov 22 12:36:00 PM PST 23
Finished Nov 22 12:36:03 PM PST 23
Peak memory 216256 kb
Host smart-074faea9-2beb-4937-a6b4-e2dd8a28ef19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38692216689513165737424735390601072382372672718518029585710997712003966707109 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.38692216689513165737424735390601072382372672718518029585710997712003966707109 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.23517546956305790909031317780358660566757831588683956775446129326053386191503
Short name T1113
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:00 PM PST 23
Peak memory 216272 kb
Host smart-5fdbbf89-780c-4a84-ba68-fcb86a42357b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517546956305790909031317780358660566757831588683956775446129326053386191503 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.23517546956305790909031317780358660566757831588683956775446129326053386191503 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.16715529615209379075402199826226067168062499212359606406472577335980028022143
Short name T1093
Test name
Test status
Simulation time 88046682 ps
CPU time 1.63 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:49 PM PST 23
Peak memory 216416 kb
Host smart-ac4de093-a026-43b7-845e-e2f206860937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715529615209379075402199826226067168062499212359606406472577335980028022143
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.16715529615209379075402199826226067168062499212359606406472577335
980028022143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.57363221249061559427124017454289902951732263024508385927250387984326965505101
Short name T1152
Test name
Test status
Simulation time 38832790 ps
CPU time 1.03 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216540 kb
Host smart-67b73bca-7542-4ef7-9a1b-91192342d6b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57363221249061559427124017454289902951732263024508385927250387984326965505101 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.57363221249061559427124017454289902951732263024508385927250387984326965
505101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.44374354559829170103385671585171377116548832131314642710910951994005842367327
Short name T1144
Test name
Test status
Simulation time 96832326 ps
CPU time 1.81 seconds
Started Nov 22 12:35:53 PM PST 23
Finished Nov 22 12:35:56 PM PST 23
Peak memory 219960 kb
Host smart-7998cf15-8118-4295-beb4-627d54d8d78e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443743545598291701033856715851713771165488321313146427109109519940058
42367327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.44374354559829170103385671585171377116548832131
314642710910951994005842367327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.29611848095005046326534962169913792443036992633632066880243427194571694715948
Short name T1164
Test name
Test status
Simulation time 103242989 ps
CPU time 2.12 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:49 PM PST 23
Peak memory 216560 kb
Host smart-da530a6d-2087-4411-b9e2-70179ee0e674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611848095005046326534962169913792443036992633632066880243427194571694715948 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.29611848095005046326534962169913792443036992633632066880243427194571694715948 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.14436858324443199190742809367972455123135494312399581994132477568291380141707
Short name T7
Test name
Test status
Simulation time 193117270 ps
CPU time 3.05 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 216476 kb
Host smart-02b7583e-8eb9-40b2-9cbf-c4432e70fdec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14436858324443199190742809367972455123135494312399581994132477568291380141707 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.14436858324443199190742809367972455123135494312399581994132477568291380141707 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.6434756016764201034882922649756457338156107244614589036243189746624797697008
Short name T1145
Test name
Test status
Simulation time 30368572 ps
CPU time 1.41 seconds
Started Nov 22 12:36:00 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 219880 kb
Host smart-773bfd5f-4a47-4433-8ed1-27a218666885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6434756016764201034882922649756457338156107
244614589036243189746624797697008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.6434756016764201034882922
649756457338156107244614589036243189746624797697008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.12856710640611548280138707581063458171807648540938605262880559874709304810012
Short name T1185
Test name
Test status
Simulation time 32814981 ps
CPU time 0.98 seconds
Started Nov 22 12:35:55 PM PST 23
Finished Nov 22 12:35:59 PM PST 23
Peak memory 216272 kb
Host smart-4d335f6a-7494-4ede-80ab-102ce831feec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856710640611548280138707581063458171807648540938605262880559874709304810012 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.12856710640611548280138707581063458171807648540938605262880559874709304810012 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.40572953036158773989166838563664429078849081288056582070302855296614842888453
Short name T1184
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 215088 kb
Host smart-976f91cd-0228-4ada-96cc-5a55138dd579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40572953036158773989166838563664429078849081288056582070302855296614842888453 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.40572953036158773989166838563664429078849081288056582070302855296614842888453 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.37289948132748886331049462239250386218273473813541732949683379822941866326016
Short name T1158
Test name
Test status
Simulation time 88046682 ps
CPU time 1.66 seconds
Started Nov 22 12:35:55 PM PST 23
Finished Nov 22 12:35:59 PM PST 23
Peak memory 216416 kb
Host smart-716810fd-e71e-4d4d-bc9d-9177f5ad02be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289948132748886331049462239250386218273473813541732949683379822941866326016
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.37289948132748886331049462239250386218273473813541732949683379822
941866326016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.71333648595451870697986927586838969445905656122824987629656728612817933201407
Short name T1092
Test name
Test status
Simulation time 38832790 ps
CPU time 1.05 seconds
Started Nov 22 12:36:01 PM PST 23
Finished Nov 22 12:36:05 PM PST 23
Peak memory 216636 kb
Host smart-4158b8e4-160b-4911-b60a-a3d08d1792b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71333648595451870697986927586838969445905656122824987629656728612817933201407 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.71333648595451870697986927586838969445905656122824987629656728612817933
201407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.85391350083220136755004677679016150144909285946096436937225992961388731727516
Short name T1212
Test name
Test status
Simulation time 96832326 ps
CPU time 1.89 seconds
Started Nov 22 12:35:47 PM PST 23
Finished Nov 22 12:35:51 PM PST 23
Peak memory 219936 kb
Host smart-6db9edc0-cfa2-449b-9e69-c9344ec8fef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853913500832201367550046776790161501449092859460964369372259929613887
31727516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.85391350083220136755004677679016150144909285946
096436937225992961388731727516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.66990971525229185856942942570592772111266148215903621314798331395999776571056
Short name T6
Test name
Test status
Simulation time 103242989 ps
CPU time 2.23 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 214684 kb
Host smart-6a09d17a-d8ba-46ac-b785-342c5bc16cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66990971525229185856942942570592772111266148215903621314798331395999776571056 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.66990971525229185856942942570592772111266148215903621314798331395999776571056 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.385068524847125105350305306397271459391300916163823605532836076169623399695
Short name T1108
Test name
Test status
Simulation time 193117270 ps
CPU time 3.03 seconds
Started Nov 22 12:35:48 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216460 kb
Host smart-324641e8-20cc-4aaf-acd7-01fb6372adfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385068524847125105350305306397271459391300916163823605532836076169623399695 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.385068524847125105350305306397271459391300916163823605532836076169623399695 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.39102257614390973557954238695534783439090573966266704950450376016966036093400
Short name T1116
Test name
Test status
Simulation time 30368572 ps
CPU time 1.37 seconds
Started Nov 22 12:36:02 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 219948 kb
Host smart-f0d218cd-5f45-40e0-9dfb-1b8d792ecdfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910225761439097355795423869553478343909057
3966266704950450376016966036093400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.391022576143909735579542
38695534783439090573966266704950450376016966036093400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.63111675898600943616213042793878149810557330245465293450184100049031591569717
Short name T1086
Test name
Test status
Simulation time 32814981 ps
CPU time 1 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216272 kb
Host smart-2fb04ed1-b2f0-4a6a-9a26-cb9721eba5f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63111675898600943616213042793878149810557330245465293450184100049031591569717 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.63111675898600943616213042793878149810557330245465293450184100049031591569717 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.84498027293485657692117909597676771221428239757072335522539051246210616718361
Short name T1175
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216268 kb
Host smart-1692646d-95f5-429b-861c-854a762745ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84498027293485657692117909597676771221428239757072335522539051246210616718361 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.84498027293485657692117909597676771221428239757072335522539051246210616718361 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.28232372419518080189199219121897750615014142007502402621728154490637697718255
Short name T1079
Test name
Test status
Simulation time 88046682 ps
CPU time 1.67 seconds
Started Nov 22 12:36:00 PM PST 23
Finished Nov 22 12:36:05 PM PST 23
Peak memory 216392 kb
Host smart-290c77b9-3fce-4118-a082-8290e88d3612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28232372419518080189199219121897750615014142007502402621728154490637697718255
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.28232372419518080189199219121897750615014142007502402621728154490
637697718255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.11571485960351588577285071701038321641579799402217594088531387123990586336101
Short name T1201
Test name
Test status
Simulation time 38832790 ps
CPU time 1.03 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 215400 kb
Host smart-e953ae05-f6dd-410a-9c4d-600ecf490b72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11571485960351588577285071701038321641579799402217594088531387123990586336101 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.11571485960351588577285071701038321641579799402217594088531387123990586
336101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.11794146338056204453610957262156496954432617198069585315293064297621439764205
Short name T1239
Test name
Test status
Simulation time 96832326 ps
CPU time 1.81 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 219948 kb
Host smart-09fb9ffe-7c1e-4dd0-80cd-0334fb800110
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117941463380562044536109572621564969544326171980695853152930642976214
39764205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.11794146338056204453610957262156496954432617198
069585315293064297621439764205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.98216338810574347731819154374553690433045107899805040465540222149001753877777
Short name T1146
Test name
Test status
Simulation time 103242989 ps
CPU time 2.04 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 216600 kb
Host smart-008b42f2-d134-4d92-bebf-f56f01b64cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98216338810574347731819154374553690433045107899805040465540222149001753877777 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.98216338810574347731819154374553690433045107899805040465540222149001753877777 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.76546094142991343529640016301666598525838684513546659469032865226129569264814
Short name T1120
Test name
Test status
Simulation time 193117270 ps
CPU time 2.95 seconds
Started Nov 22 12:35:46 PM PST 23
Finished Nov 22 12:35:51 PM PST 23
Peak memory 216488 kb
Host smart-14a2b60c-3604-4b65-ae76-7b5de87fee73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76546094142991343529640016301666598525838684513546659469032865226129569264814 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.76546094142991343529640016301666598525838684513546659469032865226129569264814 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.109770371100005006118579025266666524106726631195453509790894536260860405458468
Short name T1205
Test name
Test status
Simulation time 30368572 ps
CPU time 1.29 seconds
Started Nov 22 12:35:54 PM PST 23
Finished Nov 22 12:35:57 PM PST 23
Peak memory 219912 kb
Host smart-6b32cad7-4872-4cad-9f3c-1e1129ac37aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097703711000050061185790252666665241067266
31195453509790894536260860405458468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.10977037110000500611857
9025266666524106726631195453509790894536260860405458468 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.65975767189912993609143856505304854639194418097820544846923067837423049649206
Short name T110
Test name
Test status
Simulation time 32814981 ps
CPU time 1.02 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 216208 kb
Host smart-7cca51e0-c59a-4a43-8821-c85fefef4160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65975767189912993609143856505304854639194418097820544846923067837423049649206 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.65975767189912993609143856505304854639194418097820544846923067837423049649206 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.112361926310573435291667546931183419267166900366134563493794065050626707954005
Short name T1115
Test name
Test status
Simulation time 22940060 ps
CPU time 0.82 seconds
Started Nov 22 12:36:00 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 216228 kb
Host smart-cafb21b5-de6c-402c-86c8-2115bec05a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112361926310573435291667546931183419267166900366134563493794065050626707954005 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.112361926310573435291667546931183419267166900366134563493794065050626707954005 +enable_masking=1
+sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.114126658306622401584085227920583951011374503231392745727662867561539674844257
Short name T1221
Test name
Test status
Simulation time 88046682 ps
CPU time 1.69 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 216364 kb
Host smart-19d8152e-17ab-4c10-a589-f0b4b0fa1c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114126658306622401584085227920583951011374503231392745727662867561539674844257
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1141266583066224015840852279205839510113745032313927457276628675
61539674844257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.72773039300894047955463250072137904949707345780026160088487273698618669753272
Short name T1160
Test name
Test status
Simulation time 38832790 ps
CPU time 1.02 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216548 kb
Host smart-4c0dd522-5695-4fa7-bb0c-3b24cbf2ff81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72773039300894047955463250072137904949707345780026160088487273698618669753272 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.72773039300894047955463250072137904949707345780026160088487273698618669
753272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.114503364358156338589186255339955483002158950772104674313625716020904952268061
Short name T105
Test name
Test status
Simulation time 96832326 ps
CPU time 1.85 seconds
Started Nov 22 12:35:55 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 219956 kb
Host smart-23215106-2dae-48f9-ae18-4d7f47e31df2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114503364358156338589186255339955483002158950772104674313625716020904
952268061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.1145033643581563385891862553399554830021589507
72104674313625716020904952268061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.63033842289252704851069599009108603715585976788909967833621230234028691933466
Short name T1226
Test name
Test status
Simulation time 103242989 ps
CPU time 2.11 seconds
Started Nov 22 12:35:58 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 216556 kb
Host smart-469e7a06-43d3-42b0-b4d5-b38a94d87791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63033842289252704851069599009108603715585976788909967833621230234028691933466 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.63033842289252704851069599009108603715585976788909967833621230234028691933466 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.70674164774389970187206565599617776918755807010721738688004447169780159928966
Short name T1196
Test name
Test status
Simulation time 30368572 ps
CPU time 1.36 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 219888 kb
Host smart-018b61d5-8c76-4d71-8e52-70447bf53f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7067416477438997018720656559961777691875580
7010721738688004447169780159928966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.706741647743899701872065
65599617776918755807010721738688004447169780159928966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.23051255949162454200514982316558173721689069106624437147849727880435569295278
Short name T16
Test name
Test status
Simulation time 32814981 ps
CPU time 1.01 seconds
Started Nov 22 12:35:47 PM PST 23
Finished Nov 22 12:35:51 PM PST 23
Peak memory 216268 kb
Host smart-50eac486-11c3-4e4a-9472-2fe3783a04cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051255949162454200514982316558173721689069106624437147849727880435569295278 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.23051255949162454200514982316558173721689069106624437147849727880435569295278 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.83677155034001855308829422018858489379549279999955565156592657650758777686847
Short name T1232
Test name
Test status
Simulation time 22940060 ps
CPU time 0.89 seconds
Started Nov 22 12:35:56 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 214292 kb
Host smart-56966f22-e141-401b-9bf8-40a0f3d82364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83677155034001855308829422018858489379549279999955565156592657650758777686847 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.83677155034001855308829422018858489379549279999955565156592657650758777686847 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.87644980615916086350123069000825863958109602917654769624012050744338559112009
Short name T100
Test name
Test status
Simulation time 88046682 ps
CPU time 1.71 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 216356 kb
Host smart-14782b1e-8ea2-40c9-83a6-1d51dacf07e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87644980615916086350123069000825863958109602917654769624012050744338559112009
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.87644980615916086350123069000825863958109602917654769624012050744
338559112009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.6076460074000971112027502490025916020304175130432557167122689446976233139934
Short name T1156
Test name
Test status
Simulation time 38832790 ps
CPU time 1.09 seconds
Started Nov 22 12:36:11 PM PST 23
Finished Nov 22 12:36:14 PM PST 23
Peak memory 215784 kb
Host smart-5c59f73a-a3f6-40d1-826a-073fd852f398
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6076460074000971112027502490025916020304175130432557167122689446976233139934 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.607646007400097111202750249002591602030417513043255716712268944697623313
9934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.57402379745078910170474492397329093384609494090531562433303761379794111065533
Short name T1227
Test name
Test status
Simulation time 96832326 ps
CPU time 1.79 seconds
Started Nov 22 12:35:57 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 219924 kb
Host smart-19f865ff-45f5-40ce-b400-144f01adfeae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574023797450789101704744923973290933846094940905315624333037613797941
11065533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.57402379745078910170474492397329093384609494090
531562433303761379794111065533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.108700780199930452327192222029728614567734928359298976771252282608351725729759
Short name T91
Test name
Test status
Simulation time 103242989 ps
CPU time 2.02 seconds
Started Nov 22 12:35:53 PM PST 23
Finished Nov 22 12:35:56 PM PST 23
Peak memory 216556 kb
Host smart-14427faf-1009-4f32-9b67-25e38e7fc9c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108700780199930452327192222029728614567734928359298976771252282608351725729759 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.108700780199930452327192222029728614567734928359298976771252282608351725729759 +enable_masking=1
+sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.35136628543914152208262835103891682572652387021739515196482058821283894325256
Short name T1200
Test name
Test status
Simulation time 193117270 ps
CPU time 3.14 seconds
Started Nov 22 12:35:55 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 216456 kb
Host smart-508a1e1e-dce3-4c48-b1cb-bcdb141a4973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136628543914152208262835103891682572652387021739515196482058821283894325256 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.35136628543914152208262835103891682572652387021739515196482058821283894325256 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.115622029905650839033400316099681164989649354229088356138799472997724677722745
Short name T1181
Test name
Test status
Simulation time 30368572 ps
CPU time 1.25 seconds
Started Nov 22 12:36:09 PM PST 23
Finished Nov 22 12:36:11 PM PST 23
Peak memory 219816 kb
Host smart-3a392f5d-8f9c-4bfb-a44a-5bc2d7de16cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156220299056508390334003160996811649896493
54229088356138799472997724677722745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.11562202990565083903340
0316099681164989649354229088356138799472997724677722745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.40739350351516934854256587606100688883228600274585260757701723848197728360527
Short name T1078
Test name
Test status
Simulation time 32814981 ps
CPU time 0.95 seconds
Started Nov 22 12:36:03 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 216276 kb
Host smart-062689d7-8e7d-4e2d-8397-ee67c0bd3abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40739350351516934854256587606100688883228600274585260757701723848197728360527 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.40739350351516934854256587606100688883228600274585260757701723848197728360527 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.62323082027859977090872477872655719717769664780301300806142050344797935001996
Short name T1192
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:35:58 PM PST 23
Finished Nov 22 12:36:01 PM PST 23
Peak memory 216192 kb
Host smart-0090c029-5ba0-4cc5-b633-38e161cca809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62323082027859977090872477872655719717769664780301300806142050344797935001996 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.62323082027859977090872477872655719717769664780301300806142050344797935001996 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.67782744627428904150676306506854396486320207499054699401058745780315858848668
Short name T18
Test name
Test status
Simulation time 88046682 ps
CPU time 1.69 seconds
Started Nov 22 12:36:14 PM PST 23
Finished Nov 22 12:36:16 PM PST 23
Peak memory 216412 kb
Host smart-34291719-1362-435e-aa9e-8b9d556fd29f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67782744627428904150676306506854396486320207499054699401058745780315858848668
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.67782744627428904150676306506854396486320207499054699401058745780
315858848668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.100424137708196621501702866705477294533507999724407206838926956329847519971594
Short name T1157
Test name
Test status
Simulation time 38832790 ps
CPU time 1.03 seconds
Started Nov 22 12:35:54 PM PST 23
Finished Nov 22 12:35:56 PM PST 23
Peak memory 216512 kb
Host smart-23dd80d4-8a7b-464c-92c0-570de99405ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100424137708196621501702866705477294533507999724407206838926956329847519971594 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.1004241377081966215017028667054772945335079997244072068389269563298475
19971594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.73601360855568274457031916409814121221948617045778496835502851632517073278681
Short name T1081
Test name
Test status
Simulation time 96832326 ps
CPU time 1.88 seconds
Started Nov 22 12:35:58 PM PST 23
Finished Nov 22 12:36:02 PM PST 23
Peak memory 219984 kb
Host smart-656dbd93-4635-4875-8119-3a1e0815cd54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736013608555682744570319164098141212219486170457784968355028516325170
73278681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.73601360855568274457031916409814121221948617045
778496835502851632517073278681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.106819493751275601131110602903876165902825697850832526634642140350775809466804
Short name T4
Test name
Test status
Simulation time 103242989 ps
CPU time 2.14 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:55 PM PST 23
Peak memory 216564 kb
Host smart-88dc97af-5b5f-4d1f-84c1-829ef63048ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106819493751275601131110602903876165902825697850832526634642140350775809466804 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.106819493751275601131110602903876165902825697850832526634642140350775809466804 +enable_masking=1
+sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.38704430205905332229451996355456742453511223800118814920553198996627548745046
Short name T1188
Test name
Test status
Simulation time 193117270 ps
CPU time 3.06 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:56 PM PST 23
Peak memory 216476 kb
Host smart-d89519d6-a842-4d32-8b73-27ed89e73c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38704430205905332229451996355456742453511223800118814920553198996627548745046 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.38704430205905332229451996355456742453511223800118814920553198996627548745046 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.81559427994451144031749245305046256757848743581990221138110371340028285992247
Short name T1217
Test name
Test status
Simulation time 30368572 ps
CPU time 1.29 seconds
Started Nov 22 12:36:06 PM PST 23
Finished Nov 22 12:36:08 PM PST 23
Peak memory 219996 kb
Host smart-e2fef77b-681e-4591-89ad-ce2b6fe69c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8155942799445114403174924530504625675784874
3581990221138110371340028285992247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.815594279944511440317492
45305046256757848743581990221138110371340028285992247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.113555116682268598823867454978296848749472713756173722240377191132541766554168
Short name T1117
Test name
Test status
Simulation time 32814981 ps
CPU time 0.99 seconds
Started Nov 22 12:36:05 PM PST 23
Finished Nov 22 12:36:07 PM PST 23
Peak memory 216308 kb
Host smart-e1ee562a-a381-48ea-81e5-a386a9ebff6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113555116682268598823867454978296848749472713756173722240377191132541766554168 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.113555116682268598823867454978296848749472713756173722240377191132541766554168 +enable_masking=1
+sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.60359222167732767872138775443686221141162179168500128792890552521438093374470
Short name T1159
Test name
Test status
Simulation time 22940060 ps
CPU time 0.87 seconds
Started Nov 22 12:36:07 PM PST 23
Finished Nov 22 12:36:09 PM PST 23
Peak memory 216268 kb
Host smart-7e351938-7385-431b-90c7-cf7d134853c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60359222167732767872138775443686221141162179168500128792890552521438093374470 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.60359222167732767872138775443686221141162179168500128792890552521438093374470 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.32473041462813673667721257357217481785731737961038386639462481447578717752588
Short name T1209
Test name
Test status
Simulation time 88046682 ps
CPU time 1.64 seconds
Started Nov 22 12:36:10 PM PST 23
Finished Nov 22 12:36:12 PM PST 23
Peak memory 216452 kb
Host smart-5400a57a-ce1e-48c5-a6e7-ab6e6000e42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473041462813673667721257357217481785731737961038386639462481447578717752588
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.32473041462813673667721257357217481785731737961038386639462481447
578717752588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.46681969762644982594281859256456762534895602626949011963896226947602303673311
Short name T115
Test name
Test status
Simulation time 38832790 ps
CPU time 1 seconds
Started Nov 22 12:36:16 PM PST 23
Finished Nov 22 12:36:18 PM PST 23
Peak memory 216472 kb
Host smart-c627959a-b91d-4578-b9fa-14d4c8123e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46681969762644982594281859256456762534895602626949011963896226947602303673311 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.46681969762644982594281859256456762534895602626949011963896226947602303
673311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.92608343473037555507719438139714992177826939606574902383061837103753504872002
Short name T1176
Test name
Test status
Simulation time 96832326 ps
CPU time 1.81 seconds
Started Nov 22 12:36:09 PM PST 23
Finished Nov 22 12:36:12 PM PST 23
Peak memory 219908 kb
Host smart-2a5e73ad-4b2b-4731-b666-f1a8b2fdaff1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926083434730375555077194381397149921778269396065749023830618371037535
04872002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.92608343473037555507719438139714992177826939606
574902383061837103753504872002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.31895342970737043583573090016667130583157038736139465586455389277267072303551
Short name T1
Test name
Test status
Simulation time 103242989 ps
CPU time 2.1 seconds
Started Nov 22 12:36:16 PM PST 23
Finished Nov 22 12:36:19 PM PST 23
Peak memory 216476 kb
Host smart-d206c6a4-2599-4979-a8d3-f001033f63b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31895342970737043583573090016667130583157038736139465586455389277267072303551 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.31895342970737043583573090016667130583157038736139465586455389277267072303551 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.84856397804777485531617342009177037981926411194006390651485788910048726518159
Short name T9
Test name
Test status
Simulation time 193117270 ps
CPU time 3.12 seconds
Started Nov 22 12:36:03 PM PST 23
Finished Nov 22 12:36:08 PM PST 23
Peak memory 216452 kb
Host smart-9ef1a7ca-66a3-4f14-b460-eedbee1a82b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84856397804777485531617342009177037981926411194006390651485788910048726518159 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.84856397804777485531617342009177037981926411194006390651485788910048726518159 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.68060955151082394458766660984845767764414627293263460331511020129419094615465
Short name T1168
Test name
Test status
Simulation time 30368572 ps
CPU time 1.3 seconds
Started Nov 22 12:36:09 PM PST 23
Finished Nov 22 12:36:11 PM PST 23
Peak memory 219852 kb
Host smart-b0eeae26-38c2-4cc7-a40a-ac0afd040207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6806095515108239445876666098484576776441462
7293263460331511020129419094615465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.680609551510823944587666
60984845767764414627293263460331511020129419094615465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4907794404243727106638960996034923924326903333158025834602046189882109658973
Short name T1149
Test name
Test status
Simulation time 32814981 ps
CPU time 0.98 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:10 PM PST 23
Peak memory 216248 kb
Host smart-cc059f67-3840-4d8e-a63e-59575b9231da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4907794404243727106638960996034923924326903333158025834602046189882109658973 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4907794404243727106638960996034923924326903333158025834602046189882109658973 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.89623119058319672327066196408024114959706724977860530675726111668074576805346
Short name T1223
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:36:04 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 216268 kb
Host smart-c5a98577-582a-404c-bd2c-d07f75846308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89623119058319672327066196408024114959706724977860530675726111668074576805346 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.89623119058319672327066196408024114959706724977860530675726111668074576805346 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.97865089869533143876751368907352836787319985420962583484108347742879962121408
Short name T1137
Test name
Test status
Simulation time 88046682 ps
CPU time 1.63 seconds
Started Nov 22 12:36:02 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 216444 kb
Host smart-25773d79-65cd-4975-b336-91a797d327e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97865089869533143876751368907352836787319985420962583484108347742879962121408
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.97865089869533143876751368907352836787319985420962583484108347742
879962121408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.88316657271889017182786359306514135314160192064176584409891025625119403488770
Short name T1229
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 12:36:05 PM PST 23
Finished Nov 22 12:36:07 PM PST 23
Peak memory 216552 kb
Host smart-1fbbe6c9-85c4-4a3b-86c1-fcaee6ed077f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88316657271889017182786359306514135314160192064176584409891025625119403488770 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.88316657271889017182786359306514135314160192064176584409891025625119403
488770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.111133577686643614570057501277965502233086297426474812806034459130942060936024
Short name T1202
Test name
Test status
Simulation time 96832326 ps
CPU time 1.86 seconds
Started Nov 22 12:36:10 PM PST 23
Finished Nov 22 12:36:13 PM PST 23
Peak memory 219960 kb
Host smart-664ce9fd-313f-4038-a36f-0b3f1c4b9936
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111133577686643614570057501277965502233086297426474812806034459130942
060936024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.1111335776866436145700575012779655022330862974
26474812806034459130942060936024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.46235840863368658378935651889481210022795315934139320893980524660716751019089
Short name T10
Test name
Test status
Simulation time 103242989 ps
CPU time 1.99 seconds
Started Nov 22 12:36:12 PM PST 23
Finished Nov 22 12:36:15 PM PST 23
Peak memory 216524 kb
Host smart-66315fec-e912-4edf-a2b3-96ebb237c425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46235840863368658378935651889481210022795315934139320893980524660716751019089 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.46235840863368658378935651889481210022795315934139320893980524660716751019089 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.20737610198484074443063050025992391778297036438645243971996180929673869028925
Short name T1131
Test name
Test status
Simulation time 193117270 ps
CPU time 3 seconds
Started Nov 22 12:36:03 PM PST 23
Finished Nov 22 12:36:08 PM PST 23
Peak memory 216536 kb
Host smart-1ee57ff7-ddf2-4b0a-85b3-e39811ec5a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737610198484074443063050025992391778297036438645243971996180929673869028925 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.20737610198484074443063050025992391778297036438645243971996180929673869028925 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.93355486951508716668665863985298795865421826955772898302135997467363860405725
Short name T1087
Test name
Test status
Simulation time 403472730 ps
CPU time 6 seconds
Started Nov 22 12:35:42 PM PST 23
Finished Nov 22 12:35:49 PM PST 23
Peak memory 216512 kb
Host smart-e154402a-2713-44d8-a4b7-c6d905745687
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93355486951508716668665863985298795865421826955772898302135997467363860405725 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.93355486951508716668665863985298795865421826955772898302135997467363860405725 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2575247636172391513641950944793352950152337545443071744803616562797144646907
Short name T1139
Test name
Test status
Simulation time 934950621 ps
CPU time 10.95 seconds
Started Nov 22 12:35:30 PM PST 23
Finished Nov 22 12:35:46 PM PST 23
Peak memory 216504 kb
Host smart-c34615d5-7160-404e-93f0-b592e85b6886
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575247636172391513641950944793352950152337545443071744803616562797144646907 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2575247636172391513641950944793352950152337545443071744803616562797144646907 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.84671451138205829409828767022232492782297142081999610886021483257155526268143
Short name T1172
Test name
Test status
Simulation time 29368580 ps
CPU time 1.11 seconds
Started Nov 22 12:35:48 PM PST 23
Finished Nov 22 12:35:52 PM PST 23
Peak memory 216232 kb
Host smart-43e6ecfb-2100-4c69-a968-25b163e12adb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84671451138205829409828767022232492782297142081999610886021483257155526268143 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.84671451138205829409828767022232492782297142081999610886021483257155526268143 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.22448053144621507542568985897483980281183206146475392254617089637844182807425
Short name T1141
Test name
Test status
Simulation time 30368572 ps
CPU time 1.28 seconds
Started Nov 22 12:35:29 PM PST 23
Finished Nov 22 12:35:33 PM PST 23
Peak memory 219928 kb
Host smart-dcb44621-d14f-402c-a5cf-3e05ea9c4af6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244805314462150754256898589748398028118320
6146475392254617089637844182807425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2244805314462150754256898
5897483980281183206146475392254617089637844182807425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.109653702811625536802517802115795549577684621297666163226082005338259215650425
Short name T1204
Test name
Test status
Simulation time 32814981 ps
CPU time 1.02 seconds
Started Nov 22 12:35:22 PM PST 23
Finished Nov 22 12:35:24 PM PST 23
Peak memory 216260 kb
Host smart-2f1c08b2-5b70-49e6-98ef-0d9361a25182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109653702811625536802517802115795549577684621297666163226082005338259215650425 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.109653702811625536802517802115795549577684621297666163226082005338259215650425 +enable_masking=1
+sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.7684836185249954964557738980839860875553790534698180081925935669818140116289
Short name T1130
Test name
Test status
Simulation time 22940060 ps
CPU time 0.81 seconds
Started Nov 22 12:35:34 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216252 kb
Host smart-49313f85-ee84-4ea8-be8f-8922a76e8f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7684836185249954964557738980839860875553790534698180081925935669818140116289 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.kmac_intr_test.7684836185249954964557738980839860875553790534698180081925935669818140116289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.26433548090091069902627437282423605410853203276347343018768647904440370836537
Short name T98
Test name
Test status
Simulation time 46939868 ps
CPU time 1.23 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:23 PM PST 23
Peak memory 216384 kb
Host smart-2e566135-cfa5-4eff-ab70-29b05b566a98
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433548090091069902627437282423605410853203276347343018768647904440370836537 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2643354809009106990262743728242360541085320327634734301876864790444037
0836537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1015645355569717508040604908895507219712204434498340669387661821674603880614
Short name T1162
Test name
Test status
Simulation time 16922251 ps
CPU time 0.75 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:23 PM PST 23
Peak memory 216176 kb
Host smart-8a971a34-00e5-4dcc-a46f-a68fdf63ac84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015645355569717508040604908895507219712204434498340669387661821674603880614 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1015645355569717508040604908895507219712204434498340669387661821674603880614 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.37410692360708953162926763328792564451774378644534250933104126184214385673009
Short name T1198
Test name
Test status
Simulation time 88046682 ps
CPU time 1.71 seconds
Started Nov 22 12:35:31 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216472 kb
Host smart-f95571bd-9717-47a7-bf35-9e4fd223cc68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37410692360708953162926763328792564451774378644534250933104126184214385673009
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.374106923607089531629267633287925644517743786445342509331041261842
14385673009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.65158252835588240722609973521160390638352988795447080999711641942915310734455
Short name T1133
Test name
Test status
Simulation time 38832790 ps
CPU time 1 seconds
Started Nov 22 12:35:19 PM PST 23
Finished Nov 22 12:35:22 PM PST 23
Peak memory 216484 kb
Host smart-6ee998f1-bfab-4421-a318-205f4198a750
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65158252835588240722609973521160390638352988795447080999711641942915310734455 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.651582528355882407226099735211603906383529887954470809997116419429153107
34455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.69615596488814182892972365625726758319441392657194153065432129734534222867182
Short name T1234
Test name
Test status
Simulation time 96832326 ps
CPU time 1.79 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 219976 kb
Host smart-cfed894d-fe8b-4712-800a-7ee0dc35b729
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696155964888141828929723656257267583194413926571941530654321297345342
22867182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.696155964888141828929723656257267583194413926571
94153065432129734534222867182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.98671430712322442729074640722523957891165705199604136444536814488835556647008
Short name T94
Test name
Test status
Simulation time 103242989 ps
CPU time 2.15 seconds
Started Nov 22 12:35:21 PM PST 23
Finished Nov 22 12:35:25 PM PST 23
Peak memory 216636 kb
Host smart-289d978e-920b-4f1f-aeff-ef95f43ab9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98671430712322442729074640722523957891165705199604136444536814488835556647008 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.98671430712322442729074640722523957891165705199604136444536814488835556647008 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.28822257408153204955153501530154084022867125047551308220061958045525446512006
Short name T8
Test name
Test status
Simulation time 193117270 ps
CPU time 3.03 seconds
Started Nov 22 12:35:18 PM PST 23
Finished Nov 22 12:35:23 PM PST 23
Peak memory 216436 kb
Host smart-5abee31c-9f7b-4206-bdc2-f0197e89ce64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28822257408153204955153501530154084022867125047551308220061958045525446512006 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.28822257408153204955153501530154084022867125047551308220061958045525446512006 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.93152063837508361700990652821676709937038532858637952310975739667810438333952
Short name T1099
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:36:16 PM PST 23
Finished Nov 22 12:36:17 PM PST 23
Peak memory 216148 kb
Host smart-bed51e2f-7bf0-4673-a6d0-e2b1964e8b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93152063837508361700990652821676709937038532858637952310975739667810438333952 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.93152063837508361700990652821676709937038532858637952310975739667810438333952 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.13128602608581636499942328187768839778395721086266339236319164275174810217034
Short name T113
Test name
Test status
Simulation time 22940060 ps
CPU time 0.81 seconds
Started Nov 22 12:36:12 PM PST 23
Finished Nov 22 12:36:14 PM PST 23
Peak memory 216196 kb
Host smart-c0068cb0-f9d0-4bd2-b8a4-c494412c9277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128602608581636499942328187768839778395721086266339236319164275174810217034 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.13128602608581636499942328187768839778395721086266339236319164275174810217034 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.114469326964369343513319559147603217458102123348122472680526188861176022409402
Short name T1240
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:10 PM PST 23
Peak memory 216224 kb
Host smart-dbac70ab-6403-407e-9d70-80c3a0dc6fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114469326964369343513319559147603217458102123348122472680526188861176022409402 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.114469326964369343513319559147603217458102123348122472680526188861176022409402 +enable_masking=1
+sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.1954697805367638033590485941445064811066749610072700626667772837690479323401
Short name T1191
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:36:03 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 216228 kb
Host smart-609a458b-266c-4b64-a7e1-e64d94ef94a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954697805367638033590485941445064811066749610072700626667772837690479323401 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 23.kmac_intr_test.1954697805367638033590485941445064811066749610072700626667772837690479323401 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2465324130457616379238754871840688193816803629560183566987408862948268550883
Short name T1080
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:36:18 PM PST 23
Finished Nov 22 12:36:21 PM PST 23
Peak memory 216368 kb
Host smart-49a55522-e3f8-4007-b271-f1050728344c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465324130457616379238754871840688193816803629560183566987408862948268550883 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 24.kmac_intr_test.2465324130457616379238754871840688193816803629560183566987408862948268550883 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.95057650661593772705995205062910356210517234794411165211785207454454243699493
Short name T120
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:31 PM PST 23
Peak memory 216268 kb
Host smart-37f9bc49-d603-4009-bd22-98208d001b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95057650661593772705995205062910356210517234794411165211785207454454243699493 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.95057650661593772705995205062910356210517234794411165211785207454454243699493 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.84163835384272598449542752629079835849714142374986392205034281367224642491504
Short name T1225
Test name
Test status
Simulation time 22940060 ps
CPU time 0.82 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:24 PM PST 23
Peak memory 216268 kb
Host smart-911f5579-e525-49ec-998b-37a146fd2ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84163835384272598449542752629079835849714142374986392205034281367224642491504 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.84163835384272598449542752629079835849714142374986392205034281367224642491504 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.60875142387805809190226855468505600371899102653600409949229597020347586674831
Short name T1118
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:30 PM PST 23
Peak memory 216340 kb
Host smart-4f214c6a-4e6b-4c10-8769-5340d6d4b9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60875142387805809190226855468505600371899102653600409949229597020347586674831 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.60875142387805809190226855468505600371899102653600409949229597020347586674831 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.25671044316697317973831941165184476669422756002630336946381121172884987220722
Short name T1111
Test name
Test status
Simulation time 22940060 ps
CPU time 0.81 seconds
Started Nov 22 12:36:19 PM PST 23
Finished Nov 22 12:36:21 PM PST 23
Peak memory 216264 kb
Host smart-4f8b496f-d87b-4070-a162-2b97bd14ffdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671044316697317973831941165184476669422756002630336946381121172884987220722 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.25671044316697317973831941165184476669422756002630336946381121172884987220722 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.34781456574506410574940807245055291939355938838935932736403556068215824519701
Short name T11
Test name
Test status
Simulation time 22940060 ps
CPU time 0.81 seconds
Started Nov 22 12:36:16 PM PST 23
Finished Nov 22 12:36:18 PM PST 23
Peak memory 216320 kb
Host smart-c48f4e45-57e7-427f-9de6-45133d442b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34781456574506410574940807245055291939355938838935932736403556068215824519701 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.34781456574506410574940807245055291939355938838935932736403556068215824519701 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.17205672083795963599578483166465282954266426725540163757367345536924151248576
Short name T19
Test name
Test status
Simulation time 403472730 ps
CPU time 5.98 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216496 kb
Host smart-c6d6008e-093a-43b7-8699-287544be8ace
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205672083795963599578483166465282954266426725540163757367345536924151248576 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.17205672083795963599578483166465282954266426725540163757367345536924151248576 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.30336896691159536253145040558105943488880408187012161748688440788126819965190
Short name T1216
Test name
Test status
Simulation time 934950621 ps
CPU time 11.8 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:58 PM PST 23
Peak memory 216552 kb
Host smart-184859dd-8fd7-4358-b551-f0e39e9ca821
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30336896691159536253145040558105943488880408187012161748688440788126819965190 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.30336896691159536253145040558105943488880408187012161748688440788126819965190 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.9513049646966503500290165139931131162501286679657589187247493165753479378131
Short name T1132
Test name
Test status
Simulation time 29368580 ps
CPU time 0.95 seconds
Started Nov 22 12:35:30 PM PST 23
Finished Nov 22 12:35:35 PM PST 23
Peak memory 216240 kb
Host smart-4311fe70-7837-4e94-b4b7-987259e4545c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9513049646966503500290165139931131162501286679657589187247493165753479378131 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.9513049646966503500290165139931131162501286679657589187247493165753479378131 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.22720864490989946177368709139390954432292374423834794237930344333764565903897
Short name T1084
Test name
Test status
Simulation time 30368572 ps
CPU time 1.29 seconds
Started Nov 22 12:35:35 PM PST 23
Finished Nov 22 12:35:38 PM PST 23
Peak memory 219948 kb
Host smart-24a167f8-6b8f-4bb6-aeba-131a6ae5c768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272086449098994617736870913939095443229237
4423834794237930344333764565903897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2272086449098994617736870
9139390954432292374423834794237930344333764565903897 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.54432085209513643741970051459632380381170632021451099651998826076643608265847
Short name T1100
Test name
Test status
Simulation time 32814981 ps
CPU time 1.03 seconds
Started Nov 22 12:35:31 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216272 kb
Host smart-dda80406-3072-4b4f-baf3-408d3e5821e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54432085209513643741970051459632380381170632021451099651998826076643608265847 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.54432085209513643741970051459632380381170632021451099651998826076643608265847 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.16526406473540551125923101213500241771027913651274217788403247712446986141260
Short name T119
Test name
Test status
Simulation time 22940060 ps
CPU time 0.86 seconds
Started Nov 22 12:35:26 PM PST 23
Finished Nov 22 12:35:28 PM PST 23
Peak memory 216272 kb
Host smart-8b804d7d-a0aa-4b35-990f-53f7cedfe4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16526406473540551125923101213500241771027913651274217788403247712446986141260 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.16526406473540551125923101213500241771027913651274217788403247712446986141260 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.22597260635212838661679430474041326334753656512580133070580548444178805819570
Short name T97
Test name
Test status
Simulation time 46939868 ps
CPU time 1.26 seconds
Started Nov 22 12:35:24 PM PST 23
Finished Nov 22 12:35:26 PM PST 23
Peak memory 216388 kb
Host smart-c127368e-32d1-4781-b5e1-99eb2ee6e52e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597260635212838661679430474041326334753656512580133070580548444178805819570 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.2259726063521283866167943047404132633475365651258013307058054844417880
5819570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.70830863530655750882540077187113323625201974932894935622605620886652950307942
Short name T1090
Test name
Test status
Simulation time 16922251 ps
CPU time 0.76 seconds
Started Nov 22 12:35:27 PM PST 23
Finished Nov 22 12:35:28 PM PST 23
Peak memory 216212 kb
Host smart-6999121e-ca4b-4363-8942-00febb9423ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70830863530655750882540077187113323625201974932894935622605620886652950307942 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.70830863530655750882540077187113323625201974932894935622605620886652950307942 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.88246809063607131597711104555182294798641144890840313882459837888553385247696
Short name T1096
Test name
Test status
Simulation time 88046682 ps
CPU time 1.72 seconds
Started Nov 22 12:35:20 PM PST 23
Finished Nov 22 12:35:23 PM PST 23
Peak memory 216436 kb
Host smart-fd5cee7e-826b-4896-ab3a-93be78003fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88246809063607131597711104555182294798641144890840313882459837888553385247696
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.882468090636071315977111045551822947986411448908403138824598378885
53385247696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.42216894137265402290318509664102061732158677355476354330008748607660518609341
Short name T1121
Test name
Test status
Simulation time 38832790 ps
CPU time 1.01 seconds
Started Nov 22 12:35:24 PM PST 23
Finished Nov 22 12:35:25 PM PST 23
Peak memory 216548 kb
Host smart-e0d618ac-626d-4f42-9b16-4e0158aa00bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216894137265402290318509664102061732158677355476354330008748607660518609341 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.422168941372654022903185096641020617321586773554763543300087486076605186
09341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.10695789199554132931823968034113169036334902836070252049769489740510309297088
Short name T1186
Test name
Test status
Simulation time 96832326 ps
CPU time 1.73 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:55 PM PST 23
Peak memory 219948 kb
Host smart-185f1a22-957e-46d2-8293-626e80475968
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106957891995541329318239680341131690363349028360702520497694897405103
09297088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.106957891995541329318239680341131690363349028360
70252049769489740510309297088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.28628036672657950115152458257255679389488531063578756924825159881770115897473
Short name T1180
Test name
Test status
Simulation time 103242989 ps
CPU time 2.1 seconds
Started Nov 22 12:35:50 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 216620 kb
Host smart-54020cd3-947e-461f-9462-f4eb862ddbee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28628036672657950115152458257255679389488531063578756924825159881770115897473 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.28628036672657950115152458257255679389488531063578756924825159881770115897473 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.77209444563764348536294137041274514647119645554077256998865491936121613044748
Short name T1208
Test name
Test status
Simulation time 193117270 ps
CPU time 3.11 seconds
Started Nov 22 12:35:27 PM PST 23
Finished Nov 22 12:35:31 PM PST 23
Peak memory 216488 kb
Host smart-2aea9bcf-54f1-412d-96e2-22e0d6b53734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77209444563764348536294137041274514647119645554077256998865491936121613044748 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.77209444563764348536294137041274514647119645554077256998865491936121613044748 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.70227154160185353676397615194546882039642273960839584609819343103395328997673
Short name T1142
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:36:27 PM PST 23
Peak memory 216252 kb
Host smart-78a3b3d1-8317-428f-983f-dc587c98488b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70227154160185353676397615194546882039642273960839584609819343103395328997673 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.70227154160185353676397615194546882039642273960839584609819343103395328997673 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.39982911572956128871782899984270489312349438405254283434048539825679921731868
Short name T1083
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:36:18 PM PST 23
Finished Nov 22 12:36:20 PM PST 23
Peak memory 216132 kb
Host smart-94372629-c3a6-4e3f-9447-9c591e86f7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39982911572956128871782899984270489312349438405254283434048539825679921731868 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.39982911572956128871782899984270489312349438405254283434048539825679921731868 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.110431962046427735073815854228237124076611765653944294101729511915620789790450
Short name T1190
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:36:27 PM PST 23
Peak memory 216288 kb
Host smart-e4e15266-0257-4557-b7f1-be1ebc4aa7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110431962046427735073815854228237124076611765653944294101729511915620789790450 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.110431962046427735073815854228237124076611765653944294101729511915620789790450 +enable_masking=1
+sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.7768690764260843360940697216051285779532032588528301639653557297411010877760
Short name T1150
Test name
Test status
Simulation time 22940060 ps
CPU time 0.88 seconds
Started Nov 22 12:36:23 PM PST 23
Finished Nov 22 12:36:25 PM PST 23
Peak memory 216228 kb
Host smart-71a58535-df00-44eb-a901-add562810513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7768690764260843360940697216051285779532032588528301639653557297411010877760 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 34.kmac_intr_test.7768690764260843360940697216051285779532032588528301639653557297411010877760 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.105999159715522700253833087881089333359256187832684183545820541249669581863488
Short name T1189
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:36:26 PM PST 23
Peak memory 216264 kb
Host smart-83c801c2-4166-4547-bb8b-b862274048fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105999159715522700253833087881089333359256187832684183545820541249669581863488 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.105999159715522700253833087881089333359256187832684183545820541249669581863488 +enable_masking=1
+sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.19144963162824094354760633453822698343894746055483761615642357012855285610285
Short name T1222
Test name
Test status
Simulation time 22940060 ps
CPU time 0.76 seconds
Started Nov 22 12:37:06 PM PST 23
Finished Nov 22 12:37:08 PM PST 23
Peak memory 216324 kb
Host smart-8e6924db-c7d5-4b42-a51f-7c3127f9627f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144963162824094354760633453822698343894746055483761615642357012855285610285 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.19144963162824094354760633453822698343894746055483761615642357012855285610285 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.98680411426651491934467056832001021304602518895213823538091042339635515840175
Short name T1183
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:36:22 PM PST 23
Finished Nov 22 12:36:24 PM PST 23
Peak memory 216268 kb
Host smart-c049fd66-c228-426b-8d55-81918b07bee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98680411426651491934467056832001021304602518895213823538091042339635515840175 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.98680411426651491934467056832001021304602518895213823538091042339635515840175 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.71645451352818713381821385709841679697780505412015514292722454464920108114205
Short name T1166
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:23 PM PST 23
Peak memory 216264 kb
Host smart-3adf35a6-5a70-42f6-911b-05fca6c37d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71645451352818713381821385709841679697780505412015514292722454464920108114205 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.71645451352818713381821385709841679697780505412015514292722454464920108114205 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.104628357603652408456221340462763438137454879244372097864816472016808208291035
Short name T1199
Test name
Test status
Simulation time 22940060 ps
CPU time 0.83 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:30 PM PST 23
Peak memory 216264 kb
Host smart-dfbd0d52-5be7-4702-9ec6-0dd09e8ddf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104628357603652408456221340462763438137454879244372097864816472016808208291035 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.104628357603652408456221340462763438137454879244372097864816472016808208291035 +enable_masking=1
+sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.40771404646091614701599602408559034905282936820221647400972734752715070039964
Short name T1085
Test name
Test status
Simulation time 403472730 ps
CPU time 5.82 seconds
Started Nov 22 12:35:42 PM PST 23
Finished Nov 22 12:35:50 PM PST 23
Peak memory 216536 kb
Host smart-ec463e19-c8a5-4bd1-99de-5ae58e353266
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40771404646091614701599602408559034905282936820221647400972734752715070039964 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.40771404646091614701599602408559034905282936820221647400972734752715070039964 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.102224403945236619780718911364287234042770914335976579808195602234440666456872
Short name T1206
Test name
Test status
Simulation time 934950621 ps
CPU time 10.79 seconds
Started Nov 22 12:35:26 PM PST 23
Finished Nov 22 12:35:38 PM PST 23
Peak memory 216568 kb
Host smart-b71e8d92-d194-4838-9cfb-843f80a7b0ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102224403945236619780718911364287234042770914335976579808195602234440666456872 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.102224403945236619780718911364287234042770914335976579808195602234440666456872 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.76264958307513434135655280394795098410718444037852720742309618222431001628751
Short name T1182
Test name
Test status
Simulation time 29368580 ps
CPU time 0.99 seconds
Started Nov 22 12:35:35 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216236 kb
Host smart-b3052a06-8d7d-4707-9365-6cc6af7126e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76264958307513434135655280394795098410718444037852720742309618222431001628751 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.76264958307513434135655280394795098410718444037852720742309618222431001628751 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.100662468108680518250141840109647542389412900714509536242949167618719422754565
Short name T1169
Test name
Test status
Simulation time 30368572 ps
CPU time 1.34 seconds
Started Nov 22 12:35:51 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 219972 kb
Host smart-00648ce3-8ead-443b-9499-c07ab000205b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006624681086805182501418401096475423894129
00714509536242949167618719422754565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.100662468108680518250141
840109647542389412900714509536242949167618719422754565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.106735545254583406430007300171109485517747613403722632714038200661830482839892
Short name T1135
Test name
Test status
Simulation time 32814981 ps
CPU time 0.95 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:42 PM PST 23
Peak memory 216248 kb
Host smart-92caf999-d12f-42d6-81f5-efb2d4d695dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106735545254583406430007300171109485517747613403722632714038200661830482839892 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.106735545254583406430007300171109485517747613403722632714038200661830482839892 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.64636733405477696670305518557387879714253307091799003321280152568639140317189
Short name T1167
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:35:32 PM PST 23
Finished Nov 22 12:35:36 PM PST 23
Peak memory 216260 kb
Host smart-7e434bb5-d1fd-42e7-84c4-6b43a7664b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64636733405477696670305518557387879714253307091799003321280152568639140317189 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.64636733405477696670305518557387879714253307091799003321280152568639140317189 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.79223228074306128699415414275018969308659897032204827183613686497863046575953
Short name T99
Test name
Test status
Simulation time 46939868 ps
CPU time 1.24 seconds
Started Nov 22 12:35:34 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216380 kb
Host smart-6d2b5c75-1e1a-4dca-990f-1f31b0a9fec9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79223228074306128699415414275018969308659897032204827183613686497863046575953 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.7922322807430612869941541427501896930865989703220482718361368649786304
6575953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.19074596702693563064195775945020708310642644653106316317259473899011204805397
Short name T70
Test name
Test status
Simulation time 16922251 ps
CPU time 0.78 seconds
Started Nov 22 12:35:28 PM PST 23
Finished Nov 22 12:35:30 PM PST 23
Peak memory 216196 kb
Host smart-a84f1bde-6f33-4eaf-9b10-65e2ec75da67
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074596702693563064195775945020708310642644653106316317259473899011204805397 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.19074596702693563064195775945020708310642644653106316317259473899011204805397 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.40496237649907242167735613382476152670935069813102236742488058658359233891361
Short name T1109
Test name
Test status
Simulation time 88046682 ps
CPU time 1.69 seconds
Started Nov 22 12:35:32 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216504 kb
Host smart-ba82b354-f616-412f-9a51-7188b642d1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496237649907242167735613382476152670935069813102236742488058658359233891361
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.404962376499072421677356133824761526709350698131022367424880586583
59233891361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.78420349646872477519737586962864115916069224071824992660716521581026760430298
Short name T1089
Test name
Test status
Simulation time 38832790 ps
CPU time 1.05 seconds
Started Nov 22 12:35:50 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 216556 kb
Host smart-2ef39c7a-29cc-48c3-b125-9095c01cf5fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78420349646872477519737586962864115916069224071824992660716521581026760430298 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.784203496468724775197375869628641159160692240718249926607165215810267604
30298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.41676504223150950859658392461385975444339317138412562978221226713954890684667
Short name T1114
Test name
Test status
Simulation time 96832326 ps
CPU time 1.83 seconds
Started Nov 22 12:35:23 PM PST 23
Finished Nov 22 12:35:26 PM PST 23
Peak memory 219952 kb
Host smart-edddd063-dac2-493a-9855-40582cb52e71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416765042231509508596583924613859754443393171384125629782212267139548
90684667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.416765042231509508596583924613859754443393171384
12562978221226713954890684667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.62605337097555975840038961795744645173972862581476311444756578679103818903035
Short name T1174
Test name
Test status
Simulation time 103242989 ps
CPU time 2 seconds
Started Nov 22 12:35:47 PM PST 23
Finished Nov 22 12:35:52 PM PST 23
Peak memory 216580 kb
Host smart-b435f9bc-2137-4404-8d00-af1a051d75fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62605337097555975840038961795744645173972862581476311444756578679103818903035 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.62605337097555975840038961795744645173972862581476311444756578679103818903035 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.42709734635574292144557074804012479218485942726466330284077334251885813047131
Short name T1136
Test name
Test status
Simulation time 193117270 ps
CPU time 3 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:49 PM PST 23
Peak memory 216464 kb
Host smart-8276d3bb-a2cf-46d8-b545-7e4f9779767c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42709734635574292144557074804012479218485942726466330284077334251885813047131 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.42709734635574292144557074804012479218485942726466330284077334251885813047131 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.74641778537573868720593223885272599652125005313457770508494172894027130568925
Short name T1082
Test name
Test status
Simulation time 22940060 ps
CPU time 0.81 seconds
Started Nov 22 12:36:23 PM PST 23
Finished Nov 22 12:36:25 PM PST 23
Peak memory 216260 kb
Host smart-97914711-55f1-4116-bebb-faeeb866a1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74641778537573868720593223885272599652125005313457770508494172894027130568925 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.74641778537573868720593223885272599652125005313457770508494172894027130568925 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.53389919907562500055918172095911491136931336113972598349702209769698921749625
Short name T1218
Test name
Test status
Simulation time 22940060 ps
CPU time 0.82 seconds
Started Nov 22 12:36:19 PM PST 23
Finished Nov 22 12:36:21 PM PST 23
Peak memory 216196 kb
Host smart-2fdea111-4e21-4c44-b3ef-caedcd455918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53389919907562500055918172095911491136931336113972598349702209769698921749625 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.53389919907562500055918172095911491136931336113972598349702209769698921749625 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.82981450641881044527639429027726851440710180479810894876174609585333879455273
Short name T1091
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:36:17 PM PST 23
Finished Nov 22 12:36:20 PM PST 23
Peak memory 216232 kb
Host smart-8bc85208-ce3e-43d5-85e5-0b5487295c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82981450641881044527639429027726851440710180479810894876174609585333879455273 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.82981450641881044527639429027726851440710180479810894876174609585333879455273 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.92623249313561730677816978641170087031805732898848224349128810021806359526370
Short name T1125
Test name
Test status
Simulation time 22940060 ps
CPU time 0.82 seconds
Started Nov 22 12:36:18 PM PST 23
Finished Nov 22 12:36:20 PM PST 23
Peak memory 216232 kb
Host smart-ff88e57d-8314-4f7c-adba-8927aafca806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92623249313561730677816978641170087031805732898848224349128810021806359526370 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.92623249313561730677816978641170087031805732898848224349128810021806359526370 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.114877457314448272610254824690066506594885344494812053270546459194307171076631
Short name T1106
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:36:28 PM PST 23
Peak memory 216264 kb
Host smart-52af2e46-ee00-4164-915d-b2c22d03bd5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114877457314448272610254824690066506594885344494812053270546459194307171076631 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.114877457314448272610254824690066506594885344494812053270546459194307171076631 +enable_masking=1
+sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.96765729460176135289121795482963962350624168912378326340691993942891467025708
Short name T116
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:36:18 PM PST 23
Finished Nov 22 12:36:21 PM PST 23
Peak memory 216256 kb
Host smart-294057ff-4c09-4b5d-ab11-56e9002f5be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96765729460176135289121795482963962350624168912378326340691993942891467025708 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.96765729460176135289121795482963962350624168912378326340691993942891467025708 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.17791076847675965215981480755369639402453079171692191748704075688631781605801
Short name T1122
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:22 PM PST 23
Peak memory 216268 kb
Host smart-4a0ce4d7-eb55-40a1-8cb1-d7f68cd913e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791076847675965215981480755369639402453079171692191748704075688631781605801 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.17791076847675965215981480755369639402453079171692191748704075688631781605801 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.38317335782487673276448503186024537967227168740860170407720450093448314585095
Short name T1197
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:23 PM PST 23
Peak memory 216304 kb
Host smart-b46235c2-fca1-4d2c-ab93-256cf071c48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38317335782487673276448503186024537967227168740860170407720450093448314585095 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.38317335782487673276448503186024537967227168740860170407720450093448314585095 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.45590088390911144132607875872633656502943581462946774562217641162872488250413
Short name T1143
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:36:28 PM PST 23
Peak memory 216268 kb
Host smart-35b8b473-8245-4e13-95d7-27680f9efaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45590088390911144132607875872633656502943581462946774562217641162872488250413 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.45590088390911144132607875872633656502943581462946774562217641162872488250413 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.111458832149636178343366000435507337730388889410016885302136763743183078171890
Short name T117
Test name
Test status
Simulation time 22940060 ps
CPU time 0.82 seconds
Started Nov 22 12:36:22 PM PST 23
Finished Nov 22 12:36:24 PM PST 23
Peak memory 216300 kb
Host smart-c0b54fea-4798-4be4-a377-49c720d0cca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111458832149636178343366000435507337730388889410016885302136763743183078171890 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.111458832149636178343366000435507337730388889410016885302136763743183078171890 +enable_masking=1
+sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.16508775115308783817480135367872415109392769608865497107393501356801605923825
Short name T1228
Test name
Test status
Simulation time 30368572 ps
CPU time 1.32 seconds
Started Nov 22 12:35:35 PM PST 23
Finished Nov 22 12:35:38 PM PST 23
Peak memory 219940 kb
Host smart-039277ba-6680-4c5e-8bfb-ea3d7b22bc71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650877511530878381748013536787241510939276
9608865497107393501356801605923825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1650877511530878381748013
5367872415109392769608865497107393501356801605923825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.17152192464666909757541631271585731083772361685962272989544392199854846524819
Short name T114
Test name
Test status
Simulation time 32814981 ps
CPU time 1.01 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:47 PM PST 23
Peak memory 216276 kb
Host smart-04ebe2a6-78cd-42ab-ba70-6da295472026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152192464666909757541631271585731083772361685962272989544392199854846524819 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.17152192464666909757541631271585731083772361685962272989544392199854846524819 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.77783617134612640676748843612144808833441603218761669188381586938536615522039
Short name T1151
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:47 PM PST 23
Peak memory 216272 kb
Host smart-d3ea87db-2470-4a4d-98bf-b470985b51ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77783617134612640676748843612144808833441603218761669188381586938536615522039 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.77783617134612640676748843612144808833441603218761669188381586938536615522039 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.7686902469090634279678014367590417985379652615495243010747220520775996016743
Short name T1110
Test name
Test status
Simulation time 88046682 ps
CPU time 1.63 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216444 kb
Host smart-6fb69e65-e184-460a-ae75-185f1ef665df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7686902469090634279678014367590417985379652615495243010747220520775996016743 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.7686902469090634279678014367590417985379652615495243010747220520775
996016743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.57776249288565011829265044954230537790008187850579511226842414988159021925785
Short name T1102
Test name
Test status
Simulation time 38832790 ps
CPU time 1.09 seconds
Started Nov 22 12:35:54 PM PST 23
Finished Nov 22 12:35:56 PM PST 23
Peak memory 216552 kb
Host smart-be9d1652-0d1a-4f92-90f2-1aab3e8d315c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57776249288565011829265044954230537790008187850579511226842414988159021925785 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.577762492885650118292650449542305377900081878505795112268424149881590219
25785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.103634487000494187595373130735591455052409915252252828367656241330364469879943
Short name T1153
Test name
Test status
Simulation time 96832326 ps
CPU time 1.8 seconds
Started Nov 22 12:35:50 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 219988 kb
Host smart-02a13c5d-e913-4fc5-ac3c-3167b88bcb6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103634487000494187595373130735591455052409915252252828367656241330364
469879943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.10363448700049418759537313073559145505240991525
2252828367656241330364469879943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.60953957848087300096999693411414412385285731749490796021696905722306106645743
Short name T92
Test name
Test status
Simulation time 103242989 ps
CPU time 2.08 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216600 kb
Host smart-146b9a13-0c8b-474a-8d0f-2f3b1f86427f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60953957848087300096999693411414412385285731749490796021696905722306106645743 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.60953957848087300096999693411414412385285731749490796021696905722306106645743 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.104893056780963517454289168302320243799210950945412184715577791187119869687966
Short name T1161
Test name
Test status
Simulation time 193117270 ps
CPU time 3.2 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 216524 kb
Host smart-20d38c64-6edf-4889-8c8b-115933c20c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104893056780963517454289168302320243799210950945412184715577791187119869687966 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.104893056780963517454289168302320243799210950945412184715577791187119869687966 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.35892372717725771003124260580175557448461979730645968330122428943029819706422
Short name T1163
Test name
Test status
Simulation time 30368572 ps
CPU time 1.34 seconds
Started Nov 22 12:35:37 PM PST 23
Finished Nov 22 12:35:42 PM PST 23
Peak memory 219948 kb
Host smart-2ed88b88-8f71-4937-8e07-5dc4b1d59ee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589237271772577100312426058017555744846197
9730645968330122428943029819706422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3589237271772577100312426
0580175557448461979730645968330122428943029819706422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.30029026062297239736311738979758293982458326136183360117384877916775581648567
Short name T1104
Test name
Test status
Simulation time 32814981 ps
CPU time 1.04 seconds
Started Nov 22 12:35:53 PM PST 23
Finished Nov 22 12:35:55 PM PST 23
Peak memory 216236 kb
Host smart-068a6223-d89b-4ca4-b62e-f9e0ea47a213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30029026062297239736311738979758293982458326136183360117384877916775581648567 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.30029026062297239736311738979758293982458326136183360117384877916775581648567 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.98863050452190039526549507070172051803655990567001365718663025946173399601886
Short name T1165
Test name
Test status
Simulation time 22940060 ps
CPU time 0.79 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:47 PM PST 23
Peak memory 216200 kb
Host smart-87ef4beb-8a62-4286-b55a-a78e0da490c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98863050452190039526549507070172051803655990567001365718663025946173399601886 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.98863050452190039526549507070172051803655990567001365718663025946173399601886 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.44421097086642301731849115081020839324645616080331518572455439764128986723360
Short name T1170
Test name
Test status
Simulation time 88046682 ps
CPU time 1.67 seconds
Started Nov 22 12:35:49 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 216432 kb
Host smart-6dff4172-7341-4f18-b353-db1f5fda5672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44421097086642301731849115081020839324645616080331518572455439764128986723360
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.444210970866423017318491150810208393246456160803315185724554397641
28986723360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2869876743322101527373550718713631096524809110015595352577803583697561499800
Short name T112
Test name
Test status
Simulation time 38832790 ps
CPU time 1.05 seconds
Started Nov 22 12:35:39 PM PST 23
Finished Nov 22 12:35:42 PM PST 23
Peak memory 216548 kb
Host smart-d7f2a263-6c69-491f-a5ae-6dca20acadec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869876743322101527373550718713631096524809110015595352577803583697561499800 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2869876743322101527373550718713631096524809110015595352577803583697561499
800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.55690566313410410817717928761536997325472804675520813484631024322523763534815
Short name T106
Test name
Test status
Simulation time 96832326 ps
CPU time 1.75 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 219952 kb
Host smart-be8f83bb-5332-4595-ac36-3ba59bfb9968
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556905663134104108177179287615369973254728046755208134846310243225237
63534815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.556905663134104108177179287615369973254728046755
20813484631024322523763534815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.36558101543403742051633389615167674834807059081291311125221880070697896359333
Short name T93
Test name
Test status
Simulation time 103242989 ps
CPU time 2.07 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 216632 kb
Host smart-48ce0422-c543-4527-8c97-f3da406e5746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558101543403742051633389615167674834807059081291311125221880070697896359333 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.36558101543403742051633389615167674834807059081291311125221880070697896359333 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.106194833758208318522319269360604688015785527094754570449863716190961471132409
Short name T1210
Test name
Test status
Simulation time 193117270 ps
CPU time 2.86 seconds
Started Nov 22 12:35:38 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 216464 kb
Host smart-0f7e53db-2fab-4ee8-9b5b-2b28f8fc2669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106194833758208318522319269360604688015785527094754570449863716190961471132409 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.106194833758208318522319269360604688015785527094754570449863716190961471132409 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.65555262043464885027579781745484017471139203489860404480119831292353913062834
Short name T1088
Test name
Test status
Simulation time 30368572 ps
CPU time 1.29 seconds
Started Nov 22 12:35:37 PM PST 23
Finished Nov 22 12:35:40 PM PST 23
Peak memory 219920 kb
Host smart-31a5b976-bca5-4592-9b65-4753f98ac391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6555526204346488502757978174548401747113920
3489860404480119831292353913062834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.6555526204346488502757978
1745484017471139203489860404480119831292353913062834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.82060059596532701206707651807160368403237497572485331373140583994297291720710
Short name T1140
Test name
Test status
Simulation time 32814981 ps
CPU time 0.97 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 216260 kb
Host smart-b8c53747-312d-414b-b3a1-417986d71ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82060059596532701206707651807160368403237497572485331373140583994297291720710 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.82060059596532701206707651807160368403237497572485331373140583994297291720710 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.90052494982635806687532614742817296321021985683535064378094379074596630709659
Short name T1094
Test name
Test status
Simulation time 22940060 ps
CPU time 0.85 seconds
Started Nov 22 12:35:36 PM PST 23
Finished Nov 22 12:35:39 PM PST 23
Peak memory 216320 kb
Host smart-ab27b658-fa61-4ebf-9eb7-c9a5e749ebcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90052494982635806687532614742817296321021985683535064378094379074596630709659 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.90052494982635806687532614742817296321021985683535064378094379074596630709659 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2136533049462852124781125196136445987610697537202347268035026084788661445923
Short name T101
Test name
Test status
Simulation time 88046682 ps
CPU time 1.67 seconds
Started Nov 22 12:35:45 PM PST 23
Finished Nov 22 12:35:48 PM PST 23
Peak memory 216416 kb
Host smart-8dbf46e4-5e56-4f86-ad5a-67ae202931b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136533049462852124781125196136445987610697537202347268035026084788661445923 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.2136533049462852124781125196136445987610697537202347268035026084788
661445923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.41808945326087345389809919834758610435743311623195141478901556956697569893637
Short name T1128
Test name
Test status
Simulation time 38832790 ps
CPU time 1.07 seconds
Started Nov 22 12:35:37 PM PST 23
Finished Nov 22 12:35:42 PM PST 23
Peak memory 216496 kb
Host smart-b5cc2f77-e976-4396-8837-74d201bdc48c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808945326087345389809919834758610435743311623195141478901556956697569893637 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.418089453260873453898099198347586104357433116231951414789015569566975698
93637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.18378504494117852928552272481504933846158598484799336533219327195966470213830
Short name T1173
Test name
Test status
Simulation time 103242989 ps
CPU time 2.05 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 216600 kb
Host smart-53c02033-3733-4b1c-8d2c-9dad667ad25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378504494117852928552272481504933846158598484799336533219327195966470213830 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.18378504494117852928552272481504933846158598484799336533219327195966470213830 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.93363428702238799864748168056375638669052252077858051767896401815927073772760
Short name T1119
Test name
Test status
Simulation time 193117270 ps
CPU time 2.95 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:45 PM PST 23
Peak memory 216488 kb
Host smart-313f40e9-6918-4e20-a826-d228660a0cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93363428702238799864748168056375638669052252077858051767896401815927073772760 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.93363428702238799864748168056375638669052252077858051767896401815927073772760 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.113231186649220598435081829508775266418233626141947049050476815700495931956227
Short name T1124
Test name
Test status
Simulation time 30368572 ps
CPU time 1.29 seconds
Started Nov 22 12:35:39 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 219932 kb
Host smart-a75bb1d1-a87a-4d23-9024-4f297d19d133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132311866492205984350818295087752664182336
26141947049050476815700495931956227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.113231186649220598435081
829508775266418233626141947049050476815700495931956227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.45341544873057326488771473242260200926093788875204424694210116200054686552937
Short name T69
Test name
Test status
Simulation time 32814981 ps
CPU time 0.99 seconds
Started Nov 22 12:35:40 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 216280 kb
Host smart-4e9078eb-c372-48bc-a40d-982ce99632c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45341544873057326488771473242260200926093788875204424694210116200054686552937 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.45341544873057326488771473242260200926093788875204424694210116200054686552937 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.87756091979086213638408067419821744263714548273955217927416717429626486082840
Short name T1178
Test name
Test status
Simulation time 22940060 ps
CPU time 0.78 seconds
Started Nov 22 12:35:35 PM PST 23
Finished Nov 22 12:35:37 PM PST 23
Peak memory 216232 kb
Host smart-5b8afa7f-b37b-4f1a-9ab0-dc844bd2a637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87756091979086213638408067419821744263714548273955217927416717429626486082840 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.87756091979086213638408067419821744263714548273955217927416717429626486082840 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.15682091412118419258963382206868757230481110944674657164025399023147196140435
Short name T1107
Test name
Test status
Simulation time 88046682 ps
CPU time 1.65 seconds
Started Nov 22 12:35:49 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 216432 kb
Host smart-2625fb91-5cbc-4560-be57-423d88432942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682091412118419258963382206868757230481110944674657164025399023147196140435
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.156820914121184192589633822068687572304811109446746571640253990231
47196140435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.49883758909343833243637593572690180352050444548474613299336418492957422671487
Short name T1187
Test name
Test status
Simulation time 38832790 ps
CPU time 1.02 seconds
Started Nov 22 12:36:04 PM PST 23
Finished Nov 22 12:36:06 PM PST 23
Peak memory 216504 kb
Host smart-ca72ad9b-eddb-4667-890b-dbd212e2356d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49883758909343833243637593572690180352050444548474613299336418492957422671487 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.498837589093438332436375935726901803520504445484746132993364184929574226
71487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.109230501357822276761583969080239366065035219631932267228162510861550512610072
Short name T1194
Test name
Test status
Simulation time 96832326 ps
CPU time 1.82 seconds
Started Nov 22 12:35:49 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 219964 kb
Host smart-a9d0ca70-d26f-42b0-a5ce-c9473ad06556
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109230501357822276761583969080239366065035219631932267228162510861550
512610072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.10923050135782227676158396908023936606503521963
1932267228162510861550512610072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.75316777122341382906319283014238176117557659873151715584733665378347545044962
Short name T1155
Test name
Test status
Simulation time 103242989 ps
CPU time 2.05 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:11 PM PST 23
Peak memory 216576 kb
Host smart-2b29af77-f0cd-470e-aad7-a1c00f091bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75316777122341382906319283014238176117557659873151715584733665378347545044962 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.75316777122341382906319283014238176117557659873151715584733665378347545044962 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.43825415323882002420410226413755115453170362565416583411476949671657228034924
Short name T5
Test name
Test status
Simulation time 193117270 ps
CPU time 3.01 seconds
Started Nov 22 12:35:39 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 216464 kb
Host smart-264f15b0-98fd-461e-a171-6d39ec2fb87e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43825415323882002420410226413755115453170362565416583411476949671657228034924 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.43825415323882002420410226413755115453170362565416583411476949671657228034924 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.102018638890666998616469971555913004800144168805165982906884048200493258252639
Short name T1193
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:54 PM PST 23
Peak memory 219904 kb
Host smart-bceef90a-5009-418b-9a79-9bc4e3e0e507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020186388906669986164699715559130048001441
68805165982906884048200493258252639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.102018638890666998616469
971555913004800144168805165982906884048200493258252639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.91354364200257416653195607407010735067522039747466928813158589817642982836414
Short name T1230
Test name
Test status
Simulation time 32814981 ps
CPU time 0.98 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:10 PM PST 23
Peak memory 216248 kb
Host smart-9490e5bd-2e37-474b-87be-99b434dcee22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91354364200257416653195607407010735067522039747466928813158589817642982836414 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.91354364200257416653195607407010735067522039747466928813158589817642982836414 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.28403753566801918485522186526782486150860278940889450522686972737572746631518
Short name T1129
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 12:36:08 PM PST 23
Finished Nov 22 12:36:10 PM PST 23
Peak memory 216248 kb
Host smart-50385b05-d33f-49ae-9b47-76be43d0a434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403753566801918485522186526782486150860278940889450522686972737572746631518 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.28403753566801918485522186526782486150860278940889450522686972737572746631518 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.65799712142229197466488392544030923839288470700747806140821915914170520919810
Short name T1179
Test name
Test status
Simulation time 88046682 ps
CPU time 1.7 seconds
Started Nov 22 12:35:54 PM PST 23
Finished Nov 22 12:35:57 PM PST 23
Peak memory 216392 kb
Host smart-f6f76afb-0b29-4d92-a9d3-f6eb3969b562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65799712142229197466488392544030923839288470700747806140821915914170520919810
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.657997121422291974664883925440309238392884707007478061408219159141
70520919810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.25717631430642821800023762405455850572163477356321656052380613070621314134307
Short name T13
Test name
Test status
Simulation time 38832790 ps
CPU time 1.04 seconds
Started Nov 22 12:35:44 PM PST 23
Finished Nov 22 12:35:47 PM PST 23
Peak memory 216468 kb
Host smart-f4248f7b-9aaf-43a1-a2f8-f17f6ebbb4a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25717631430642821800023762405455850572163477356321656052380613070621314134307 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.257176314306428218000237624054558505721634773563216560523806130706213141
34307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.56670309931240001979179610129688973426369895943171743793479561702550683528742
Short name T1097
Test name
Test status
Simulation time 96832326 ps
CPU time 1.82 seconds
Started Nov 22 12:35:47 PM PST 23
Finished Nov 22 12:35:53 PM PST 23
Peak memory 219988 kb
Host smart-55eb008a-02f7-4fb1-8515-00a6e61609db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566703099312400019791796101296889734263698959431717437934795617025506
83528742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.566703099312400019791796101296889734263698959431
71743793479561702550683528742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.75919409709861720753180791720651838366521954039089094580910512957831708275246
Short name T1231
Test name
Test status
Simulation time 103242989 ps
CPU time 2.05 seconds
Started Nov 22 12:35:52 PM PST 23
Finished Nov 22 12:35:55 PM PST 23
Peak memory 216472 kb
Host smart-ffc9da04-8e8b-4b44-a98c-68b16136da08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75919409709861720753180791720651838366521954039089094580910512957831708275246 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.75919409709861720753180791720651838366521954039089094580910512957831708275246 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.21428353593286476125420826388399445395718782011915284247193375787786392189338
Short name T1236
Test name
Test status
Simulation time 193117270 ps
CPU time 3.04 seconds
Started Nov 22 12:35:41 PM PST 23
Finished Nov 22 12:35:45 PM PST 23
Peak memory 216468 kb
Host smart-bd994526-1da9-44c2-b30b-7fea505b2a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21428353593286476125420826388399445395718782011915284247193375787786392189338 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.21428353593286476125420826388399445395718782011915284247193375787786392189338 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.32802269137882136170054028627345867551052511011086494379705302677812496824949
Short name T890
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:00:16 PM PST 23
Peak memory 218992 kb
Host smart-891fdde7-487e-4318-9f3b-447c38dc34bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802269137882136170054028627345867551052511011086494379705302677812496824949 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.kmac_alert_test.32802269137882136170054028627345867551052511011086494379705302677812496824949 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.50660152308295772356806017467770818125215786676060110324563418870500979130381
Short name T629
Test name
Test status
Simulation time 6076748772 ps
CPU time 95.82 seconds
Started Nov 22 02:00:09 PM PST 23
Finished Nov 22 02:01:46 PM PST 23
Peak memory 236224 kb
Host smart-3ee4051b-86db-41d3-895e-2e7efe4d1c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50660152308295772356806017467770818125215786676060110324563418870500979130381 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_app.50660152308295772356806017467770818125215786676060110324563418870500979130381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.57303001816859950092444872393111707378857339784708989966829103818797654063953
Short name T1033
Test name
Test status
Simulation time 7277596308 ps
CPU time 113.3 seconds
Started Nov 22 02:00:16 PM PST 23
Finished Nov 22 02:02:10 PM PST 23
Peak memory 243836 kb
Host smart-0af57b36-05e4-40fe-94c9-7a899ecc1e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57303001816859950092444872393111707378857339784708989966829103818797654063953 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_app_with_partial_data.57303001816859950092444872393111707378857339784708989966829103818797654063953 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.82117545446325348905668964957615662201181910177371491021039331319361434979567
Short name T422
Test name
Test status
Simulation time 14830000174 ps
CPU time 376.01 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:06:29 PM PST 23
Peak memory 243256 kb
Host smart-d489abd3-37ea-47d3-86dd-cdc2b798a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82117545446325348905668964957615662201181910177371491021039331319361434979567 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.kmac_burst_write.82117545446325348905668964957615662201181910177371491021039331319361434979567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.27693720727281002804493220086688294549119114633843645736162082204174207144108
Short name T827
Test name
Test status
Simulation time 62261174 ps
CPU time 1.26 seconds
Started Nov 22 02:00:08 PM PST 23
Finished Nov 22 02:00:11 PM PST 23
Peak memory 218960 kb
Host smart-1f8c7783-9ddd-4b3f-b90a-906f0d74c853
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=27693720727281002804493220086688294549119114633843645736162082204174207144108 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.kmac_edn_timeout_error.27693720727281002804493220086688294549119114633843645736162082204174207144108 +enable_masking=1
+sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.107245266425893001620698509328375165540424608858490047146170516855382003954641
Short name T292
Test name
Test status
Simulation time 64850439 ps
CPU time 1.21 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 219044 kb
Host smart-62df27db-4818-495e-b552-c5e8fbb5320e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107245266425893001620698509328375165540424608858490047146170516855382003954641 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.107245266425893001620698509328375165540424608858490047146170516855382003954641 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.76658796824869237654055732770667542332206464544253665604445609524910831088803
Short name T643
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.2 seconds
Started Nov 22 02:00:22 PM PST 23
Finished Nov 22 02:00:45 PM PST 23
Peak memory 219296 kb
Host smart-04873e54-cc1f-4315-84bb-5113eba3ab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76658796824869237654055732770667542332206464544253665604445609524910831088803 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.kmac_entropy_ready_error.76658796824869237654055732770667542332206464544253665604445609524910831088803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.111329745887117638432927174347053339562884332685783168818146328670374623625816
Short name T680
Test name
Test status
Simulation time 7238810904 ps
CPU time 107.32 seconds
Started Nov 22 02:00:15 PM PST 23
Finished Nov 22 02:02:04 PM PST 23
Peak memory 243844 kb
Host smart-7f552b74-fed2-43b7-924d-72b52b61b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111329745887117638432927174347053339562884332685783168818146328670374623625816 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_entropy_refresh.111329745887117638432927174347053339562884332685783168818146328670374623625816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.11130631740598873873953285626651298660599202098465135127606520546809258251142
Short name T682
Test name
Test status
Simulation time 8137821569 ps
CPU time 152.01 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:02:44 PM PST 23
Peak memory 252768 kb
Host smart-bd069631-0e7e-47fd-a502-e9ec704103bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11130631740598873873953285626651298660599202098465135127606520546809258251142 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.kmac_error.11130631740598873873953285626651298660599202098465135127606520546809258251142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.115199006869609199221089610450167193324514047355717971079993007814043442468927
Short name T555
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.6 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 219264 kb
Host smart-4616e740-ec31-4e2a-acc1-2db5cf4b98ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115199006869609199221089610450167193324514047355717971079993007814043442468927 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.kmac_key_error.115199006869609199221089610450167193324514047355717971079993007814043442468927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.36200159975763851316056384753273603674119517674160837658043653057785447708883
Short name T1000
Test name
Test status
Simulation time 72761090 ps
CPU time 1.54 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 220456 kb
Host smart-c0c5c0c5-d020-4f82-86ae-6f7254cc2b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36200159975763851316056384753273603674119517674160837658043653057785447708883 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.kmac_lc_escalation.36200159975763851316056384753273603674119517674160837658043653057785447708883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.16798594811684712337543431612256622916971129369009882406069276196800208303806
Short name T601
Test name
Test status
Simulation time 50513696845 ps
CPU time 1026.64 seconds
Started Nov 22 02:00:09 PM PST 23
Finished Nov 22 02:17:17 PM PST 23
Peak memory 306368 kb
Host smart-77567c75-a55c-4b22-bb7e-d5f55ce70f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16798594811684712337543431612256622916971129369009882406069276196800208303806 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1679859481168471233754343161225662291697112936900988240606927619680020
8303806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.87980090432264268529366568454358879592609166688409505102195636833826253285948
Short name T931
Test name
Test status
Simulation time 7712378544 ps
CPU time 136.92 seconds
Started Nov 22 02:00:23 PM PST 23
Finished Nov 22 02:02:41 PM PST 23
Peak memory 244020 kb
Host smart-a5153b13-ced2-456f-8dde-e93a9a9dd581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87980090432264268529366568454358879592609166688409505102195636833826253285948 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.kmac_mubi.87980090432264268529366568454358879592609166688409505102195636833826253285948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.102968823094884080961605085856443855151754996723453463539617757814820748096753
Short name T81
Test name
Test status
Simulation time 6415496062 ps
CPU time 55.14 seconds
Started Nov 22 02:00:14 PM PST 23
Finished Nov 22 02:01:11 PM PST 23
Peak memory 277264 kb
Host smart-7567c1cb-21e9-4480-b0c4-1d7369441d65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102968823094884080961605085856443855151754996723453463539617757814820748096753 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.kmac_sec_cm.102968823094884080961605085856443855151754996723453463539617757814820748096753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.94794768084279915053732069097464227153373084296957279734569909492670343007219
Short name T740
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.19 seconds
Started Nov 22 02:00:16 PM PST 23
Finished Nov 22 02:02:36 PM PST 23
Peak memory 236400 kb
Host smart-fc9909f4-886f-4ffa-95d8-a406a33a599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94794768084279915053732069097464227153373084296957279734569909492670343007219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.kmac_sideload.94794768084279915053732069097464227153373084296957279734569909492670343007219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.94365482933429910507535243299138124562231617208014694654881577581331738468833
Short name T225
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.96 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:00:40 PM PST 23
Peak memory 225196 kb
Host smart-f2d6f302-0283-49f0-acdf-90e663e12b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94365482933429910507535243299138124562231617208014694654881577581331738468833 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.kmac_smoke.94365482933429910507535243299138124562231617208014694654881577581331738468833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.101874208246861729901536428851726235223437689804562803809664357779178545276192
Short name T862
Test name
Test status
Simulation time 47207151869 ps
CPU time 924.68 seconds
Started Nov 22 02:00:24 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 339768 kb
Host smart-17523692-b6f6-4c5a-9165-1c5da2d41981
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=101874208246861729901536428851726235223437689804562803809664357779178545276192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_st
ress_all.101874208246861729901536428851726235223437689804562803809664357779178545276192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.24720796093687428022933208859155656733059545575825522771766208818182901223850
Short name T790
Test name
Test status
Simulation time 322955517 ps
CPU time 5.93 seconds
Started Nov 22 02:00:14 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 219264 kb
Host smart-c3e49511-21fa-4074-ada4-b8c729ff2748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720796093687428022933208859155656733059545575825522
771766208818182901223850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.247207960936874280229332088591556567330
59545575825522771766208818182901223850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.89917545028508800588425041488715453553625472175745675389739417707832685609873
Short name T502
Test name
Test status
Simulation time 309259198 ps
CPU time 5.66 seconds
Started Nov 22 02:00:10 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 219288 kb
Host smart-da5dac25-145e-4a43-a49f-4dd319cd7707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89917545028508800588425041488715453553625472175745675
389739417707832685609873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.8991754502850880058842504148871
5453553625472175745675389739417707832685609873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.65054844949978902745330875871639659586852645681425863886557668051756767067406
Short name T1015
Test name
Test status
Simulation time 117329894454 ps
CPU time 2236.31 seconds
Started Nov 22 02:00:24 PM PST 23
Finished Nov 22 02:37:41 PM PST 23
Peak memory 400884 kb
Host smart-bd85d320-5a19-4478-b46e-76632e4459ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65054844949978902745330875871639659586852645681425863886557668051756767067406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_224.65054844949978902745330875871639659586852645681425863886557668051756767067406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3102388040936902422147992520147626005618501617405053076071863366389022187501
Short name T162
Test name
Test status
Simulation time 106843317633 ps
CPU time 1896.76 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:31:50 PM PST 23
Peak memory 376472 kb
Host smart-f970d441-e410-4f79-8ccb-775c36ef6f4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3102388040936902422147992520147626005618501617405053076071863366389022187501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.k
mac_test_vectors_sha3_256.3102388040936902422147992520147626005618501617405053076071863366389022187501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.39266988911365734828454173118354439467403231195345946043097894330828870469660
Short name T966
Test name
Test status
Simulation time 83520343504 ps
CPU time 1654.46 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:27:49 PM PST 23
Peak memory 338440 kb
Host smart-c7179371-e415-4b14-abb5-03e2a1404214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=39266988911365734828454173118354439467403231195345946043097894330828870469660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_384.39266988911365734828454173118354439467403231195345946043097894330828870469660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.110381017353688122214910174280594008845277847452433002022033413290957825494746
Short name T648
Test name
Test status
Simulation time 57499426673 ps
CPU time 1219.05 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:20:33 PM PST 23
Peak memory 297756 kb
Host smart-db07ded0-b8fe-4986-bbe3-6b6dff3e03b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=110381017353688122214910174280594008845277847452433002022033413290957825494746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.kmac_test_vectors_sha3_512.110381017353688122214910174280594008845277847452433002022033413290957825494746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.42413897771829469942919251143920047809049118608032637550292089094465208597733
Short name T238
Test name
Test status
Simulation time 320694338954 ps
CPU time 5546.32 seconds
Started Nov 22 02:00:24 PM PST 23
Finished Nov 22 03:32:52 PM PST 23
Peak memory 674276 kb
Host smart-3ae848b3-1193-4d62-b9c4-d46be9d7d382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42413897771829469942919251143920047809049118608032637550292089094465208597733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_test_vectors_shake_128.42413897771829469942919251143920047809049118608032637550292089094465208597733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.24527990351135712152307039239306019292294929335116823474960477252362034873089
Short name T421
Test name
Test status
Simulation time 270085708112 ps
CPU time 4698.13 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 03:18:30 PM PST 23
Peak memory 577212 kb
Host smart-90d8652c-31d7-42f3-8765-ed79597f0d3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=24527990351135712152307039239306019292294929335116823474960477252362034873089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_test_vectors_shake_256.24527990351135712152307039239306019292294929335116823474960477252362034873089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_app.19399330810093772059612715935623764992111328180360139596924532399892071740279
Short name T308
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.88 seconds
Started Nov 22 02:00:16 PM PST 23
Finished Nov 22 02:01:57 PM PST 23
Peak memory 236244 kb
Host smart-be4237af-7d59-4e80-98ea-c27b731a254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19399330810093772059612715935623764992111328180360139596924532399892071740279 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_app.19399330810093772059612715935623764992111328180360139596924532399892071740279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.14421144985491091000619713347896616314893542454828284271172243135638328809975
Short name T712
Test name
Test status
Simulation time 7277596308 ps
CPU time 109.9 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:02:21 PM PST 23
Peak memory 243900 kb
Host smart-7274d388-8e84-4892-afbb-90c626d80b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14421144985491091000619713347896616314893542454828284271172243135638328809975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_app_with_partial_data.14421144985491091000619713347896616314893542454828284271172243135638328809975 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.96918710370906940395307819670116385431106543925217728559333500405675196625869
Short name T1008
Test name
Test status
Simulation time 14830000174 ps
CPU time 381.01 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:06:36 PM PST 23
Peak memory 243272 kb
Host smart-649d9303-f8bd-4a81-b812-7fbef828e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96918710370906940395307819670116385431106543925217728559333500405675196625869 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.kmac_burst_write.96918710370906940395307819670116385431106543925217728559333500405675196625869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.69998628612926309489545055752772385802507844095604049668833760969883463322299
Short name T753
Test name
Test status
Simulation time 64850439 ps
CPU time 1.31 seconds
Started Nov 22 02:00:27 PM PST 23
Finished Nov 22 02:00:29 PM PST 23
Peak memory 219020 kb
Host smart-7021166a-b54e-4403-9363-b8d786a5b5e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69998628612926309489545055752772385802507844095604049668833760969883463322299 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.69998628612926309489545055752772385802507844095604049668833760969883463322299 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.42769673316278137006779472786019584697425539069058776733036209342611526359801
Short name T746
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.16 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:00:51 PM PST 23
Peak memory 219336 kb
Host smart-5c1ac623-877a-43de-8285-8def3bc7a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42769673316278137006779472786019584697425539069058776733036209342611526359801 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.kmac_entropy_ready_error.42769673316278137006779472786019584697425539069058776733036209342611526359801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.109631601680862280963270053477857632550667303019913400412464514425437967046872
Short name T898
Test name
Test status
Simulation time 7238810904 ps
CPU time 116.47 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 243880 kb
Host smart-311d9f03-d2fc-46e0-a050-06a59309712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109631601680862280963270053477857632550667303019913400412464514425437967046872 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_entropy_refresh.109631601680862280963270053477857632550667303019913400412464514425437967046872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.92642759950089110320577325119152223947110438371566605731413425192638328051973
Short name T709
Test name
Test status
Simulation time 8137821569 ps
CPU time 138.69 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:02:47 PM PST 23
Peak memory 252632 kb
Host smart-90dbcd44-861d-485d-8037-9d316bed28a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92642759950089110320577325119152223947110438371566605731413425192638328051973 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.kmac_error.92642759950089110320577325119152223947110438371566605731413425192638328051973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.51389540004344381680375794685377398745464512650763297046432610281789462277736
Short name T318
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 220380 kb
Host smart-07b8a780-a658-4316-a936-d0a559bf81e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51389540004344381680375794685377398745464512650763297046432610281789462277736 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.kmac_lc_escalation.51389540004344381680375794685377398745464512650763297046432610281789462277736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.4663605941998579663773747814595423178455909335718055062766823720806879831901
Short name T517
Test name
Test status
Simulation time 50513696845 ps
CPU time 994.64 seconds
Started Nov 22 02:00:09 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 306348 kb
Host smart-5c16dcfb-ceae-43ab-8e28-8bb96998a360
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4663605941998579663773747814595423178455909335718055062766823720806879831901 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.46636059419985796637737478145954231784559093357180550627668237208068798
31901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.80849762266220063492705656960873645052179777371908878343971538341486733929495
Short name T507
Test name
Test status
Simulation time 7712378544 ps
CPU time 139.42 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:02:51 PM PST 23
Peak memory 244140 kb
Host smart-61a225cf-4aae-4b88-80e8-09baced226f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80849762266220063492705656960873645052179777371908878343971538341486733929495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.kmac_mubi.80849762266220063492705656960873645052179777371908878343971538341486733929495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.81352142099228026509885442522223541229450696803994366094865424582539751025228
Short name T717
Test name
Test status
Simulation time 7628111361 ps
CPU time 136.12 seconds
Started Nov 22 02:00:13 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 236384 kb
Host smart-59461e38-3474-4353-b45d-ed521472824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81352142099228026509885442522223541229450696803994366094865424582539751025228 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.kmac_sideload.81352142099228026509885442522223541229450696803994366094865424582539751025228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.108269508270714517544120010405144478923419270183337969407562723829094968449645
Short name T413
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.57 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:00:40 PM PST 23
Peak memory 225392 kb
Host smart-2f16b60f-9cf9-40b4-b0eb-0260d5c86a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108269508270714517544120010405144478923419270183337969407562723829094968449645 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.kmac_smoke.108269508270714517544120010405144478923419270183337969407562723829094968449645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.109726412176325913144051300490450491848389774524099363172315102548058704246611
Short name T481
Test name
Test status
Simulation time 47207151869 ps
CPU time 877.42 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:15:06 PM PST 23
Peak memory 339808 kb
Host smart-f509c0d1-d2e6-400e-9f90-e2958e693edd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=109726412176325913144051300490450491848389774524099363172315102548058704246611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_st
ress_all.109726412176325913144051300490450491848389774524099363172315102548058704246611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.39289324088266510534515632849429760015342014816481236335029253837146059282367
Short name T357
Test name
Test status
Simulation time 322955517 ps
CPU time 6.07 seconds
Started Nov 22 02:00:15 PM PST 23
Finished Nov 22 02:00:22 PM PST 23
Peak memory 217876 kb
Host smart-b7d0655d-d7b0-410c-a516-4809aac7ef00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39289324088266510534515632849429760015342014816481236
335029253837146059282367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.392893240882665105345156328494297600153
42014816481236335029253837146059282367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.106365304063833032596686350637343762870141326954869582157153713839016775907600
Short name T671
Test name
Test status
Simulation time 309259198 ps
CPU time 5.7 seconds
Started Nov 22 02:00:15 PM PST 23
Finished Nov 22 02:00:22 PM PST 23
Peak memory 217852 kb
Host smart-6fd8e6bb-9bd7-4a78-8693-cd99a114d239
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636530406383303259668635063734376287014132695486958
2157153713839016775907600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.106365304063833032596686350637
343762870141326954869582157153713839016775907600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.22074462766723121899974581245020457073921168822030060311838089767960736271693
Short name T831
Test name
Test status
Simulation time 117329894454 ps
CPU time 2026.44 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:34:00 PM PST 23
Peak memory 400672 kb
Host smart-0baf6943-75e3-495b-83b1-f35c27aa56f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=22074462766723121899974581245020457073921168822030060311838089767960736271693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_224.22074462766723121899974581245020457073921168822030060311838089767960736271693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.17628193134953964853182211459230681683128244251855590556442648800107578834002
Short name T569
Test name
Test status
Simulation time 106843317633 ps
CPU time 1912.29 seconds
Started Nov 22 02:00:12 PM PST 23
Finished Nov 22 02:32:05 PM PST 23
Peak memory 376376 kb
Host smart-e98a3920-606c-459e-a532-465b9e6c9a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17628193134953964853182211459230681683128244251855590556442648800107578834002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_256.17628193134953964853182211459230681683128244251855590556442648800107578834002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.6768357478793939515438591254616045127034584598493793414288219099599262581904
Short name T217
Test name
Test status
Simulation time 83520343504 ps
CPU time 1644.9 seconds
Started Nov 22 02:00:10 PM PST 23
Finished Nov 22 02:27:36 PM PST 23
Peak memory 338484 kb
Host smart-c08fd654-876b-4f5d-96a3-e787e1c30936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=6768357478793939515438591254616045127034584598493793414288219099599262581904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.k
mac_test_vectors_sha3_384.6768357478793939515438591254616045127034584598493793414288219099599262581904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.103191942391158940263444826534927858878827635229795648460934187340087477183650
Short name T1054
Test name
Test status
Simulation time 57499426673 ps
CPU time 1171.73 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 02:19:44 PM PST 23
Peak memory 297668 kb
Host smart-ff0027a1-ddd8-4c5b-940d-15fe6be6bc57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=103191942391158940263444826534927858878827635229795648460934187340087477183650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.kmac_test_vectors_sha3_512.103191942391158940263444826534927858878827635229795648460934187340087477183650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.42051765789556427926366408508573687205724702681104259071608506045476503031039
Short name T655
Test name
Test status
Simulation time 320694338954 ps
CPU time 5401.69 seconds
Started Nov 22 02:00:11 PM PST 23
Finished Nov 22 03:30:14 PM PST 23
Peak memory 674188 kb
Host smart-3523d4ac-41fe-493a-b1ee-a67f1cf97742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42051765789556427926366408508573687205724702681104259071608506045476503031039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_test_vectors_shake_128.42051765789556427926366408508573687205724702681104259071608506045476503031039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.10788927404426411745217926775021873169717857889795682859185020053167184406927
Short name T910
Test name
Test status
Simulation time 270085708112 ps
CPU time 4580.38 seconds
Started Nov 22 02:00:14 PM PST 23
Finished Nov 22 03:16:37 PM PST 23
Peak memory 577176 kb
Host smart-fa530a36-df31-447e-a54d-1b9cee261d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10788927404426411745217926775021873169717857889795682859185020053167184406927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_test_vectors_shake_256.10788927404426411745217926775021873169717857889795682859185020053167184406927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.75263513322175330332249881577551722441838079780115732559476180273234751448486
Short name T74
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 02:01:30 PM PST 23
Finished Nov 22 02:01:32 PM PST 23
Peak memory 218964 kb
Host smart-364e3b17-5fff-4dbd-9d21-f6155ce1279d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75263513322175330332249881577551722441838079780115732559476180273234751448486 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.kmac_alert_test.75263513322175330332249881577551722441838079780115732559476180273234751448486 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.45735654468401937193265437112128227304272427963526336039265921071494522391800
Short name T150
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.33 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:04:07 PM PST 23
Peak memory 236228 kb
Host smart-a63b08a6-69c6-4bdf-bf7b-d7fdfc5f7731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45735654468401937193265437112128227304272427963526336039265921071494522391800 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.kmac_app.45735654468401937193265437112128227304272427963526336039265921071494522391800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.4705313724334291725259775086999406249582952830237772780685636573001484483514
Short name T596
Test name
Test status
Simulation time 14830000174 ps
CPU time 405.66 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:09:22 PM PST 23
Peak memory 243244 kb
Host smart-641021a4-44d3-4bb8-b6f2-25d587e32d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4705313724334291725259775086999406249582952830237772780685636573001484483514 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.kmac_burst_write.4705313724334291725259775086999406249582952830237772780685636573001484483514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.19171113349547915327901565188492014375910195841974109923749511663914605159563
Short name T940
Test name
Test status
Simulation time 62261174 ps
CPU time 1.22 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219092 kb
Host smart-2d322b23-cee9-451c-8d5d-e89c45354af9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=19171113349547915327901565188492014375910195841974109923749511663914605159563 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.kmac_edn_timeout_error.19171113349547915327901565188492014375910195841974109923749511663914605159563 +enable_masking=1
+sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.65630775968054430234876184714125942738395261579526202169971556816393530019856
Short name T395
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.67 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:20 PM PST 23
Peak memory 243872 kb
Host smart-0fc4dce7-5b49-4a2b-a953-af9f44e3abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65630775968054430234876184714125942738395261579526202169971556816393530019856 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.kmac_entropy_refresh.65630775968054430234876184714125942738395261579526202169971556816393530019856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.107953685057930061941906388004056247782537405716291554404865091403659048741704
Short name T845
Test name
Test status
Simulation time 8137821569 ps
CPU time 139.55 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:49 PM PST 23
Peak memory 252476 kb
Host smart-dfd9bcc6-f799-4fe5-9cab-408c36a094cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107953685057930061941906388004056247782537405716291554404865091403659048741704 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.kmac_error.107953685057930061941906388004056247782537405716291554404865091403659048741704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.84595416948218110784159299828020981381837610104378075675330444396456745601298
Short name T612
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.77 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 219232 kb
Host smart-56109c11-710a-44ac-bc0f-02150e1f1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84595416948218110784159299828020981381837610104378075675330444396456745601298 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.kmac_key_error.84595416948218110784159299828020981381837610104378075675330444396456745601298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.113994977294684649811992733528720285526324671753659071786743401087250077695246
Short name T771
Test name
Test status
Simulation time 72761090 ps
CPU time 1.53 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 220480 kb
Host smart-3b3a1dcb-6fa3-48f0-b4e5-1dfb943bb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113994977294684649811992733528720285526324671753659071786743401087250077695246 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.kmac_lc_escalation.113994977294684649811992733528720285526324671753659071786743401087250077695246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.48814777212940878046366834224689425599866450847013244598722116619924090762547
Short name T978
Test name
Test status
Simulation time 50513696845 ps
CPU time 1083.08 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:20:36 PM PST 23
Peak memory 306300 kb
Host smart-3aad2824-50f8-4aaf-b7c4-78f20695e107
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48814777212940878046366834224689425599866450847013244598722116619924090762547 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.488147772129408780463668342246894255998664508470132445987221166199240
90762547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.69339265150418401834859236910511268499441773591159534882004288959745592545667
Short name T689
Test name
Test status
Simulation time 7628111361 ps
CPU time 142.91 seconds
Started Nov 22 02:01:16 PM PST 23
Finished Nov 22 02:03:39 PM PST 23
Peak memory 236404 kb
Host smart-0dd67b38-f981-4067-9897-7e684d7c5c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69339265150418401834859236910511268499441773591159534882004288959745592545667 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.kmac_sideload.69339265150418401834859236910511268499441773591159534882004288959745592545667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.51009999234044632247467945889914135240460229891077617136294456819334966628547
Short name T772
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.52 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:57 PM PST 23
Peak memory 225388 kb
Host smart-b985d97b-44c2-4a66-8bd4-f6f30334d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51009999234044632247467945889914135240460229891077617136294456819334966628547 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.kmac_smoke.51009999234044632247467945889914135240460229891077617136294456819334966628547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.13907205126197748303019495849655927702070171538923339141772781459153803134223
Short name T925
Test name
Test status
Simulation time 47207151869 ps
CPU time 908.49 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:17:38 PM PST 23
Peak memory 339800 kb
Host smart-32f473a5-3051-43ab-9601-595d6eefae29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=13907205126197748303019495849655927702070171538923339141772781459153803134223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_st
ress_all.13907205126197748303019495849655927702070171538923339141772781459153803134223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.45672444394193871762588280523276278696464815017923789396054485959203737598182
Short name T719
Test name
Test status
Simulation time 322955517 ps
CPU time 5.73 seconds
Started Nov 22 02:02:29 PM PST 23
Finished Nov 22 02:02:42 PM PST 23
Peak memory 219244 kb
Host smart-4bc08e99-a48c-4a5f-bb68-1edb5a42d67e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45672444394193871762588280523276278696464815017923789
396054485959203737598182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac.45672444394193871762588280523276278696
464815017923789396054485959203737598182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.95395625014251266457625478009952149199755356907549510338755341251337606700520
Short name T715
Test name
Test status
Simulation time 309259198 ps
CPU time 5.83 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:39 PM PST 23
Peak memory 219184 kb
Host smart-357c9409-9f49-47bc-b557-8fd4dd906f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95395625014251266457625478009952149199755356907549510
338755341251337606700520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.953956250142512664576254780099
52149199755356907549510338755341251337606700520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.78760097636277065344385195554645049802830332363612618346802533989600994696888
Short name T850
Test name
Test status
Simulation time 117329894454 ps
CPU time 2095.82 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:37:29 PM PST 23
Peak memory 400912 kb
Host smart-3f7e4e8e-b56f-43b7-ae98-e2dbe58dbb28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=78760097636277065344385195554645049802830332363612618346802533989600994696888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_224.78760097636277065344385195554645049802830332363612618346802533989600994696888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.112301538583112140026172828484701800135870316968416447793603048807724142923748
Short name T658
Test name
Test status
Simulation time 106843317633 ps
CPU time 1923.85 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:34:35 PM PST 23
Peak memory 376480 kb
Host smart-ca46b1ef-5cdc-4364-ba59-388d236c8bbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=112301538583112140026172828484701800135870316968416447793603048807724142923748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.kmac_test_vectors_sha3_256.112301538583112140026172828484701800135870316968416447793603048807724142923748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.17964772585422862051968883471321087792899453287080160514849290013338398362238
Short name T354
Test name
Test status
Simulation time 83520343504 ps
CPU time 1591.84 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:29:01 PM PST 23
Peak memory 338500 kb
Host smart-3da95143-6dba-4112-ab22-d9e2b01ea198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17964772585422862051968883471321087792899453287080160514849290013338398362238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_384.17964772585422862051968883471321087792899453287080160514849290013338398362238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.42845297857375248715968550994400753724232796711088718918397543633973939599013
Short name T885
Test name
Test status
Simulation time 57499426673 ps
CPU time 1198.61 seconds
Started Nov 22 02:01:53 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 297752 kb
Host smart-d97ce796-0a83-460a-a730-c55550e05b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42845297857375248715968550994400753724232796711088718918397543633973939599013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_512.42845297857375248715968550994400753724232796711088718918397543633973939599013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.66961116140253688640889215503203759733059780400923370418167377557464613995261
Short name T701
Test name
Test status
Simulation time 320694338954 ps
CPU time 5384.28 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 03:32:20 PM PST 23
Peak memory 674296 kb
Host smart-6368847e-f0cb-4186-a2d6-b20842bbd9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=66961116140253688640889215503203759733059780400923370418167377557464613995261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.kmac_test_vectors_shake_128.66961116140253688640889215503203759733059780400923370418167377557464613995261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.34001500370196461696992528150232272344594952769721017873443433482904774527981
Short name T181
Test name
Test status
Simulation time 270085708112 ps
CPU time 4636.03 seconds
Started Nov 22 02:01:15 PM PST 23
Finished Nov 22 03:18:33 PM PST 23
Peak memory 577328 kb
Host smart-9c30ae8c-337e-40e4-82f7-31d376e05aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=34001500370196461696992528150232272344594952769721017873443433482904774527981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.kmac_test_vectors_shake_256.34001500370196461696992528150232272344594952769721017873443433482904774527981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.7425453816991847906586349593744010275230961570666673087370340530750282438106
Short name T662
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 219024 kb
Host smart-60798574-b9bf-415f-a86e-6351b9227140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7425453816991847906586349593744010275230961570666673087370340530750282438106 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.kmac_alert_test.7425453816991847906586349593744010275230961570666673087370340530750282438106 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.81930658336225296599330212418764965028390377940150547252311083001141138354984
Short name T335
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.74 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:13 PM PST 23
Peak memory 236200 kb
Host smart-e83bb338-5c9c-4386-a5d0-268edd6f06d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81930658336225296599330212418764965028390377940150547252311083001141138354984 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.kmac_app.81930658336225296599330212418764965028390377940150547252311083001141138354984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.73560873913640291897805686052903023402373991686451246280576759106713050461968
Short name T104
Test name
Test status
Simulation time 14830000174 ps
CPU time 420.46 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:08:32 PM PST 23
Peak memory 243256 kb
Host smart-84a26bf7-5e2a-4b3b-b4fa-57c1751b4473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73560873913640291897805686052903023402373991686451246280576759106713050461968 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.kmac_burst_write.73560873913640291897805686052903023402373991686451246280576759106713050461968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.107986375705177768311244271381232587400247083890901900139548533976424156740147
Short name T964
Test name
Test status
Simulation time 62261174 ps
CPU time 1.26 seconds
Started Nov 22 02:01:40 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 219088 kb
Host smart-b075f736-281a-42e9-a677-e7b5d112824c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107986375705177768311244271381232587400247083890901900139548533976424156740147 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.107986375705177768311244271381232587400247083890901900139548533976424156740147 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.25930061900352060946955535271568164642222549882495213862226391339759036735890
Short name T705
Test name
Test status
Simulation time 64850439 ps
CPU time 1.32 seconds
Started Nov 22 02:02:06 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 219096 kb
Host smart-7bd8daf4-1d09-48b5-a82b-c6792fb7758d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25930061900352060946955535271568164642222549882495213862226391339759036735890 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.25930061900352060946955535271568164642222549882495213862226391339759036735890 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_error.51543403308478079838175851853209653235636376927637978927157751348782012363114
Short name T974
Test name
Test status
Simulation time 8137821569 ps
CPU time 138.15 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 02:04:03 PM PST 23
Peak memory 252772 kb
Host smart-4573195f-5fb6-4f30-b868-6d22e47febf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51543403308478079838175851853209653235636376927637978927157751348782012363114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.kmac_error.51543403308478079838175851853209653235636376927637978927157751348782012363114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.45524935645686849715625076216674809228698576224590929092474242966888086041931
Short name T55
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.86 seconds
Started Nov 22 02:02:01 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 219148 kb
Host smart-9e41f27a-9aba-4d53-b4c2-fcc9f34ba8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45524935645686849715625076216674809228698576224590929092474242966888086041931 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.kmac_key_error.45524935645686849715625076216674809228698576224590929092474242966888086041931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.82983751998321010730685968537813023869063304737121694876416086318600838110033
Short name T882
Test name
Test status
Simulation time 72761090 ps
CPU time 1.48 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:32 PM PST 23
Peak memory 220592 kb
Host smart-afc91e30-0177-43b7-902b-b51186a00d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82983751998321010730685968537813023869063304737121694876416086318600838110033 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.kmac_lc_escalation.82983751998321010730685968537813023869063304737121694876416086318600838110033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.14593818212509957323256270458519736355457395629432289293195222847772938750193
Short name T681
Test name
Test status
Simulation time 50513696845 ps
CPU time 999.84 seconds
Started Nov 22 02:01:39 PM PST 23
Finished Nov 22 02:18:20 PM PST 23
Peak memory 306340 kb
Host smart-6a2ee1c2-3913-4f62-8f14-bb489b5761de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14593818212509957323256270458519736355457395629432289293195222847772938750193 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.145938182125099573232562704585197363554573956294322892931952228477729
38750193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.94080039481933385059440532621550139621407777363035527162412435293645749795441
Short name T560
Test name
Test status
Simulation time 7628111361 ps
CPU time 134.85 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 02:03:51 PM PST 23
Peak memory 236424 kb
Host smart-291d6f80-2444-475e-a8a2-d1964bd73882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94080039481933385059440532621550139621407777363035527162412435293645749795441 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.kmac_sideload.94080039481933385059440532621550139621407777363035527162412435293645749795441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.35334933182520670061819041521348395573551191760180383101929305005003619518746
Short name T732
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.15 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:02:04 PM PST 23
Peak memory 225360 kb
Host smart-b8db4198-d71b-4230-a1be-93a8682c3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35334933182520670061819041521348395573551191760180383101929305005003619518746 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.kmac_smoke.35334933182520670061819041521348395573551191760180383101929305005003619518746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.18554868909597044289416415755381007322337997954040388526838887090698194480079
Short name T918
Test name
Test status
Simulation time 47207151869 ps
CPU time 921.93 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:17:56 PM PST 23
Peak memory 339792 kb
Host smart-754fb807-8049-42d5-8cb0-373e3e25b7fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=18554868909597044289416415755381007322337997954040388526838887090698194480079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_st
ress_all.18554868909597044289416415755381007322337997954040388526838887090698194480079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.45372108210130398044507694768573427496727036096825573921016175596553861576301
Short name T340
Test name
Test status
Simulation time 322955517 ps
CPU time 5.67 seconds
Started Nov 22 02:01:58 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 219200 kb
Host smart-d670b665-f86e-465f-a28e-869ae0b29818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45372108210130398044507694768573427496727036096825573
921016175596553861576301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac.45372108210130398044507694768573427496
727036096825573921016175596553861576301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.68973005901588854228821959593003560272040404705976891557022901467614523718401
Short name T930
Test name
Test status
Simulation time 309259198 ps
CPU time 5.52 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 219280 kb
Host smart-1bf317a1-2d7a-4e9e-80ef-dab56c4c98c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68973005901588854228821959593003560272040404705976891
557022901467614523718401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.689730059015888542288219595930
03560272040404705976891557022901467614523718401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.108580353123014915985043440739312549321633579006830059484367455694312147925630
Short name T663
Test name
Test status
Simulation time 117329894454 ps
CPU time 2121.1 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:36:57 PM PST 23
Peak memory 400880 kb
Host smart-e6c31440-cdf2-4d52-aa68-05f025c77383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=108580353123014915985043440739312549321633579006830059484367455694312147925630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.kmac_test_vectors_sha3_224.108580353123014915985043440739312549321633579006830059484367455694312147925630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.20051845631556377690459751387622086118437479792400903431268939347608594460097
Short name T1070
Test name
Test status
Simulation time 106843317633 ps
CPU time 1854.37 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:32:30 PM PST 23
Peak memory 376396 kb
Host smart-0259baeb-979b-4c71-ac0b-a98d3fe6afe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20051845631556377690459751387622086118437479792400903431268939347608594460097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.kmac_test_vectors_sha3_256.20051845631556377690459751387622086118437479792400903431268939347608594460097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.31768041815930273161887032862654836638174602288719440778462351171914907119919
Short name T396
Test name
Test status
Simulation time 83520343504 ps
CPU time 1545.25 seconds
Started Nov 22 02:02:00 PM PST 23
Finished Nov 22 02:28:10 PM PST 23
Peak memory 338464 kb
Host smart-618e7a83-d262-47d5-bf2a-eadc1a998715
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=31768041815930273161887032862654836638174602288719440778462351171914907119919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.kmac_test_vectors_sha3_384.31768041815930273161887032862654836638174602288719440778462351171914907119919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.106584231158851786562814168511411518426406845591527931528077023318407044570984
Short name T508
Test name
Test status
Simulation time 57499426673 ps
CPU time 1242.78 seconds
Started Nov 22 02:01:40 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 297800 kb
Host smart-d4740b30-e1fb-4144-af2f-6e3ce7a463f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=106584231158851786562814168511411518426406845591527931528077023318407044570984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.kmac_test_vectors_sha3_512.106584231158851786562814168511411518426406845591527931528077023318407044570984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.18517468967129525434595084286511774959369671818558260241436983599264964852155
Short name T1021
Test name
Test status
Simulation time 320694338954 ps
CPU time 5419.16 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 03:31:55 PM PST 23
Peak memory 674308 kb
Host smart-1b0b3638-d945-4946-9102-c7c940415998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=18517468967129525434595084286511774959369671818558260241436983599264964852155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.kmac_test_vectors_shake_128.18517468967129525434595084286511774959369671818558260241436983599264964852155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.5825148147161823766170519547393575264511253564080670000319714181821703454694
Short name T921
Test name
Test status
Simulation time 270085708112 ps
CPU time 4531.87 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 03:17:10 PM PST 23
Peak memory 577248 kb
Host smart-2cb62313-c384-45da-9fb5-9ae77e3af371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=5825148147161823766170519547393575264511253564080670000319714181821703454694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.kmac_test_vectors_shake_256.5825148147161823766170519547393575264511253564080670000319714181821703454694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.59908867863893200170776438969995562383312506978921711422354025087790798660858
Short name T87
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:01:29 PM PST 23
Finished Nov 22 02:01:30 PM PST 23
Peak memory 218888 kb
Host smart-84e66afd-240a-43c3-9dbe-e69722c5f4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59908867863893200170776438969995562383312506978921711422354025087790798660858 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.kmac_alert_test.59908867863893200170776438969995562383312506978921711422354025087790798660858 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.441154805350821581295295388190431946865472849002639718327036247670002711728
Short name T403
Test name
Test status
Simulation time 6076748772 ps
CPU time 96.47 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:04:08 PM PST 23
Peak memory 236156 kb
Host smart-b80c3d2e-92ba-4784-9a89-0f7cd536593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441154805350821581295295388190431946865472849002639718327036247670002711728 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.kmac_app.441154805350821581295295388190431946865472849002639718327036247670002711728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.110279018638885566638632205024397244652543533481750952218178355763257148955896
Short name T631
Test name
Test status
Simulation time 14830000174 ps
CPU time 385.99 seconds
Started Nov 22 02:01:59 PM PST 23
Finished Nov 22 02:08:50 PM PST 23
Peak memory 243196 kb
Host smart-d2db8782-c789-45ab-8331-01dc4b65f257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110279018638885566638632205024397244652543533481750952218178355763257148955896 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.kmac_burst_write.110279018638885566638632205024397244652543533481750952218178355763257148955896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.85418494334482191289885512097690031194331892070049468937015104685973971301160
Short name T63
Test name
Test status
Simulation time 62261174 ps
CPU time 1.24 seconds
Started Nov 22 02:01:38 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 219100 kb
Host smart-f0b830bd-8708-45e2-bea9-979ed0d3a256
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85418494334482191289885512097690031194331892070049468937015104685973971301160 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.kmac_edn_timeout_error.85418494334482191289885512097690031194331892070049468937015104685973971301160 +enable_masking=1
+sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.36636106247729100315356627863675801534195460486673996519655606371377330660031
Short name T227
Test name
Test status
Simulation time 64850439 ps
CPU time 1.24 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:01:20 PM PST 23
Peak memory 218888 kb
Host smart-4098b3af-cf00-48d5-9ce2-2077d3b8deb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=36636106247729100315356627863675801534195460486673996519655606371377330660031 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.36636106247729100315356627863675801534195460486673996519655606371377330660031 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.90960083055150337709665661056894336330835422772178770603968699487048630809699
Short name T387
Test name
Test status
Simulation time 7238810904 ps
CPU time 108.34 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:18 PM PST 23
Peak memory 243708 kb
Host smart-3391ec64-545f-45ca-a257-498b86b40252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90960083055150337709665661056894336330835422772178770603968699487048630809699 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.kmac_entropy_refresh.90960083055150337709665661056894336330835422772178770603968699487048630809699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.96085735897529810461127076610438870589027369969974260539092555425521933904757
Short name T336
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.1 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 252764 kb
Host smart-71f0cb45-c4f9-48a6-956e-50fa82421e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96085735897529810461127076610438870589027369969974260539092555425521933904757 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.kmac_error.96085735897529810461127076610438870589027369969974260539092555425521933904757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.17654872830180227516903761868833769012405027220148583172842736007962147958989
Short name T384
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.63 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 219204 kb
Host smart-8f0a7345-0ab0-4e6b-8cd6-7f32a72bbb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17654872830180227516903761868833769012405027220148583172842736007962147958989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.kmac_key_error.17654872830180227516903761868833769012405027220148583172842736007962147958989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.18728080017850803893355733366257254611986039617145071166272231813839619673296
Short name T718
Test name
Test status
Simulation time 72761090 ps
CPU time 1.49 seconds
Started Nov 22 02:02:04 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 220424 kb
Host smart-b5a3b42a-970e-4e6d-b7f9-163977173d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18728080017850803893355733366257254611986039617145071166272231813839619673296 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.kmac_lc_escalation.18728080017850803893355733366257254611986039617145071166272231813839619673296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.67786910302769786334345676621150732847719163994973911785190106537318437955790
Short name T402
Test name
Test status
Simulation time 50513696845 ps
CPU time 1021.25 seconds
Started Nov 22 02:02:04 PM PST 23
Finished Nov 22 02:19:25 PM PST 23
Peak memory 306340 kb
Host smart-ef0a0d8c-298c-4005-801f-2ec6cc4f9ebf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67786910302769786334345676621150732847719163994973911785190106537318437955790 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.677869103027697863343456766211507328477191639949739117851901065373184
37955790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.25025515804510769639013422074195900087965293897466275956727358253338026164727
Short name T186
Test name
Test status
Simulation time 7628111361 ps
CPU time 143.94 seconds
Started Nov 22 02:02:07 PM PST 23
Finished Nov 22 02:04:48 PM PST 23
Peak memory 236396 kb
Host smart-16478bdc-31c1-4115-8f33-62a9424f4860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25025515804510769639013422074195900087965293897466275956727358253338026164727 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.kmac_sideload.25025515804510769639013422074195900087965293897466275956727358253338026164727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.96217910321403861350347273192543870550004053039932029223435384116377559669419
Short name T503
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.36 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:58 PM PST 23
Peak memory 225260 kb
Host smart-0db2dde3-a53a-46e5-84d4-46399b4d8d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96217910321403861350347273192543870550004053039932029223435384116377559669419 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.kmac_smoke.96217910321403861350347273192543870550004053039932029223435384116377559669419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.19553517715274146721907311283219293684818095992181309640467434122243378792477
Short name T779
Test name
Test status
Simulation time 47207151869 ps
CPU time 854.94 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:15:46 PM PST 23
Peak memory 339776 kb
Host smart-1c55e99a-2c20-4953-8097-6160940c570a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=19553517715274146721907311283219293684818095992181309640467434122243378792477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_st
ress_all.19553517715274146721907311283219293684818095992181309640467434122243378792477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.45981243961701358864425161788611693487153180539186524088315198994678529289615
Short name T455
Test name
Test status
Simulation time 322955517 ps
CPU time 5.8 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 219264 kb
Host smart-e2e804bc-62f0-4cbe-89a9-e0fcef2394ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45981243961701358864425161788611693487153180539186524
088315198994678529289615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac.45981243961701358864425161788611693487
153180539186524088315198994678529289615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.36193290299739037950749910442637821289740602516413697572366063068912188676096
Short name T987
Test name
Test status
Simulation time 309259198 ps
CPU time 5.46 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:33 PM PST 23
Peak memory 219236 kb
Host smart-b03b554e-dc46-4b45-959d-813240106ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193290299739037950749910442637821289740602516413697
572366063068912188676096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.361932902997390379507499104426
37821289740602516413697572366063068912188676096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.8395018938682712212371241930708930201331516946685944737641192186708077838928
Short name T764
Test name
Test status
Simulation time 117329894454 ps
CPU time 2052.5 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:36:42 PM PST 23
Peak memory 400580 kb
Host smart-f40221a5-8eb0-4d6e-b273-ac2e839d7cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8395018938682712212371241930708930201331516946685944737641192186708077838928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
kmac_test_vectors_sha3_224.8395018938682712212371241930708930201331516946685944737641192186708077838928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.36373247844661860017706562194207572529281493326538844544505500373969478701444
Short name T142
Test name
Test status
Simulation time 106843317633 ps
CPU time 1881.3 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:33:49 PM PST 23
Peak memory 376424 kb
Host smart-37c51b7c-fb8d-42e2-aa40-cfdcd18117a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=36373247844661860017706562194207572529281493326538844544505500373969478701444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_256.36373247844661860017706562194207572529281493326538844544505500373969478701444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.55956579483894749459490279470920047575332074190339522839002649696742442333672
Short name T620
Test name
Test status
Simulation time 83520343504 ps
CPU time 1610 seconds
Started Nov 22 02:02:21 PM PST 23
Finished Nov 22 02:29:17 PM PST 23
Peak memory 338468 kb
Host smart-be9df1cc-66a7-4a3f-b142-8f6c1e694d96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55956579483894749459490279470920047575332074190339522839002649696742442333672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_384.55956579483894749459490279470920047575332074190339522839002649696742442333672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.80312200110679550998871736338282927167057411731986382172116561743414320103510
Short name T529
Test name
Test status
Simulation time 57499426673 ps
CPU time 1118.94 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 297784 kb
Host smart-14a6e795-ea91-44c5-b250-bc99ec8a44d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=80312200110679550998871736338282927167057411731986382172116561743414320103510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_512.80312200110679550998871736338282927167057411731986382172116561743414320103510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.23566250042603459955344518866903499591378036241223487736814954855192372738420
Short name T151
Test name
Test status
Simulation time 320694338954 ps
CPU time 5133.48 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 03:28:21 PM PST 23
Peak memory 674212 kb
Host smart-1a082d5b-edab-4f4b-9efa-4718c20899a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=23566250042603459955344518866903499591378036241223487736814954855192372738420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.kmac_test_vectors_shake_128.23566250042603459955344518866903499591378036241223487736814954855192372738420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.64515314524167366340486336056779236400243174744408498387732995456465388872867
Short name T557
Test name
Test status
Simulation time 270085708112 ps
CPU time 4521.54 seconds
Started Nov 22 02:02:31 PM PST 23
Finished Nov 22 03:17:59 PM PST 23
Peak memory 577412 kb
Host smart-a27ff2fd-bf9f-43cb-9c6c-a6f6f3834ddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=64515314524167366340486336056779236400243174744408498387732995456465388872867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.kmac_test_vectors_shake_256.64515314524167366340486336056779236400243174744408498387732995456465388872867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.54634108178180237903479101059483013433341023456495116980635169660676946829843
Short name T268
Test name
Test status
Simulation time 21118646 ps
CPU time 0.82 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:47 PM PST 23
Peak memory 218968 kb
Host smart-6c51a806-eaf3-490a-b2cc-9da07f4fa9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54634108178180237903479101059483013433341023456495116980635169660676946829843 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.kmac_alert_test.54634108178180237903479101059483013433341023456495116980635169660676946829843 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.14607858353827767740145499644705279323939889354773598190566524972054762024172
Short name T143
Test name
Test status
Simulation time 6076748772 ps
CPU time 93.69 seconds
Started Nov 22 02:01:51 PM PST 23
Finished Nov 22 02:03:25 PM PST 23
Peak memory 236208 kb
Host smart-5eb66c65-de29-476a-ae0f-e055166e137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14607858353827767740145499644705279323939889354773598190566524972054762024172 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.kmac_app.14607858353827767740145499644705279323939889354773598190566524972054762024172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.3644786414526874857554591040725513665870637156785790202420388674944653000480
Short name T982
Test name
Test status
Simulation time 14830000174 ps
CPU time 394.15 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:08:08 PM PST 23
Peak memory 243252 kb
Host smart-25c0a483-5e1f-4ff7-860b-f488591f270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644786414526874857554591040725513665870637156785790202420388674944653000480 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.kmac_burst_write.3644786414526874857554591040725513665870637156785790202420388674944653000480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.52216698639143737191088422924567819004263673648898635747356663217737767386429
Short name T543
Test name
Test status
Simulation time 62261174 ps
CPU time 1.23 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:36 PM PST 23
Peak memory 219128 kb
Host smart-4e1932ad-e61a-461d-8c85-8563de919754
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52216698639143737191088422924567819004263673648898635747356663217737767386429 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.kmac_edn_timeout_error.52216698639143737191088422924567819004263673648898635747356663217737767386429 +enable_masking=1
+sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.72958400453826390695490441653691209069788248698221181436655252966643789159388
Short name T986
Test name
Test status
Simulation time 64850439 ps
CPU time 1.35 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:33 PM PST 23
Peak memory 218780 kb
Host smart-e88a42e1-5beb-4300-9d67-ec72de08ef56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72958400453826390695490441653691209069788248698221181436655252966643789159388 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.72958400453826390695490441653691209069788248698221181436655252966643789159388 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.101031816748881941401249350801779831025754618662381952361653513731732626001495
Short name T761
Test name
Test status
Simulation time 7238810904 ps
CPU time 110.67 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:04:25 PM PST 23
Peak memory 243948 kb
Host smart-793211af-f628-48d0-9888-6f32e4baf12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101031816748881941401249350801779831025754618662381952361653513731732626001495 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.kmac_entropy_refresh.101031816748881941401249350801779831025754618662381952361653513731732626001495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.99722970024800261612892501580082748938638363600059657622975622671269146788371
Short name T726
Test name
Test status
Simulation time 8137821569 ps
CPU time 141.79 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:04:58 PM PST 23
Peak memory 252688 kb
Host smart-d87e3844-5af4-4726-8291-c91bfeca07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99722970024800261612892501580082748938638363600059657622975622671269146788371 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.kmac_error.99722970024800261612892501580082748938638363600059657622975622671269146788371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.65269844129455756038603725831696216351036352480595218246184937757411513070572
Short name T79
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.64 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:33 PM PST 23
Peak memory 219252 kb
Host smart-56d100d2-2973-4465-9e96-54fbad5c2052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65269844129455756038603725831696216351036352480595218246184937757411513070572 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.kmac_key_error.65269844129455756038603725831696216351036352480595218246184937757411513070572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.59480803360113830937991992113512741142851804932717711679251681879361703401416
Short name T678
Test name
Test status
Simulation time 72761090 ps
CPU time 1.44 seconds
Started Nov 22 02:02:29 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 220512 kb
Host smart-4fbc7392-fe87-4964-bf1a-c7e61b59424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59480803360113830937991992113512741142851804932717711679251681879361703401416 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.kmac_lc_escalation.59480803360113830937991992113512741142851804932717711679251681879361703401416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.93618674075722400772351866077595369721190732554311214981906064569169276612807
Short name T207
Test name
Test status
Simulation time 50513696845 ps
CPU time 982.12 seconds
Started Nov 22 02:01:39 PM PST 23
Finished Nov 22 02:18:03 PM PST 23
Peak memory 306340 kb
Host smart-6dfb0ac0-ada7-4810-a727-8ca5917647cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93618674075722400772351866077595369721190732554311214981906064569169276612807 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.936186740757224007723518660775953697211907325543112149819060645691692
76612807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.99454152474661942975974081393636856924982645323234322254176794498458677242722
Short name T544
Test name
Test status
Simulation time 7628111361 ps
CPU time 134.03 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:03:48 PM PST 23
Peak memory 236396 kb
Host smart-069ad314-a5f1-491e-98d8-95941a9fff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99454152474661942975974081393636856924982645323234322254176794498458677242722 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.kmac_sideload.99454152474661942975974081393636856924982645323234322254176794498458677242722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.83802578044350264221288717895182786047003549747685916080672183485334578278198
Short name T1055
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.58 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:01:48 PM PST 23
Peak memory 225328 kb
Host smart-04b08fa5-34ef-4298-8f32-747fee8c04f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83802578044350264221288717895182786047003549747685916080672183485334578278198 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.kmac_smoke.83802578044350264221288717895182786047003549747685916080672183485334578278198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.29726308801723818717312168129626201735077765268619595836618179936327167583606
Short name T38
Test name
Test status
Simulation time 47207151869 ps
CPU time 867.82 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:16:05 PM PST 23
Peak memory 339836 kb
Host smart-4b12ee79-d3b5-4e75-b653-129440e34df9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=29726308801723818717312168129626201735077765268619595836618179936327167583606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_st
ress_all.29726308801723818717312168129626201735077765268619595836618179936327167583606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.20569022265098936807845734713579410632138024505340961309902141815624118849656
Short name T728
Test name
Test status
Simulation time 322955517 ps
CPU time 5.39 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 219332 kb
Host smart-f6037c75-bf30-41f6-afed-39669f653600
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569022265098936807845734713579410632138024505340961
309902141815624118849656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac.20569022265098936807845734713579410632
138024505340961309902141815624118849656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.49477170988328751223222402757457846579640360100122685542884052761391614135851
Short name T202
Test name
Test status
Simulation time 309259198 ps
CPU time 5.59 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 219236 kb
Host smart-7c4cd0ec-a2e8-4ebd-8cb2-ad20a6ab248c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49477170988328751223222402757457846579640360100122685
542884052761391614135851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.494771709883287512232224027574
57846579640360100122685542884052761391614135851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.83133282147035623017750913432728937231842559445577594885076374960990938772542
Short name T1041
Test name
Test status
Simulation time 117329894454 ps
CPU time 2164.9 seconds
Started Nov 22 02:01:20 PM PST 23
Finished Nov 22 02:37:26 PM PST 23
Peak memory 400816 kb
Host smart-c9d37108-f003-485f-af16-a230fd5344b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83133282147035623017750913432728937231842559445577594885076374960990938772542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_224.83133282147035623017750913432728937231842559445577594885076374960990938772542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.20310758968070968678444313266118114346297910614521707011663661220828901836983
Short name T321
Test name
Test status
Simulation time 106843317633 ps
CPU time 1875.17 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:32:47 PM PST 23
Peak memory 376404 kb
Host smart-6a71f024-6214-46bd-886a-0196a16ade75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20310758968070968678444313266118114346297910614521707011663661220828901836983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_256.20310758968070968678444313266118114346297910614521707011663661220828901836983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.80272810673201387781769873862850852065340216505538269736170208829024701887305
Short name T331
Test name
Test status
Simulation time 83520343504 ps
CPU time 1635.97 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:28:49 PM PST 23
Peak memory 338436 kb
Host smart-c7c2290c-73f3-474a-9529-e19795d4414b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=80272810673201387781769873862850852065340216505538269736170208829024701887305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_384.80272810673201387781769873862850852065340216505538269736170208829024701887305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.71816735103802963454346693038248552227730428034461338858523182042960707972876
Short name T1023
Test name
Test status
Simulation time 57499426673 ps
CPU time 1165.92 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 297808 kb
Host smart-41ea9b5d-68b1-44d8-9696-694b9c529ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=71816735103802963454346693038248552227730428034461338858523182042960707972876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_512.71816735103802963454346693038248552227730428034461338858523182042960707972876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.89253502170963833810219973085524941617414050325685629166919295051712137953157
Short name T293
Test name
Test status
Simulation time 320694338954 ps
CPU time 5361.08 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 03:30:55 PM PST 23
Peak memory 674308 kb
Host smart-5898a796-8b98-40a9-8c2e-d1f323034af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=89253502170963833810219973085524941617414050325685629166919295051712137953157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.kmac_test_vectors_shake_128.89253502170963833810219973085524941617414050325685629166919295051712137953157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3317127653584368947736727518723910564104550614551825291204683358940861229146
Short name T535
Test name
Test status
Simulation time 270085708112 ps
CPU time 4601.54 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 03:18:02 PM PST 23
Peak memory 577200 kb
Host smart-f00c4f6b-751a-4ffd-9357-8d4293f79470
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3317127653584368947736727518723910564104550614551825291204683358940861229146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.kmac_test_vectors_shake_256.3317127653584368947736727518723910564104550614551825291204683358940861229146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.50119376283121600912449009244356275570083087342473792961733366325972696761383
Short name T222
Test name
Test status
Simulation time 21118646 ps
CPU time 0.83 seconds
Started Nov 22 02:02:05 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 218952 kb
Host smart-b705f7d8-068d-48fa-ae8e-1256fef40375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50119376283121600912449009244356275570083087342473792961733366325972696761383 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.kmac_alert_test.50119376283121600912449009244356275570083087342473792961733366325972696761383 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.35702613746683752624810326845799655177419960237635952531629139319351982741282
Short name T230
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.84 seconds
Started Nov 22 02:01:39 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 236252 kb
Host smart-e98e604b-48e2-412e-8d68-f7f5aaa99515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35702613746683752624810326845799655177419960237635952531629139319351982741282 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_app.35702613746683752624810326845799655177419960237635952531629139319351982741282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.88067727230086190421522520157493092031417321800497320009973681907607064895493
Short name T160
Test name
Test status
Simulation time 14830000174 ps
CPU time 386.71 seconds
Started Nov 22 02:02:31 PM PST 23
Finished Nov 22 02:09:04 PM PST 23
Peak memory 243196 kb
Host smart-9fffece1-dd4d-4eca-a37f-ff0010bbee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88067727230086190421522520157493092031417321800497320009973681907607064895493 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.kmac_burst_write.88067727230086190421522520157493092031417321800497320009973681907607064895493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.27170457281552226779128212838096157450588196556338743689968176746788858442778
Short name T638
Test name
Test status
Simulation time 62261174 ps
CPU time 1.32 seconds
Started Nov 22 02:02:01 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 219088 kb
Host smart-7118ebf7-9d29-42e5-839a-d74ffeaa08f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=27170457281552226779128212838096157450588196556338743689968176746788858442778 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.kmac_edn_timeout_error.27170457281552226779128212838096157450588196556338743689968176746788858442778 +enable_masking=1
+sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.55804624693663986088626767682915816115752951817949749042801915976579918146323
Short name T1016
Test name
Test status
Simulation time 64850439 ps
CPU time 1.31 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 219076 kb
Host smart-c9b1919b-a930-4334-9836-74ab620336e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55804624693663986088626767682915816115752951817949749042801915976579918146323 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.55804624693663986088626767682915816115752951817949749042801915976579918146323 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.37549903440271233144529777056640433918628349301333978088765711900309212267440
Short name T478
Test name
Test status
Simulation time 7238810904 ps
CPU time 103 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:03:17 PM PST 23
Peak memory 243856 kb
Host smart-590ed2a2-b77b-450e-9aba-c06cb8fc84b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37549903440271233144529777056640433918628349301333978088765711900309212267440 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.kmac_entropy_refresh.37549903440271233144529777056640433918628349301333978088765711900309212267440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.423912163872113901141341948322718435232897219454524899157902904684214852312
Short name T389
Test name
Test status
Simulation time 8137821569 ps
CPU time 152.82 seconds
Started Nov 22 02:01:39 PM PST 23
Finished Nov 22 02:04:13 PM PST 23
Peak memory 252776 kb
Host smart-44b84591-4bf4-4ffd-9cb4-d72850237e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423912163872113901141341948322718435232897219454524899157902904684214852312 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_error.423912163872113901141341948322718435232897219454524899157902904684214852312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.111516027881799153792000241287657041419877813610755234156059040495170751209180
Short name T972
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.76 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 219120 kb
Host smart-737d2799-8d7f-461c-8413-75cc2603a902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111516027881799153792000241287657041419877813610755234156059040495170751209180 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.kmac_key_error.111516027881799153792000241287657041419877813610755234156059040495170751209180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.102503009686944706806496530255391504947545373974157471824153889997900460746993
Short name T167
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 220480 kb
Host smart-369eeb8b-3453-4194-88b6-115d642399bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102503009686944706806496530255391504947545373974157471824153889997900460746993 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.kmac_lc_escalation.102503009686944706806496530255391504947545373974157471824153889997900460746993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.74141408327329357971925288771860101704889329473934666487039759769284018250759
Short name T188
Test name
Test status
Simulation time 50513696845 ps
CPU time 937.81 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:18:28 PM PST 23
Peak memory 306268 kb
Host smart-14a69586-6c46-42f2-bbb0-cb26b0c481f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74141408327329357971925288771860101704889329473934666487039759769284018250759 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.741414083273293579719252887718601017048893294739346664870397597692840
18250759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.14804010433383659381311404562156945251988596008918535862971878972579797183581
Short name T908
Test name
Test status
Simulation time 7628111361 ps
CPU time 141.12 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:04:58 PM PST 23
Peak memory 236340 kb
Host smart-7d4a923b-ea91-40b9-b41d-90996d4cb891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14804010433383659381311404562156945251988596008918535862971878972579797183581 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.kmac_sideload.14804010433383659381311404562156945251988596008918535862971878972579797183581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.95887057666742996682356127577200979710236486992454837813491952539583365764013
Short name T244
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.08 seconds
Started Nov 22 02:02:31 PM PST 23
Finished Nov 22 02:03:03 PM PST 23
Peak memory 225332 kb
Host smart-a21a4e51-7831-4c32-a84b-5934c63bd3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95887057666742996682356127577200979710236486992454837813491952539583365764013 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.kmac_smoke.95887057666742996682356127577200979710236486992454837813491952539583365764013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.91354830224925560961562025325861885371340918969762806966563089730562896417674
Short name T459
Test name
Test status
Simulation time 47207151869 ps
CPU time 857.77 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:16:53 PM PST 23
Peak memory 339828 kb
Host smart-1360b213-ecb5-478f-96bc-e551d1cab26c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=91354830224925560961562025325861885371340918969762806966563089730562896417674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_st
ress_all.91354830224925560961562025325861885371340918969762806966563089730562896417674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.59650124209248040460054206153143336613443903669584319306889044999166392301936
Short name T751
Test name
Test status
Simulation time 322955517 ps
CPU time 5.87 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:01:43 PM PST 23
Peak memory 219188 kb
Host smart-8a29e0c5-47dc-420a-b065-3db45deb68b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59650124209248040460054206153143336613443903669584319
306889044999166392301936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac.59650124209248040460054206153143336613
443903669584319306889044999166392301936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.71107275366089834162778312933121155206562875845541412324812532354937929007657
Short name T602
Test name
Test status
Simulation time 309259198 ps
CPU time 5.5 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 219192 kb
Host smart-7707b100-391c-40ab-8828-80cf8bc6f989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71107275366089834162778312933121155206562875845541412
324812532354937929007657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.711072753660898341627783129331
21155206562875845541412324812532354937929007657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.28384671128720214951175678133262565726074297949900062451574870666786681474541
Short name T291
Test name
Test status
Simulation time 117329894454 ps
CPU time 2073.09 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:36:09 PM PST 23
Peak memory 400752 kb
Host smart-d119227e-acac-4c9a-8261-998a61d24da1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=28384671128720214951175678133262565726074297949900062451574870666786681474541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_224.28384671128720214951175678133262565726074297949900062451574870666786681474541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.3041116296617820249445959895007622177210196791829545145060594413827473886898
Short name T232
Test name
Test status
Simulation time 106843317633 ps
CPU time 1887.96 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:33:56 PM PST 23
Peak memory 376408 kb
Host smart-4993843c-c90a-4578-8087-024e4fa3bfb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3041116296617820249445959895007622177210196791829545145060594413827473886898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
kmac_test_vectors_sha3_256.3041116296617820249445959895007622177210196791829545145060594413827473886898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.40970344009499143847076529342474123072860136146262911871087745977627234965136
Short name T324
Test name
Test status
Simulation time 83520343504 ps
CPU time 1546.06 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:27:19 PM PST 23
Peak memory 338468 kb
Host smart-09b2f493-ed97-49da-86d4-41c0590959be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=40970344009499143847076529342474123072860136146262911871087745977627234965136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_384.40970344009499143847076529342474123072860136146262911871087745977627234965136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.60904760365184667208820689919126014594302093847663567295147718698041351237255
Short name T1038
Test name
Test status
Simulation time 57499426673 ps
CPU time 1099.92 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:20:52 PM PST 23
Peak memory 297748 kb
Host smart-a0ba6a06-839a-4775-9fa8-f3d32b399e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=60904760365184667208820689919126014594302093847663567295147718698041351237255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_512.60904760365184667208820689919126014594302093847663567295147718698041351237255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.46188418821469474572655758700113007900943339645001915473522564732571409832981
Short name T158
Test name
Test status
Simulation time 320694338954 ps
CPU time 5384.25 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 03:31:22 PM PST 23
Peak memory 674284 kb
Host smart-c38c8eac-aabe-480f-97eb-3b40561d4499
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=46188418821469474572655758700113007900943339645001915473522564732571409832981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_test_vectors_shake_128.46188418821469474572655758700113007900943339645001915473522564732571409832981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.13817490207736165292891373944869882965061332466375299104998910456705634825067
Short name T183
Test name
Test status
Simulation time 270085708112 ps
CPU time 4610.32 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 03:18:28 PM PST 23
Peak memory 577392 kb
Host smart-27619bae-f684-4d0c-b772-9f427e6b5072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=13817490207736165292891373944869882965061332466375299104998910456705634825067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_test_vectors_shake_256.13817490207736165292891373944869882965061332466375299104998910456705634825067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.64262870451826710446136810393236449601423259147773553178689809574839696432962
Short name T176
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219048 kb
Host smart-bb12ea70-0748-4255-9c3a-8ee5c7ef3b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64262870451826710446136810393236449601423259147773553178689809574839696432962 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.kmac_alert_test.64262870451826710446136810393236449601423259147773553178689809574839696432962 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.9094843488397499217660260873478979304521428400290173529461891388789601855235
Short name T621
Test name
Test status
Simulation time 6076748772 ps
CPU time 101.1 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:04:10 PM PST 23
Peak memory 236216 kb
Host smart-b041afad-0372-443c-8410-36785adb6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9094843488397499217660260873478979304521428400290173529461891388789601855235 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_app.9094843488397499217660260873478979304521428400290173529461891388789601855235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.91979415596130917426357145825155086199650533492329002996225534028034410714921
Short name T360
Test name
Test status
Simulation time 14830000174 ps
CPU time 397.2 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:09:11 PM PST 23
Peak memory 243208 kb
Host smart-2a66cd7d-dab7-4296-b4b5-ffd6b8226f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91979415596130917426357145825155086199650533492329002996225534028034410714921 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.kmac_burst_write.91979415596130917426357145825155086199650533492329002996225534028034410714921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.54555438145538364423729310613640589897735818041279805443710868849056105225608
Short name T465
Test name
Test status
Simulation time 62261174 ps
CPU time 1.3 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:29 PM PST 23
Peak memory 219100 kb
Host smart-e1a9cc0d-9bef-43f1-9c79-c6c3bd5e9e1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=54555438145538364423729310613640589897735818041279805443710868849056105225608 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.kmac_edn_timeout_error.54555438145538364423729310613640589897735818041279805443710868849056105225608 +enable_masking=1
+sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.3819527659295697602048462145187264719198096079781413683394714779902273471953
Short name T362
Test name
Test status
Simulation time 64850439 ps
CPU time 1.25 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:33 PM PST 23
Peak memory 219080 kb
Host smart-cd538ca1-d95a-49e6-a5db-8e36545ab209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819527659295697602048462145187264719198096079781413683394714779902273471953 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.kmac_entropy_mode_error.3819527659295697602048462145187264719198096079781413683394714779902273471953 +enable_masking=1
+sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.113775684924018069163029202691555654250025201979170110418794087960192121276389
Short name T563
Test name
Test status
Simulation time 7238810904 ps
CPU time 112.2 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:22 PM PST 23
Peak memory 243812 kb
Host smart-4413ce6c-1db0-4f12-ab7c-c9608ba31280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113775684924018069163029202691555654250025201979170110418794087960192121276389 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.kmac_entropy_refresh.113775684924018069163029202691555654250025201979170110418794087960192121276389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.33930922948119559295267287464014168687602213164674872581987735679827398338359
Short name T1017
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.09 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:57 PM PST 23
Peak memory 252764 kb
Host smart-5f568634-73fe-4482-9c92-ab240cc9324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33930922948119559295267287464014168687602213164674872581987735679827398338359 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.kmac_error.33930922948119559295267287464014168687602213164674872581987735679827398338359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.40349351830682097004569362619740600688243352216728179813593920542896588911449
Short name T404
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.7 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:02:42 PM PST 23
Peak memory 219132 kb
Host smart-a123fdd1-afc6-4b17-86c5-7217462a2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40349351830682097004569362619740600688243352216728179813593920542896588911449 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.kmac_key_error.40349351830682097004569362619740600688243352216728179813593920542896588911449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.71642533106748119510865193695549080729278618694583989567506616740272538346989
Short name T716
Test name
Test status
Simulation time 72761090 ps
CPU time 1.43 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 220428 kb
Host smart-c78ea0a6-0f96-4223-b34c-d390902b66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71642533106748119510865193695549080729278618694583989567506616740272538346989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.kmac_lc_escalation.71642533106748119510865193695549080729278618694583989567506616740272538346989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.89048498169546987800279375528982100839818233766962596793397917053053778347843
Short name T692
Test name
Test status
Simulation time 50513696845 ps
CPU time 977.37 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 02:18:02 PM PST 23
Peak memory 305676 kb
Host smart-a6adcedd-a312-407d-8cbd-5da228810389
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89048498169546987800279375528982100839818233766962596793397917053053778347843 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.890484981695469878002793755289821008398182337669625967933979170530537
78347843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.87091575403598611910697758833256312258245197639493904105077449633261359914042
Short name T760
Test name
Test status
Simulation time 7628111361 ps
CPU time 143.17 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 236332 kb
Host smart-fae42377-f06f-462c-8f9e-64b9247941ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87091575403598611910697758833256312258245197639493904105077449633261359914042 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.kmac_sideload.87091575403598611910697758833256312258245197639493904105077449633261359914042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.34176115027099941339111030742619460453645552529036089354577329159144968231755
Short name T327
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.91 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:03:01 PM PST 23
Peak memory 225340 kb
Host smart-b0de5faa-a6ce-4de5-8a5c-fa6bc8402610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34176115027099941339111030742619460453645552529036089354577329159144968231755 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.kmac_smoke.34176115027099941339111030742619460453645552529036089354577329159144968231755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.42971066231418216892677725927470892910993795607918493133104883972907407530110
Short name T628
Test name
Test status
Simulation time 47207151869 ps
CPU time 892.23 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:17:29 PM PST 23
Peak memory 339764 kb
Host smart-ae9376d7-8b78-4cf2-bf19-781ad318e8ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=42971066231418216892677725927470892910993795607918493133104883972907407530110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_st
ress_all.42971066231418216892677725927470892910993795607918493133104883972907407530110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.15838399533936992661787069861808330893874864761274101821478888038589665152557
Short name T283
Test name
Test status
Simulation time 322955517 ps
CPU time 6.33 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:53 PM PST 23
Peak memory 219204 kb
Host smart-099d6b13-376f-40a3-bfc4-5bfba62f380c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15838399533936992661787069861808330893874864761274101
821478888038589665152557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac.15838399533936992661787069861808330893
874864761274101821478888038589665152557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.12727133018420044361556264055642565620100219571252864403506900969774636200269
Short name T730
Test name
Test status
Simulation time 309259198 ps
CPU time 5.67 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 219264 kb
Host smart-d0b8b3e1-d169-4c8d-8dd8-12b3c4848424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727133018420044361556264055642565620100219571252864
403506900969774636200269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.127271330184200443615562640556
42565620100219571252864403506900969774636200269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.66352432871697250829607293451391043128457257118349359285581584581357599783374
Short name T1024
Test name
Test status
Simulation time 117329894454 ps
CPU time 2098.29 seconds
Started Nov 22 02:02:05 PM PST 23
Finished Nov 22 02:37:23 PM PST 23
Peak memory 400852 kb
Host smart-fc17a435-52bb-48bd-a77e-dc6d9508db6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=66352432871697250829607293451391043128457257118349359285581584581357599783374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_224.66352432871697250829607293451391043128457257118349359285581584581357599783374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.78449675630435926326970770637894593953163930542325075063540566237653522955878
Short name T492
Test name
Test status
Simulation time 106843317633 ps
CPU time 1961.97 seconds
Started Nov 22 02:02:29 PM PST 23
Finished Nov 22 02:35:18 PM PST 23
Peak memory 376396 kb
Host smart-ff79989f-05d9-44c0-a663-bf4c878b9dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=78449675630435926326970770637894593953163930542325075063540566237653522955878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_256.78449675630435926326970770637894593953163930542325075063540566237653522955878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.12700502928424202350306499195858526945575143524896970558460822369823197437928
Short name T338
Test name
Test status
Simulation time 83520343504 ps
CPU time 1493.34 seconds
Started Nov 22 02:02:29 PM PST 23
Finished Nov 22 02:27:30 PM PST 23
Peak memory 338436 kb
Host smart-b9664144-f1f1-44aa-a2c3-7a9e829ec9e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=12700502928424202350306499195858526945575143524896970558460822369823197437928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_384.12700502928424202350306499195858526945575143524896970558460822369823197437928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.86702368152932002953179554094541143707172544787191648227071755192086963466946
Short name T615
Test name
Test status
Simulation time 57499426673 ps
CPU time 1194.86 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:22:25 PM PST 23
Peak memory 297752 kb
Host smart-52e69fda-6b43-47c1-a1ea-4a1e4934713f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86702368152932002953179554094541143707172544787191648227071755192086963466946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_512.86702368152932002953179554094541143707172544787191648227071755192086963466946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.114415057877091905295641599154957718840018771565097270107828621857927136058055
Short name T901
Test name
Test status
Simulation time 320694338954 ps
CPU time 5375.53 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 03:32:09 PM PST 23
Peak memory 672932 kb
Host smart-6695326f-3bbe-40cd-94ef-8781978fd4fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=114415057877091905295641599154957718840018771565097270107828621857927136058055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_test_vectors_shake_128.114415057877091905295641599154957718840018771565097270107828621857927136058055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.30853395061923072746126146710948952500797700554108264349821547268211204441942
Short name T1059
Test name
Test status
Simulation time 270085708112 ps
CPU time 4579.32 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 03:18:54 PM PST 23
Peak memory 577400 kb
Host smart-be5be768-b3ac-4458-bb73-3e558061c34a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=30853395061923072746126146710948952500797700554108264349821547268211204441942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_test_vectors_shake_256.30853395061923072746126146710948952500797700554108264349821547268211204441942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.21128639469016530322146836717463630103620350857560740295958885711985904552267
Short name T383
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:01:45 PM PST 23
Finished Nov 22 02:01:48 PM PST 23
Peak memory 219004 kb
Host smart-6774e7c4-8abf-40b9-95ac-ac11332aef35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128639469016530322146836717463630103620350857560740295958885711985904552267 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.kmac_alert_test.21128639469016530322146836717463630103620350857560740295958885711985904552267 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.80762431516341156792228488672678538220170488469292806107905439182021298880987
Short name T425
Test name
Test status
Simulation time 6076748772 ps
CPU time 101.25 seconds
Started Nov 22 02:02:04 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 236104 kb
Host smart-5cf87237-644a-464e-8b85-b88141549fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80762431516341156792228488672678538220170488469292806107905439182021298880987 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_app.80762431516341156792228488672678538220170488469292806107905439182021298880987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.66925661990649941144000424718828152776760356952278232490410778796946967205437
Short name T661
Test name
Test status
Simulation time 14830000174 ps
CPU time 390.31 seconds
Started Nov 22 02:01:41 PM PST 23
Finished Nov 22 02:08:12 PM PST 23
Peak memory 243212 kb
Host smart-9ddd3927-a578-43e2-a814-7c073d6a1110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66925661990649941144000424718828152776760356952278232490410778796946967205437 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.kmac_burst_write.66925661990649941144000424718828152776760356952278232490410778796946967205437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.95095269467742757732228309364314740210855069443961990723839963334698310115096
Short name T967
Test name
Test status
Simulation time 62261174 ps
CPU time 1.24 seconds
Started Nov 22 02:01:40 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 219080 kb
Host smart-c2c8d6be-e2d3-4d04-b161-aa8a7ce360b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=95095269467742757732228309364314740210855069443961990723839963334698310115096 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.kmac_edn_timeout_error.95095269467742757732228309364314740210855069443961990723839963334698310115096 +enable_masking=1
+sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.103309154631747113467778846258206633739540149713842002287466323327083167758669
Short name T493
Test name
Test status
Simulation time 64850439 ps
CPU time 1.27 seconds
Started Nov 22 02:01:59 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 218952 kb
Host smart-a80538ee-ecf4-4882-a54b-8ce35b088aa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103309154631747113467778846258206633739540149713842002287466323327083167758669 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.103309154631747113467778846258206633739540149713842002287466323327083167758669 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.74814631720431692800654510650434054006891735677686693660500325877150187830317
Short name T59
Test name
Test status
Simulation time 7238810904 ps
CPU time 108.76 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:04:24 PM PST 23
Peak memory 243892 kb
Host smart-28bb29b2-4735-42d5-9ea3-8d1fa480f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74814631720431692800654510650434054006891735677686693660500325877150187830317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.kmac_entropy_refresh.74814631720431692800654510650434054006891735677686693660500325877150187830317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_key_error.16942058635416481343977561388109217263845415703254883386001645168814269498726
Short name T304
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.73 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 219260 kb
Host smart-3012c8ed-9540-44a5-8e9d-cde4d429c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16942058635416481343977561388109217263845415703254883386001645168814269498726 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.kmac_key_error.16942058635416481343977561388109217263845415703254883386001645168814269498726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.62058377057278592075906863916929789425243176119871525450549187876313736854629
Short name T545
Test name
Test status
Simulation time 72761090 ps
CPU time 1.44 seconds
Started Nov 22 02:02:01 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 220472 kb
Host smart-842ebae0-11b5-4f21-9ccb-51fff5a326a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62058377057278592075906863916929789425243176119871525450549187876313736854629 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.kmac_lc_escalation.62058377057278592075906863916929789425243176119871525450549187876313736854629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1682332202415232919203296657145720358884354460721356366778224662345582886704
Short name T833
Test name
Test status
Simulation time 50513696845 ps
CPU time 1007.08 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:19:15 PM PST 23
Peak memory 306320 kb
Host smart-32acad44-3001-48f4-a983-e0596314390f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682332202415232919203296657145720358884354460721356366778224662345582886704 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.1682332202415232919203296657145720358884354460721356366778224662345582
886704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.96977189876341044066457211746791957982209360679902513909787575287847396261717
Short name T1006
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.62 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:04:47 PM PST 23
Peak memory 236384 kb
Host smart-f222b49c-af82-4c4c-b48c-59dad7d1b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96977189876341044066457211746791957982209360679902513909787575287847396261717 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.kmac_sideload.96977189876341044066457211746791957982209360679902513909787575287847396261717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.67809851244817000494448717322811297602652919567292933963473392434931288757007
Short name T322
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.75 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 225428 kb
Host smart-7ad79431-95b4-4c14-88ce-a67187dc4235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67809851244817000494448717322811297602652919567292933963473392434931288757007 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.kmac_smoke.67809851244817000494448717322811297602652919567292933963473392434931288757007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.62624914481949606363816928465216695165873955533580347264542492898551711930517
Short name T804
Test name
Test status
Simulation time 47207151869 ps
CPU time 934.77 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:18:11 PM PST 23
Peak memory 339792 kb
Host smart-49b8f9ae-e4ea-4866-8e54-444a2a22d597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62624914481949606363816928465216695165873955533580347264542492898551711930517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_st
ress_all.62624914481949606363816928465216695165873955533580347264542492898551711930517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.51332343297530780791629442668497453584729485501389866361012157986446359801384
Short name T124
Test name
Test status
Simulation time 322955517 ps
CPU time 5.78 seconds
Started Nov 22 02:02:03 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 219064 kb
Host smart-b09f7341-01fe-4296-8a27-dd1feaaf756f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51332343297530780791629442668497453584729485501389866
361012157986446359801384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac.51332343297530780791629442668497453584
729485501389866361012157986446359801384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.28746030163846731292255646286347761082992735065625131901321763763568268261088
Short name T390
Test name
Test status
Simulation time 309259198 ps
CPU time 5.66 seconds
Started Nov 22 02:02:02 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 219144 kb
Host smart-0af9e62c-d4e8-4c38-9cfc-602bff1d156a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28746030163846731292255646286347761082992735065625131
901321763763568268261088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.287460301638467312922556462863
47761082992735065625131901321763763568268261088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.108297433657965408222498594395025423463179424841232735090906837999172196739141
Short name T798
Test name
Test status
Simulation time 117329894454 ps
CPU time 2278.36 seconds
Started Nov 22 02:02:02 PM PST 23
Finished Nov 22 02:40:23 PM PST 23
Peak memory 400880 kb
Host smart-b508c53a-949b-4d4e-a35c-7b63ef66f014
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=108297433657965408222498594395025423463179424841232735090906837999172196739141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.kmac_test_vectors_sha3_224.108297433657965408222498594395025423463179424841232735090906837999172196739141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.45174956151993480069723030908922725117893912611608552894137921328562251611055
Short name T739
Test name
Test status
Simulation time 106843317633 ps
CPU time 1908.1 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:34:16 PM PST 23
Peak memory 376408 kb
Host smart-97972597-9686-4b85-8832-f532534051d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45174956151993480069723030908922725117893912611608552894137921328562251611055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.kmac_test_vectors_sha3_256.45174956151993480069723030908922725117893912611608552894137921328562251611055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.29818726056963404503954232991789062658086292345676834456303963305852292462410
Short name T829
Test name
Test status
Simulation time 83520343504 ps
CPU time 1571.5 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:28:44 PM PST 23
Peak memory 338476 kb
Host smart-fe0132f7-9d4a-45dc-a705-df67e0a09582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=29818726056963404503954232991789062658086292345676834456303963305852292462410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.kmac_test_vectors_sha3_384.29818726056963404503954232991789062658086292345676834456303963305852292462410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.113476310939509414581418150207860679768241678478690857155741084188339117380319
Short name T667
Test name
Test status
Simulation time 57499426673 ps
CPU time 1186.98 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 297740 kb
Host smart-183f7931-72d5-4634-99ac-e679659ee48d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113476310939509414581418150207860679768241678478690857155741084188339117380319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.kmac_test_vectors_sha3_512.113476310939509414581418150207860679768241678478690857155741084188339117380319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.36422780934671982201387950871479701802043924977242017796036613468948664811797
Short name T343
Test name
Test status
Simulation time 320694338954 ps
CPU time 5331.63 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 03:30:37 PM PST 23
Peak memory 674292 kb
Host smart-351bf405-2998-4238-8196-b74b93d4697e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=36422780934671982201387950871479701802043924977242017796036613468948664811797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_test_vectors_shake_128.36422780934671982201387950871479701802043924977242017796036613468948664811797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.108657402678235673764829331537087164372986527092185235911493952599881946636175
Short name T614
Test name
Test status
Simulation time 270085708112 ps
CPU time 4586.65 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 03:18:14 PM PST 23
Peak memory 577420 kb
Host smart-c4d57487-f192-4a9f-b048-95d981a37a10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=108657402678235673764829331537087164372986527092185235911493952599881946636175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_test_vectors_shake_256.108657402678235673764829331537087164372986527092185235911493952599881946636175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.27621422297817454182522628405026925484829091691176330732090880376720193489022
Short name T941
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219008 kb
Host smart-77e501a4-350d-43d4-9c8b-a40950f9f893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27621422297817454182522628405026925484829091691176330732090880376720193489022 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.kmac_alert_test.27621422297817454182522628405026925484829091691176330732090880376720193489022 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.32309112145768977106785584291050851227822704140961620663170160256878223869246
Short name T1073
Test name
Test status
Simulation time 6076748772 ps
CPU time 100.24 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:04:12 PM PST 23
Peak memory 236228 kb
Host smart-1539be99-1660-466b-8779-e5c9600730d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32309112145768977106785584291050851227822704140961620663170160256878223869246 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_app.32309112145768977106785584291050851227822704140961620663170160256878223869246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.96735208498992792877873159033307625161421216368014460250637686956446600364855
Short name T103
Test name
Test status
Simulation time 14830000174 ps
CPU time 388.01 seconds
Started Nov 22 02:02:05 PM PST 23
Finished Nov 22 02:08:52 PM PST 23
Peak memory 243252 kb
Host smart-d24e6e5c-1eee-4de5-8db7-e17d90f37a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96735208498992792877873159033307625161421216368014460250637686956446600364855 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.kmac_burst_write.96735208498992792877873159033307625161421216368014460250637686956446600364855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.69498234375211437771042454664033142077847278370668562246781286609484735255131
Short name T314
Test name
Test status
Simulation time 62261174 ps
CPU time 1.2 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:32 PM PST 23
Peak memory 219012 kb
Host smart-97fd3a06-e13d-4f2e-8303-4e579077f9ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69498234375211437771042454664033142077847278370668562246781286609484735255131 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.kmac_edn_timeout_error.69498234375211437771042454664033142077847278370668562246781286609484735255131 +enable_masking=1
+sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.27040980101570456047235792089935690844666070707210356103593578525116852031052
Short name T578
Test name
Test status
Simulation time 64850439 ps
CPU time 1.28 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:48 PM PST 23
Peak memory 219020 kb
Host smart-d88ac9ae-6f2b-457b-a914-d14fa88fb800
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=27040980101570456047235792089935690844666070707210356103593578525116852031052 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.27040980101570456047235792089935690844666070707210356103593578525116852031052 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.103148457300263459980126360700778150992325260753054384791599092110829245770345
Short name T627
Test name
Test status
Simulation time 7238810904 ps
CPU time 113.18 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 243900 kb
Host smart-516263a0-22ec-4cc2-b0f7-b67c0ecc3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103148457300263459980126360700778150992325260753054384791599092110829245770345 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_entropy_refresh.103148457300263459980126360700778150992325260753054384791599092110829245770345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.105389097711218957088729440396943329703700655543284311700315577347945503027657
Short name T279
Test name
Test status
Simulation time 8137821569 ps
CPU time 143.62 seconds
Started Nov 22 02:02:31 PM PST 23
Finished Nov 22 02:05:01 PM PST 23
Peak memory 252692 kb
Host smart-dc266341-a81e-4766-8809-b76f0ce1c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105389097711218957088729440396943329703700655543284311700315577347945503027657 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 17.kmac_error.105389097711218957088729440396943329703700655543284311700315577347945503027657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.33876297323411168696546528957124763892266446922435799897061630417047980203468
Short name T824
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.76 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:39 PM PST 23
Peak memory 219200 kb
Host smart-39e7746d-7188-48a6-b14e-8d533fab6d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33876297323411168696546528957124763892266446922435799897061630417047980203468 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.kmac_key_error.33876297323411168696546528957124763892266446922435799897061630417047980203468 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.53543539231689385761247965616572834259378244293937326815756778816210746772384
Short name T619
Test name
Test status
Simulation time 72761090 ps
CPU time 1.49 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 220480 kb
Host smart-e64395fa-1616-4e3c-a05e-3e846ffc7f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53543539231689385761247965616572834259378244293937326815756778816210746772384 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.kmac_lc_escalation.53543539231689385761247965616572834259378244293937326815756778816210746772384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.64569304193840722045014805764237714634936012910864778161807737600531067914830
Short name T1036
Test name
Test status
Simulation time 50513696845 ps
CPU time 945.13 seconds
Started Nov 22 02:02:04 PM PST 23
Finished Nov 22 02:18:09 PM PST 23
Peak memory 306296 kb
Host smart-73a30438-ef91-4f7a-9c1e-77f06d151f5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64569304193840722045014805764237714634936012910864778161807737600531067914830 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.645693041938407220450148057642377146349360129108647781618077376005310
67914830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.55583487470665288199467597672545619017268895008863762204908334282453256582179
Short name T863
Test name
Test status
Simulation time 7628111361 ps
CPU time 135.54 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 02:04:01 PM PST 23
Peak memory 236396 kb
Host smart-66be6f2e-f971-484f-9241-0d3a1e7a8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55583487470665288199467597672545619017268895008863762204908334282453256582179 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.kmac_sideload.55583487470665288199467597672545619017268895008863762204908334282453256582179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.43868280016158619234594708191694361316690028750468136882813769345064771421199
Short name T426
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.16 seconds
Started Nov 22 02:02:01 PM PST 23
Finished Nov 22 02:02:51 PM PST 23
Peak memory 225384 kb
Host smart-88b403f9-a1bf-4ecd-80a2-afdc97547109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43868280016158619234594708191694361316690028750468136882813769345064771421199 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.kmac_smoke.43868280016158619234594708191694361316690028750468136882813769345064771421199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.102419776221973630198517774297428222255695957699458575439808833805090313961282
Short name T656
Test name
Test status
Simulation time 47207151869 ps
CPU time 855.55 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 339812 kb
Host smart-bd090413-bc85-4782-aa1f-c8e53aa0e424
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=102419776221973630198517774297428222255695957699458575439808833805090313961282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_s
tress_all.102419776221973630198517774297428222255695957699458575439808833805090313961282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.83944997862090647338358306772477368408863129306604506404440137402329942495117
Short name T635
Test name
Test status
Simulation time 322955517 ps
CPU time 5.53 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:35 PM PST 23
Peak memory 219272 kb
Host smart-51896826-f802-4736-bf9a-e69bfbe34047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83944997862090647338358306772477368408863129306604506
404440137402329942495117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac.83944997862090647338358306772477368408
863129306604506404440137402329942495117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.103000173929828693822748161238801878095422270192324260051386459119142242485385
Short name T807
Test name
Test status
Simulation time 309259198 ps
CPU time 5.71 seconds
Started Nov 22 02:02:03 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 219172 kb
Host smart-3d71abe2-0e22-4013-9f06-078023f725ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10300017392982869382274816123880187809542227019232426
0051386459119142242485385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.10300017392982869382274816123
8801878095422270192324260051386459119142242485385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.66629375494073854309465272064166926246306940501506323174335920879737202559791
Short name T437
Test name
Test status
Simulation time 117329894454 ps
CPU time 2131.12 seconds
Started Nov 22 02:01:45 PM PST 23
Finished Nov 22 02:37:19 PM PST 23
Peak memory 400876 kb
Host smart-13d3e79e-9337-4900-8254-da5faa2348df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=66629375494073854309465272064166926246306940501506323174335920879737202559791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_224.66629375494073854309465272064166926246306940501506323174335920879737202559791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.33517002658706852913231197211817807712451729309960040593409031686433741556200
Short name T622
Test name
Test status
Simulation time 106843317633 ps
CPU time 2004.06 seconds
Started Nov 22 02:02:02 PM PST 23
Finished Nov 22 02:35:48 PM PST 23
Peak memory 376208 kb
Host smart-bb7b9851-5ba4-4f91-b6f4-2cba1e2bc792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=33517002658706852913231197211817807712451729309960040593409031686433741556200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_256.33517002658706852913231197211817807712451729309960040593409031686433741556200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.20488177685924840747619732346244761377145668392354707336487387356866876098128
Short name T289
Test name
Test status
Simulation time 83520343504 ps
CPU time 1559.46 seconds
Started Nov 22 02:02:03 PM PST 23
Finished Nov 22 02:28:24 PM PST 23
Peak memory 338380 kb
Host smart-c4f328fe-f8b1-4467-86b9-93fbe9f713b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20488177685924840747619732346244761377145668392354707336487387356866876098128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_384.20488177685924840747619732346244761377145668392354707336487387356866876098128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.59538922918375937425406927438370077547685796937613460278912418566530588024249
Short name T245
Test name
Test status
Simulation time 57499426673 ps
CPU time 1272.46 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:23:46 PM PST 23
Peak memory 297748 kb
Host smart-48d45570-615f-449e-a263-1dd84a4d1194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59538922918375937425406927438370077547685796937613460278912418566530588024249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_512.59538922918375937425406927438370077547685796937613460278912418566530588024249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.62904065350550924519365178134227587034659996896578826159687141160892436649004
Short name T1025
Test name
Test status
Simulation time 320694338954 ps
CPU time 5387.83 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 03:32:18 PM PST 23
Peak memory 674372 kb
Host smart-9b74aab9-9b89-40cc-8dd6-53131484c028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=62904065350550924519365178134227587034659996896578826159687141160892436649004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_test_vectors_shake_128.62904065350550924519365178134227587034659996896578826159687141160892436649004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.60804407340527114831989626959510070760430957422351019515717477876192281937540
Short name T159
Test name
Test status
Simulation time 270085708112 ps
CPU time 4723.71 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 03:21:20 PM PST 23
Peak memory 577400 kb
Host smart-869c6870-1d18-4cd6-9f7e-6477bfbfbd25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=60804407340527114831989626959510070760430957422351019515717477876192281937540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_test_vectors_shake_256.60804407340527114831989626959510070760430957422351019515717477876192281937540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.82912306488384631425929341478140808115832039929630849939398456021250602155562
Short name T980
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:47 PM PST 23
Peak memory 218972 kb
Host smart-1234397a-eafb-4700-85c8-1283ba58dc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82912306488384631425929341478140808115832039929630849939398456021250602155562 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.kmac_alert_test.82912306488384631425929341478140808115832039929630849939398456021250602155562 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.66267804147024225729915962617277376576497097118449053987636065493320125327709
Short name T604
Test name
Test status
Simulation time 6076748772 ps
CPU time 96.71 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:09 PM PST 23
Peak memory 236264 kb
Host smart-ef3300a5-1df2-4599-8e64-f556d9c34b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66267804147024225729915962617277376576497097118449053987636065493320125327709 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.kmac_app.66267804147024225729915962617277376576497097118449053987636065493320125327709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.54739430994343330580745024056534828470636888835475546262027626714009027437114
Short name T380
Test name
Test status
Simulation time 14830000174 ps
CPU time 376.78 seconds
Started Nov 22 02:02:31 PM PST 23
Finished Nov 22 02:08:53 PM PST 23
Peak memory 243268 kb
Host smart-da9a8a71-da00-4eee-b62d-85709d975f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54739430994343330580745024056534828470636888835475546262027626714009027437114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.kmac_burst_write.54739430994343330580745024056534828470636888835475546262027626714009027437114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.115258753594240825971538867472354040496371997736951281391862162987281682193690
Short name T945
Test name
Test status
Simulation time 62261174 ps
CPU time 1.29 seconds
Started Nov 22 02:02:29 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 219112 kb
Host smart-d60e865b-ace0-460e-b550-0af5e4425e77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=115258753594240825971538867472354040496371997736951281391862162987281682193690 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.115258753594240825971538867472354040496371997736951281391862162987281682193690 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.78367822519772416661271081478428655395819035050295882339854522216096681312474
Short name T842
Test name
Test status
Simulation time 64850439 ps
CPU time 1.22 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 219088 kb
Host smart-f756cf02-7c79-414a-af4e-410e20473d8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78367822519772416661271081478428655395819035050295882339854522216096681312474 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.78367822519772416661271081478428655395819035050295882339854522216096681312474 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.53780297298696026408596717528274197834092827045734597037559782452686613449596
Short name T1010
Test name
Test status
Simulation time 7238810904 ps
CPU time 108.9 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 243900 kb
Host smart-001a38c5-6560-4a8f-b081-913072886195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53780297298696026408596717528274197834092827045734597037559782452686613449596 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.kmac_entropy_refresh.53780297298696026408596717528274197834092827045734597037559782452686613449596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.16949120515960400035491016662060336125259640843761826193407129359235807103098
Short name T788
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.46 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 252724 kb
Host smart-eb4922ac-aaa8-434c-b3f6-6105e1cf8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16949120515960400035491016662060336125259640843761826193407129359235807103098 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.kmac_error.16949120515960400035491016662060336125259640843761826193407129359235807103098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.78169665921452887806553384356760053231953213379414064335115073802921256458889
Short name T463
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.83 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 219184 kb
Host smart-9f6677a8-a21c-4959-b195-7a101e5c294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78169665921452887806553384356760053231953213379414064335115073802921256458889 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.kmac_key_error.78169665921452887806553384356760053231953213379414064335115073802921256458889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.65309553242735127138082836304617045312041179370520244142643641516991568356865
Short name T650
Test name
Test status
Simulation time 50513696845 ps
CPU time 1020.53 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:19:33 PM PST 23
Peak memory 304772 kb
Host smart-8fbe1480-0797-4d53-a0b0-6f7719dea068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65309553242735127138082836304617045312041179370520244142643641516991568356865 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.653095532427351271380828363046170453120411793705202441426436415169915
68356865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.63543773539196658011801339716930203143062094155951910806354943464469310597279
Short name T1048
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.86 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:05:06 PM PST 23
Peak memory 236344 kb
Host smart-19ee7b34-6395-4f79-9d2a-2417998b55d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63543773539196658011801339716930203143062094155951910806354943464469310597279 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.kmac_sideload.63543773539196658011801339716930203143062094155951910806354943464469310597279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.24012220363869561862965653401625883527663086389768462467299608836495084727929
Short name T765
Test name
Test status
Simulation time 1925406983 ps
CPU time 24.9 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:53 PM PST 23
Peak memory 225268 kb
Host smart-de907a80-3e6a-4545-ac3e-4e353ce61b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24012220363869561862965653401625883527663086389768462467299608836495084727929 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.kmac_smoke.24012220363869561862965653401625883527663086389768462467299608836495084727929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.97931321032600695324526385267703640855009291882161556704743957564071292567985
Short name T39
Test name
Test status
Simulation time 47207151869 ps
CPU time 878.56 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:17:14 PM PST 23
Peak memory 339872 kb
Host smart-23b35f57-9054-490e-8c4d-20487b7089f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=97931321032600695324526385267703640855009291882161556704743957564071292567985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_st
ress_all.97931321032600695324526385267703640855009291882161556704743957564071292567985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.16859840688616508588487069005870780097009611847733207040007732912026141607996
Short name T640
Test name
Test status
Simulation time 322955517 ps
CPU time 6.21 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:02:42 PM PST 23
Peak memory 219284 kb
Host smart-d8c627f5-101c-448f-91f1-067fa1c57964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16859840688616508588487069005870780097009611847733207
040007732912026141607996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac.16859840688616508588487069005870780097
009611847733207040007732912026141607996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.26208100570892171845541874372650368507205642620996628872302502593899382884027
Short name T679
Test name
Test status
Simulation time 309259198 ps
CPU time 5.65 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 219324 kb
Host smart-7f6fd419-a125-45dd-a64d-367a919bd0d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208100570892171845541874372650368507205642620996628
872302502593899382884027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.262081005708921718455418743726
50368507205642620996628872302502593899382884027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.84493286136474599129738738869768621665462582750922607506444561303343176494362
Short name T911
Test name
Test status
Simulation time 117329894454 ps
CPU time 2177.55 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:38:47 PM PST 23
Peak memory 400816 kb
Host smart-3b23cbc3-2473-423b-80b6-c598bff86359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=84493286136474599129738738869768621665462582750922607506444561303343176494362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_sha3_224.84493286136474599129738738869768621665462582750922607506444561303343176494362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.89918822628802273460349860514902329776302506298742247570207891102047821412530
Short name T424
Test name
Test status
Simulation time 106843317633 ps
CPU time 1895.77 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:34:09 PM PST 23
Peak memory 376404 kb
Host smart-f9ac53f5-04f5-4563-bae3-2a607bd6d180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89918822628802273460349860514902329776302506298742247570207891102047821412530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_sha3_256.89918822628802273460349860514902329776302506298742247570207891102047821412530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.57946105517519216367645752121014570046128760802103551285050331960871945306147
Short name T458
Test name
Test status
Simulation time 83520343504 ps
CPU time 1609.27 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:29:22 PM PST 23
Peak memory 337296 kb
Host smart-9f1f39fc-d222-4d5e-bcfa-c1a81c31cb63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57946105517519216367645752121014570046128760802103551285050331960871945306147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_sha3_384.57946105517519216367645752121014570046128760802103551285050331960871945306147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.88604091935615811877825001431016003163379673346492740739644373931334246033996
Short name T464
Test name
Test status
Simulation time 57499426673 ps
CPU time 1201.89 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 297852 kb
Host smart-11a82cd3-a8f6-455d-bc63-35093eb72fe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=88604091935615811877825001431016003163379673346492740739644373931334246033996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_sha3_512.88604091935615811877825001431016003163379673346492740739644373931334246033996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.43005578789540338286467051611853923269500818995401449469052462577604949323762
Short name T1068
Test name
Test status
Simulation time 320694338954 ps
CPU time 5374.77 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 03:32:03 PM PST 23
Peak memory 674372 kb
Host smart-5b567359-7bf2-4365-8dcd-a04a0c97aec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=43005578789540338286467051611853923269500818995401449469052462577604949323762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.kmac_test_vectors_shake_128.43005578789540338286467051611853923269500818995401449469052462577604949323762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.29264788335641036047560524226140899140575864901431735276030027992621222739085
Short name T130
Test name
Test status
Simulation time 270085708112 ps
CPU time 4507.48 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 03:17:37 PM PST 23
Peak memory 577368 kb
Host smart-dd20750d-7faa-42a5-b394-23ff3ad61001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=29264788335641036047560524226140899140575864901431735276030027992621222739085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.kmac_test_vectors_shake_256.29264788335641036047560524226140899140575864901431735276030027992621222739085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.115023666924141774820860341889498170236331710135234551945343476363097110309106
Short name T344
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:28 PM PST 23
Peak memory 218916 kb
Host smart-3b8908ef-d1c6-4063-81ca-c94cf738b957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115023666924141774820860341889498170236331710135234551945343476363097110309106 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.115023666924141774820860341889498170236331710135234551945343476363097110309106 +enable_masking=1
+sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.22749741391547356065654297060996087830891319687474034554702065375983089352342
Short name T1012
Test name
Test status
Simulation time 6076748772 ps
CPU time 91.94 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 236264 kb
Host smart-15bcb8d5-8f85-4335-8823-8eb5dacdc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22749741391547356065654297060996087830891319687474034554702065375983089352342 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_app.22749741391547356065654297060996087830891319687474034554702065375983089352342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.114551419675726817650476145919952091073503782436084990055117548668408125253269
Short name T770
Test name
Test status
Simulation time 14830000174 ps
CPU time 386.19 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:09:13 PM PST 23
Peak memory 243188 kb
Host smart-f0a6b2cf-a483-4659-8dfb-74dd6e60eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114551419675726817650476145919952091073503782436084990055117548668408125253269 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.kmac_burst_write.114551419675726817650476145919952091073503782436084990055117548668408125253269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.30307630623810895083885245681533602858641604083490736477838345637060472053209
Short name T895
Test name
Test status
Simulation time 62261174 ps
CPU time 1.2 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219092 kb
Host smart-1a795592-b78b-4576-9031-d4d96e9ca244
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30307630623810895083885245681533602858641604083490736477838345637060472053209 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.kmac_edn_timeout_error.30307630623810895083885245681533602858641604083490736477838345637060472053209 +enable_masking=1
+sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.105970619569606342398884181700200982126645508580265324855650683985176901138808
Short name T864
Test name
Test status
Simulation time 64850439 ps
CPU time 1.26 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219012 kb
Host smart-bed20f05-8962-4051-af5f-c07675f2ee8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=105970619569606342398884181700200982126645508580265324855650683985176901138808 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.105970619569606342398884181700200982126645508580265324855650683985176901138808 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.31124616138495711879844291823261630733437456043182571414045404809162671569932
Short name T486
Test name
Test status
Simulation time 7238810904 ps
CPU time 107.75 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:04:16 PM PST 23
Peak memory 243908 kb
Host smart-8679d0e3-93c0-4c46-a505-e28464ef12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31124616138495711879844291823261630733437456043182571414045404809162671569932 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.kmac_entropy_refresh.31124616138495711879844291823261630733437456043182571414045404809162671569932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.90708304549362098319395315891870382762495213654723619519553806078560169870488
Short name T349
Test name
Test status
Simulation time 8137821569 ps
CPU time 142.01 seconds
Started Nov 22 02:02:32 PM PST 23
Finished Nov 22 02:05:00 PM PST 23
Peak memory 252776 kb
Host smart-9e621cb7-a2d3-4a45-a112-1605b8a93a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90708304549362098319395315891870382762495213654723619519553806078560169870488 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.kmac_error.90708304549362098319395315891870382762495213654723619519553806078560169870488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.93919157755293945679920689780330331301346333518661094340903487301464610511511
Short name T1019
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.82 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 219312 kb
Host smart-22d5eb25-52b5-4902-8022-58f426482f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93919157755293945679920689780330331301346333518661094340903487301464610511511 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.kmac_key_error.93919157755293945679920689780330331301346333518661094340903487301464610511511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.69434834578779039602034678495768694097961174430596257310099116871639046945105
Short name T252
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:02:35 PM PST 23
Peak memory 220508 kb
Host smart-65650db7-8ff3-4c06-97a6-d777bd6ec905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69434834578779039602034678495768694097961174430596257310099116871639046945105 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.kmac_lc_escalation.69434834578779039602034678495768694097961174430596257310099116871639046945105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.98972386262736415591134705625731740819598160006790820358562889858458434251528
Short name T818
Test name
Test status
Simulation time 50513696845 ps
CPU time 996.7 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:19:08 PM PST 23
Peak memory 306336 kb
Host smart-18580cdd-8349-4b31-97e3-d1e9cce136b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98972386262736415591134705625731740819598160006790820358562889858458434251528 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.989723862627364155911347056257317408195981600067908203585628898584584
34251528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.82361572319415060914217923686968357265854443402718100675516176212227675290018
Short name T599
Test name
Test status
Simulation time 7628111361 ps
CPU time 136.95 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:04:50 PM PST 23
Peak memory 236376 kb
Host smart-9db39ad3-d5e1-49eb-b391-b91da6aca328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82361572319415060914217923686968357265854443402718100675516176212227675290018 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.kmac_sideload.82361572319415060914217923686968357265854443402718100675516176212227675290018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.53961562016053490128052872193901372145290733916195334809141531279861571083536
Short name T674
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.15 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 225464 kb
Host smart-1177c31d-f644-46bd-ad20-d6700de70c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53961562016053490128052872193901372145290733916195334809141531279861571083536 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.kmac_smoke.53961562016053490128052872193901372145290733916195334809141531279861571083536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.66898515607590798297132377840235141486144568884804392341347270801654437697315
Short name T714
Test name
Test status
Simulation time 47207151869 ps
CPU time 907.78 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:17:41 PM PST 23
Peak memory 339812 kb
Host smart-22937af8-64e6-4f91-b9ac-ae3667032725
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=66898515607590798297132377840235141486144568884804392341347270801654437697315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_st
ress_all.66898515607590798297132377840235141486144568884804392341347270801654437697315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.94510482189953839569417986085366476684608714486697096341447555885718066597239
Short name T550
Test name
Test status
Simulation time 322955517 ps
CPU time 5.91 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:39 PM PST 23
Peak memory 219300 kb
Host smart-5dfa825a-93f7-44a5-9a11-2fc27a0a79d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94510482189953839569417986085366476684608714486697096
341447555885718066597239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac.94510482189953839569417986085366476684
608714486697096341447555885718066597239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.45460416552952705173234995990854034356881015690801590400703972770641758308758
Short name T431
Test name
Test status
Simulation time 309259198 ps
CPU time 6.08 seconds
Started Nov 22 02:02:30 PM PST 23
Finished Nov 22 02:02:43 PM PST 23
Peak memory 219280 kb
Host smart-f53636b9-04d4-431c-bb6b-e4ac7215123e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45460416552952705173234995990854034356881015690801590
400703972770641758308758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.454604165529527051732349959908
54034356881015690801590400703972770641758308758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.14176180136941485259438388893257709885391508780987797132396992735757745470828
Short name T618
Test name
Test status
Simulation time 117329894454 ps
CPU time 2086.08 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:37:13 PM PST 23
Peak memory 400804 kb
Host smart-1c219bd5-6ebd-4aa5-ac2b-ea34c06d821f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14176180136941485259438388893257709885391508780987797132396992735757745470828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_224.14176180136941485259438388893257709885391508780987797132396992735757745470828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.90141915140185893132475180737011934744444114331784110550738959600778385945735
Short name T821
Test name
Test status
Simulation time 106843317633 ps
CPU time 1871.5 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:33:40 PM PST 23
Peak memory 376384 kb
Host smart-53f45e56-84ee-456e-a805-e41f3fea22e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90141915140185893132475180737011934744444114331784110550738959600778385945735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_256.90141915140185893132475180737011934744444114331784110550738959600778385945735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.48325155264053582421314472350526493937856978187982800475256860328679222101635
Short name T490
Test name
Test status
Simulation time 83520343504 ps
CPU time 1622.84 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:29:35 PM PST 23
Peak memory 338468 kb
Host smart-45416e68-9d38-46eb-8e5d-63ef94c6eb7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=48325155264053582421314472350526493937856978187982800475256860328679222101635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_384.48325155264053582421314472350526493937856978187982800475256860328679222101635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.38271378821031569553192819670200872971994869282755367695880359503199095465182
Short name T920
Test name
Test status
Simulation time 57499426673 ps
CPU time 1164.19 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:21:57 PM PST 23
Peak memory 297788 kb
Host smart-df68328a-6320-4028-b30c-3cf2fbd0c1a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38271378821031569553192819670200872971994869282755367695880359503199095465182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_512.38271378821031569553192819670200872971994869282755367695880359503199095465182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.54937752605175307440464486998242047462515498578464535117729577714393004087733
Short name T721
Test name
Test status
Simulation time 320694338954 ps
CPU time 5436.82 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 03:33:09 PM PST 23
Peak memory 674192 kb
Host smart-279c5eb2-d267-4762-b381-624f9b4ecb1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=54937752605175307440464486998242047462515498578464535117729577714393004087733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_test_vectors_shake_128.54937752605175307440464486998242047462515498578464535117729577714393004087733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.42449261732698033618641481627586758213391504989696478530266781163141439791813
Short name T595
Test name
Test status
Simulation time 270085708112 ps
CPU time 4653.86 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 03:20:06 PM PST 23
Peak memory 577452 kb
Host smart-013bea99-1a69-48da-b8a1-588e294f2eed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42449261732698033618641481627586758213391504989696478530266781163141439791813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_test_vectors_shake_256.42449261732698033618641481627586758213391504989696478530266781163141439791813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.77871864609734778630666429084891110485675451014412221025548040444710238413
Short name T469
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:00:29 PM PST 23
Peak memory 219000 kb
Host smart-fe22c4b9-7d88-4fa5-8e5d-4c302b9b8a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77871864609734778630666429084891110485675451014412221025548040444710238413 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.kmac_alert_test.77871864609734778630666429084891110485675451014412221025548040444710238413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.22230608877036062440556671620601933855189997523864802505272154670770858685455
Short name T590
Test name
Test status
Simulation time 6076748772 ps
CPU time 96.76 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:02:07 PM PST 23
Peak memory 236304 kb
Host smart-8c32253b-b190-4c99-9594-c7b9f5d4d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22230608877036062440556671620601933855189997523864802505272154670770858685455 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_app.22230608877036062440556671620601933855189997523864802505272154670770858685455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_burst_write.87694249529616787798894122534064359406468408754274698534393738217300305557463
Short name T1049
Test name
Test status
Simulation time 14830000174 ps
CPU time 402.64 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:07:14 PM PST 23
Peak memory 243232 kb
Host smart-396d6c46-02b5-4034-b546-36663f4d35ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87694249529616787798894122534064359406468408754274698534393738217300305557463 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.kmac_burst_write.87694249529616787798894122534064359406468408754274698534393738217300305557463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.69513343643028571862453122062868923495426801348980908896339591323131686223218
Short name T1011
Test name
Test status
Simulation time 62261174 ps
CPU time 1.26 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:00:32 PM PST 23
Peak memory 219004 kb
Host smart-b7babd86-9b71-4552-95b7-4196597abec5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69513343643028571862453122062868923495426801348980908896339591323131686223218 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.kmac_edn_timeout_error.69513343643028571862453122062868923495426801348980908896339591323131686223218 +enable_masking=1
+sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.76424336699582080893826428887158976307620706044995674609149607197421426888070
Short name T301
Test name
Test status
Simulation time 64850439 ps
CPU time 1.23 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:00:50 PM PST 23
Peak memory 218960 kb
Host smart-63f05f17-67bf-4bae-9936-510349c3fcb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76424336699582080893826428887158976307620706044995674609149607197421426888070 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.76424336699582080893826428887158976307620706044995674609149607197421426888070 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.67879584649581652964476762244580708668287102510330270757084381006872659639508
Short name T57
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.61 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:01:10 PM PST 23
Peak memory 219220 kb
Host smart-43831e5a-79b2-4ec2-b2cd-be2b9dc6b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67879584649581652964476762244580708668287102510330270757084381006872659639508 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.kmac_entropy_ready_error.67879584649581652964476762244580708668287102510330270757084381006872659639508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.60540759962214463992625622603170128256177686204561261270191099330806554543164
Short name T912
Test name
Test status
Simulation time 7238810904 ps
CPU time 106.72 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:02:36 PM PST 23
Peak memory 243864 kb
Host smart-d734e37f-6937-4a3e-809b-9ebbec33c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60540759962214463992625622603170128256177686204561261270191099330806554543164 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.kmac_entropy_refresh.60540759962214463992625622603170128256177686204561261270191099330806554543164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.65418415661305044229449809195825016669820633699543449708885247640364954643239
Short name T82
Test name
Test status
Simulation time 8137821569 ps
CPU time 149.46 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 252688 kb
Host smart-47039308-bc03-4589-a44f-ab52018c63f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65418415661305044229449809195825016669820633699543449708885247640364954643239 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.kmac_error.65418415661305044229449809195825016669820633699543449708885247640364954643239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.27185178151370846344132586384253619464987059190133039601185560799690776682506
Short name T524
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.67 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:00:37 PM PST 23
Peak memory 219252 kb
Host smart-1f9c96f8-6950-4da2-9064-1ec8573e1f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27185178151370846344132586384253619464987059190133039601185560799690776682506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.kmac_key_error.27185178151370846344132586384253619464987059190133039601185560799690776682506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.51751381512727330655727726173595464668859589299750434961628840679286497702737
Short name T453
Test name
Test status
Simulation time 72761090 ps
CPU time 1.45 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:00:49 PM PST 23
Peak memory 220488 kb
Host smart-d959be99-37f8-4aed-be52-db97bba608cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51751381512727330655727726173595464668859589299750434961628840679286497702737 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.kmac_lc_escalation.51751381512727330655727726173595464668859589299750434961628840679286497702737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.99364279327551426814979655922690222375959013490630533329195614353258425818099
Short name T903
Test name
Test status
Simulation time 50513696845 ps
CPU time 971.81 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:16:41 PM PST 23
Peak memory 306332 kb
Host smart-16e9e486-09e3-4eda-a2b3-624f77ce5e03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99364279327551426814979655922690222375959013490630533329195614353258425818099 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.9936427932755142681497965592269022237595901349063053332919561435325842
5818099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.99742740097428764414365058485701553573012149843567617288396795773058775577330
Short name T328
Test name
Test status
Simulation time 7712378544 ps
CPU time 136.1 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:02:47 PM PST 23
Peak memory 244136 kb
Host smart-97e52e33-a7b3-4932-8e37-069ea7a72634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99742740097428764414365058485701553573012149843567617288396795773058775577330 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.kmac_mubi.99742740097428764414365058485701553573012149843567617288396795773058775577330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.111542785172242556522351843756775322837124161740078284278490173671503039370247
Short name T29
Test name
Test status
Simulation time 6415496062 ps
CPU time 54.66 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:01:57 PM PST 23
Peak memory 277196 kb
Host smart-0cdb766a-9500-407e-a0d1-021b7510f311
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111542785172242556522351843756775322837124161740078284278490173671503039370247 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.kmac_sec_cm.111542785172242556522351843756775322837124161740078284278490173671503039370247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.37931110487471263579943544470021071808183851317740128609281449105867916700357
Short name T748
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.47 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:02:46 PM PST 23
Peak memory 236472 kb
Host smart-6e8ad07f-9a1f-43b9-9fa7-ca91e00394f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37931110487471263579943544470021071808183851317740128609281449105867916700357 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.kmac_sideload.37931110487471263579943544470021071808183851317740128609281449105867916700357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.18234914993307469711754540208143397150025842374022468347631366388784442939157
Short name T592
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.65 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:00:55 PM PST 23
Peak memory 225384 kb
Host smart-5a67b987-3f2c-49f8-bdf2-73ff393861fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18234914993307469711754540208143397150025842374022468347631366388784442939157 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.kmac_smoke.18234914993307469711754540208143397150025842374022468347631366388784442939157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.84692624205578880554440198217578345813356617879514100494034365803659107608722
Short name T41
Test name
Test status
Simulation time 47207151869 ps
CPU time 909.75 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:15:58 PM PST 23
Peak memory 339832 kb
Host smart-ebf934f1-7aad-4fb4-bd61-ee9d10394f85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=84692624205578880554440198217578345813356617879514100494034365803659107608722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_str
ess_all.84692624205578880554440198217578345813356617879514100494034365803659107608722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.34918156259701783840142835932696074542939748818505730869075924966258244457952
Short name T352
Test name
Test status
Simulation time 322955517 ps
CPU time 5.89 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:00:36 PM PST 23
Peak memory 219272 kb
Host smart-c9eb2140-a833-4c78-8ec6-c055928fc7d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34918156259701783840142835932696074542939748818505730
869075924966258244457952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.349181562597017838401428359326960745429
39748818505730869075924966258244457952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.102325904855764989826031617719688113567205050862321761508999455893879998236689
Short name T950
Test name
Test status
Simulation time 309259198 ps
CPU time 5.5 seconds
Started Nov 22 02:00:31 PM PST 23
Finished Nov 22 02:00:37 PM PST 23
Peak memory 219260 kb
Host smart-e30eacd4-1acb-4afb-bdb5-48bdf69a1f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10232590485576498982603161771968811356720505086232176
1508999455893879998236689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.102325904855764989826031617719
688113567205050862321761508999455893879998236689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.55979839258715413346708180541609875605543736049709989824812508682654491461731
Short name T876
Test name
Test status
Simulation time 117329894454 ps
CPU time 2119.56 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 02:35:50 PM PST 23
Peak memory 400836 kb
Host smart-1b0b6df2-d2d3-4c0c-be94-8a73d8500bd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55979839258715413346708180541609875605543736049709989824812508682654491461731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
kmac_test_vectors_sha3_224.55979839258715413346708180541609875605543736049709989824812508682654491461731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.104504281918533019531624163322945224715597644555901203766519612686220962013194
Short name T452
Test name
Test status
Simulation time 106843317633 ps
CPU time 2001.84 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:33:50 PM PST 23
Peak memory 376428 kb
Host smart-bfc924d6-5d03-413a-b521-249f2ccdd588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=104504281918533019531624163322945224715597644555901203766519612686220962013194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.kmac_test_vectors_sha3_256.104504281918533019531624163322945224715597644555901203766519612686220962013194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.60940142404716430552654540876746917882843159469903132471240463130927287063616
Short name T251
Test name
Test status
Simulation time 83520343504 ps
CPU time 1556.7 seconds
Started Nov 22 02:00:41 PM PST 23
Finished Nov 22 02:26:39 PM PST 23
Peak memory 338476 kb
Host smart-d9658a2a-680d-4013-af20-5e4b80fcb9f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=60940142404716430552654540876746917882843159469903132471240463130927287063616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
kmac_test_vectors_sha3_384.60940142404716430552654540876746917882843159469903132471240463130927287063616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.16286694592444479727205939175767334230249094630454935717545399788817765763421
Short name T710
Test name
Test status
Simulation time 57499426673 ps
CPU time 1158.73 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:19:51 PM PST 23
Peak memory 297844 kb
Host smart-542a5a6e-832f-454c-bd68-1f3d33d35546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16286694592444479727205939175767334230249094630454935717545399788817765763421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
kmac_test_vectors_sha3_512.16286694592444479727205939175767334230249094630454935717545399788817765763421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.44062914664385111137631506745145529284557328153074708202523549573580450515662
Short name T35
Test name
Test status
Simulation time 320694338954 ps
CPU time 5522.28 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 03:32:32 PM PST 23
Peak memory 674316 kb
Host smart-d8e8a907-4abf-44f3-b273-66975704a603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=44062914664385111137631506745145529284557328153074708202523549573580450515662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_test_vectors_shake_128.44062914664385111137631506745145529284557328153074708202523549573580450515662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.86317449156091313045304283419671018190607092311892387090915923773347180872538
Short name T365
Test name
Test status
Simulation time 270085708112 ps
CPU time 4706.75 seconds
Started Nov 22 02:00:27 PM PST 23
Finished Nov 22 03:18:55 PM PST 23
Peak memory 577236 kb
Host smart-7fd3103b-9239-4778-81fc-f9113189d32c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=86317449156091313045304283419671018190607092311892387090915923773347180872538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_test_vectors_shake_256.86317449156091313045304283419671018190607092311892387090915923773347180872538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.76078430374493692625805048961504881864231010940360065398030876435000484276876
Short name T634
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:02:36 PM PST 23
Peak memory 219048 kb
Host smart-42d0677e-d01f-46bf-aa33-fc3e6144c78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76078430374493692625805048961504881864231010940360065398030876435000484276876 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.kmac_alert_test.76078430374493692625805048961504881864231010940360065398030876435000484276876 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.57751197746511896912101539352194366066323129939603264670209379782467748290278
Short name T571
Test name
Test status
Simulation time 6076748772 ps
CPU time 102.93 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:04:19 PM PST 23
Peak memory 236104 kb
Host smart-07d32eda-beb5-4a4d-98b3-b2e829c2c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57751197746511896912101539352194366066323129939603264670209379782467748290278 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_app.57751197746511896912101539352194366066323129939603264670209379782467748290278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.8400634659923366487706173984316328514639130871101693577488089926033907350276
Short name T487
Test name
Test status
Simulation time 14830000174 ps
CPU time 419.72 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:09:30 PM PST 23
Peak memory 243268 kb
Host smart-b1e13425-68fc-4e1a-b008-412b07db9d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8400634659923366487706173984316328514639130871101693577488089926033907350276 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.kmac_burst_write.8400634659923366487706173984316328514639130871101693577488089926033907350276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.108396075678909554311706711285852715285327344079330863294549113331581973411942
Short name T1057
Test name
Test status
Simulation time 7238810904 ps
CPU time 107.47 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:04:20 PM PST 23
Peak memory 243868 kb
Host smart-7e230709-2fee-4202-9c47-4c46c5c1568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108396075678909554311706711285852715285327344079330863294549113331581973411942 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.kmac_entropy_refresh.108396075678909554311706711285852715285327344079330863294549113331581973411942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.34834961641521822070482381824834858678043180135443607930935035297349399851685
Short name T127
Test name
Test status
Simulation time 8137821569 ps
CPU time 149.94 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:05:02 PM PST 23
Peak memory 252740 kb
Host smart-91164420-510c-43cc-9dc0-ac8c949287a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34834961641521822070482381824834858678043180135443607930935035297349399851685 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.kmac_error.34834961641521822070482381824834858678043180135443607930935035297349399851685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.5489055105117429905212116896700930142986553134489706156270630131447177207955
Short name T219
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.78 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:33 PM PST 23
Peak memory 219248 kb
Host smart-805c407b-d812-4b80-9757-58d0f5776974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5489055105117429905212116896700930142986553134489706156270630131447177207955 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.kmac_key_error.5489055105117429905212116896700930142986553134489706156270630131447177207955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.97666108669039304770023733588557404097371670679411621791551580647793495439771
Short name T968
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:35 PM PST 23
Peak memory 220416 kb
Host smart-92129a51-1293-4880-ae9a-c0348761dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97666108669039304770023733588557404097371670679411621791551580647793495439771 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.kmac_lc_escalation.97666108669039304770023733588557404097371670679411621791551580647793495439771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.51323211069508312801042894353410290357861673430965682680689715348747325576073
Short name T432
Test name
Test status
Simulation time 50513696845 ps
CPU time 1019.34 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:19:31 PM PST 23
Peak memory 306280 kb
Host smart-8aabf37f-29e6-47bc-bb36-f55f8d82f19f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51323211069508312801042894353410290357861673430965682680689715348747325576073 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.513232110695083128010428943534102903578616734309656826806897153487473
25576073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.108527719361235840624255035751399518778662142115305098143619822220154519316498
Short name T239
Test name
Test status
Simulation time 7628111361 ps
CPU time 135.96 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:49 PM PST 23
Peak memory 236396 kb
Host smart-ce70a3d1-049b-40f9-8fcc-9984151c1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108527719361235840624255035751399518778662142115305098143619822220154519316498 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.kmac_sideload.108527719361235840624255035751399518778662142115305098143619822220154519316498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.10282475511790023535072381611668835711686094640808772704582983717921293455990
Short name T415
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.65 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 225404 kb
Host smart-61004520-1f81-4ea8-913e-74d08897f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10282475511790023535072381611668835711686094640808772704582983717921293455990 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.kmac_smoke.10282475511790023535072381611668835711686094640808772704582983717921293455990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.83269911818212710444618637612667534729416451312397526904693558321069093969953
Short name T429
Test name
Test status
Simulation time 47207151869 ps
CPU time 906.52 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:17:35 PM PST 23
Peak memory 339808 kb
Host smart-f8805304-3a8d-4278-a9c8-837e5bd316a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=83269911818212710444618637612667534729416451312397526904693558321069093969953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_st
ress_all.83269911818212710444618637612667534729416451312397526904693558321069093969953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.18039593742672287586258206594031000307906320194562022525231762834191368985423
Short name T400
Test name
Test status
Simulation time 322955517 ps
CPU time 6.14 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 219228 kb
Host smart-0008f811-8b2a-48f6-b083-f1e85db317d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18039593742672287586258206594031000307906320194562022
525231762834191368985423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac.18039593742672287586258206594031000307
906320194562022525231762834191368985423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.80434331601154231820695243402236704378012716326725034232823413900540159821486
Short name T242
Test name
Test status
Simulation time 309259198 ps
CPU time 6.1 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:53 PM PST 23
Peak memory 219204 kb
Host smart-9c7bf22f-a41c-47c7-b84f-519a7f699a91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80434331601154231820695243402236704378012716326725034
232823413900540159821486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.804343316011542318206952434022
36704378012716326725034232823413900540159821486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.72951050974093522369279566495416727030831033673688244991669307205674573327879
Short name T738
Test name
Test status
Simulation time 117329894454 ps
CPU time 2124.69 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:37:56 PM PST 23
Peak memory 400856 kb
Host smart-81dd7a3e-0536-4cf2-805f-2cb4fcc64e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=72951050974093522369279566495416727030831033673688244991669307205674573327879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_224.72951050974093522369279566495416727030831033673688244991669307205674573327879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.86861249844854989189891064742982205689455377899786682177052922960998973468805
Short name T313
Test name
Test status
Simulation time 106843317633 ps
CPU time 1906.36 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:34:20 PM PST 23
Peak memory 376392 kb
Host smart-070aa683-2cb8-4d34-843e-5dcc33a5ed8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86861249844854989189891064742982205689455377899786682177052922960998973468805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_256.86861249844854989189891064742982205689455377899786682177052922960998973468805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.29030812841619176568730439733539772536972829760669886951750660635454966765303
Short name T169
Test name
Test status
Simulation time 83520343504 ps
CPU time 1564.41 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:28:36 PM PST 23
Peak memory 338380 kb
Host smart-e759d085-9ace-4d8d-8b6b-4b6fa956abc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=29030812841619176568730439733539772536972829760669886951750660635454966765303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_384.29030812841619176568730439733539772536972829760669886951750660635454966765303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.25865039402257283079471716582951947800222542740369832225304812652603805802319
Short name T215
Test name
Test status
Simulation time 57499426673 ps
CPU time 1111.81 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 297476 kb
Host smart-9d183be8-e2a9-45cb-8c68-88c4d61c8ca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25865039402257283079471716582951947800222542740369832225304812652603805802319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_512.25865039402257283079471716582951947800222542740369832225304812652603805802319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.65528493681478564432620035296047045795786288609053496857016372218884653131321
Short name T122
Test name
Test status
Simulation time 320694338954 ps
CPU time 5358.82 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 03:31:52 PM PST 23
Peak memory 674188 kb
Host smart-c8f949dd-dcf6-4b49-8cfd-bfed5fcfaa23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=65528493681478564432620035296047045795786288609053496857016372218884653131321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_test_vectors_shake_128.65528493681478564432620035296047045795786288609053496857016372218884653131321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.24207599483548403830728175780535064918704024771158310270942720959258620442951
Short name T586
Test name
Test status
Simulation time 270085708112 ps
CPU time 4668.74 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 03:20:25 PM PST 23
Peak memory 577352 kb
Host smart-a4713489-2e18-42c9-ab99-5014812667f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=24207599483548403830728175780535064918704024771158310270942720959258620442951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_test_vectors_shake_256.24207599483548403830728175780535064918704024771158310270942720959258620442951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.85782203523251822929945940167354304184759032503813877997201323824361584226918
Short name T1075
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 218956 kb
Host smart-15ddf55b-dd02-48be-95d7-3f03041bdd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85782203523251822929945940167354304184759032503813877997201323824361584226918 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.kmac_alert_test.85782203523251822929945940167354304184759032503813877997201323824361584226918 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.81861973787630741716096195391440081539933020600538762813368035444254582118934
Short name T856
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.38 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:04:29 PM PST 23
Peak memory 236156 kb
Host smart-a832fba5-6878-4c65-9b13-a0429e5db457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81861973787630741716096195391440081539933020600538762813368035444254582118934 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.kmac_app.81861973787630741716096195391440081539933020600538762813368035444254582118934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.36353851140521692304057647637624898585577656842746225223916275260450327450367
Short name T610
Test name
Test status
Simulation time 14830000174 ps
CPU time 391.32 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:08:59 PM PST 23
Peak memory 243260 kb
Host smart-a65e4026-e7fd-4837-adf7-4a647ee006cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36353851140521692304057647637624898585577656842746225223916275260450327450367 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.kmac_burst_write.36353851140521692304057647637624898585577656842746225223916275260450327450367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.24640697782892867004759056283145305567364330317437812253742205999108965696012
Short name T476
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.19 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:04:38 PM PST 23
Peak memory 243848 kb
Host smart-2cc0c5d5-62aa-4530-a328-5e243bc2aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24640697782892867004759056283145305567364330317437812253742205999108965696012 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.kmac_entropy_refresh.24640697782892867004759056283145305567364330317437812253742205999108965696012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.10748292229635840343856655912433976827794602434774832959243372830149124358744
Short name T364
Test name
Test status
Simulation time 8137821569 ps
CPU time 150.46 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:05:20 PM PST 23
Peak memory 252732 kb
Host smart-c1775e38-9ec0-41b6-b342-6e12b62afe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10748292229635840343856655912433976827794602434774832959243372830149124358744 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.kmac_error.10748292229635840343856655912433976827794602434774832959243372830149124358744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.60422711354325574288638150137652085404346861261568094504850699756020406541014
Short name T78
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.81 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 219236 kb
Host smart-bd910f6a-837a-4c70-abd2-8fba6d6d915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60422711354325574288638150137652085404346861261568094504850699756020406541014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.kmac_key_error.60422711354325574288638150137652085404346861261568094504850699756020406541014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.93845528618213642997148873198056272285160543194463411859713486735887313259348
Short name T460
Test name
Test status
Simulation time 72761090 ps
CPU time 1.38 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:02:49 PM PST 23
Peak memory 220424 kb
Host smart-45794c5c-9057-49d1-a2b1-6a92987e1c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93845528618213642997148873198056272285160543194463411859713486735887313259348 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.kmac_lc_escalation.93845528618213642997148873198056272285160543194463411859713486735887313259348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.97631277280247631506832465093703646007231207306547725214936324917097057107000
Short name T211
Test name
Test status
Simulation time 50513696845 ps
CPU time 1070.66 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:20:18 PM PST 23
Peak memory 306336 kb
Host smart-28a14fbb-6ca4-4fed-8f90-e28d15daa2a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97631277280247631506832465093703646007231207306547725214936324917097057107000 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.976312772802476315068324650937036460072312073065477252149363249170970
57107000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.111401159291961973703039561857944199196076819777932426891069428347275769537353
Short name T134
Test name
Test status
Simulation time 7628111361 ps
CPU time 144.73 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:04:58 PM PST 23
Peak memory 236340 kb
Host smart-cfe7add4-405c-47c0-920b-83ea8ccabbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111401159291961973703039561857944199196076819777932426891069428347275769537353 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.kmac_sideload.111401159291961973703039561857944199196076819777932426891069428347275769537353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.95847009076574159663088640499492157607895680150575750451374895164242541784640
Short name T523
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.01 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:03:03 PM PST 23
Peak memory 225416 kb
Host smart-ab50567a-a043-45e9-a30a-16ad420d566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95847009076574159663088640499492157607895680150575750451374895164242541784640 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.kmac_smoke.95847009076574159663088640499492157607895680150575750451374895164242541784640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.46913378386959013160550644523190303033149098875000885758450935909669849614381
Short name T865
Test name
Test status
Simulation time 47207151869 ps
CPU time 879.82 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:17:29 PM PST 23
Peak memory 339792 kb
Host smart-28cf7350-b359-4d74-b5d5-d559fa14b4ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=46913378386959013160550644523190303033149098875000885758450935909669849614381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_st
ress_all.46913378386959013160550644523190303033149098875000885758450935909669849614381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3727563996694867145287595682136080820509498133660234473038805218945328658355
Short name T281
Test name
Test status
Simulation time 322955517 ps
CPU time 5.96 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 218068 kb
Host smart-786373d0-0711-4adb-b72c-3e3bbadfad39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37275639966948671452875956821360808205094981336602344
73038805218945328658355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac.372756399669486714528759568213608082050
9498133660234473038805218945328658355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.64348290487001247989595759578296080503190550500050317149689291883685240860142
Short name T1004
Test name
Test status
Simulation time 309259198 ps
CPU time 5.66 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 218260 kb
Host smart-9a043d52-b6f0-4615-abb1-6c35a4b66294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64348290487001247989595759578296080503190550500050317
149689291883685240860142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.643482904870012479895957595782
96080503190550500050317149689291883685240860142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.86740204708605960878433717585448141462454761846898804609927933789801539104388
Short name T999
Test name
Test status
Simulation time 117329894454 ps
CPU time 2131.16 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:37:59 PM PST 23
Peak memory 400852 kb
Host smart-99d08a21-0079-4219-b641-59a3710a895c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86740204708605960878433717585448141462454761846898804609927933789801539104388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_224.86740204708605960878433717585448141462454761846898804609927933789801539104388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.49351899833630829235290131965295691135586887234582626864475645974714329979805
Short name T1044
Test name
Test status
Simulation time 106843317633 ps
CPU time 1886.5 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:34:00 PM PST 23
Peak memory 376452 kb
Host smart-1f73a531-4357-4fc0-8a02-57174cbf19b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=49351899833630829235290131965295691135586887234582626864475645974714329979805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_256.49351899833630829235290131965295691135586887234582626864475645974714329979805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.47341020874979660623427917476533254564986613121085830156187744929458205615867
Short name T319
Test name
Test status
Simulation time 83520343504 ps
CPU time 1640.45 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:29:53 PM PST 23
Peak memory 338392 kb
Host smart-14356104-646e-414a-8093-821d303185a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47341020874979660623427917476533254564986613121085830156187744929458205615867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_384.47341020874979660623427917476533254564986613121085830156187744929458205615867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.80977798088543951496888825246002643146903838732516169839344574515386806769145
Short name T971
Test name
Test status
Simulation time 57499426673 ps
CPU time 1153.04 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 297804 kb
Host smart-09d17044-76f4-494d-94ce-3fae90f4c64a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=80977798088543951496888825246002643146903838732516169839344574515386806769145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_512.80977798088543951496888825246002643146903838732516169839344574515386806769145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.7511350025608470504254798584467168597552228778510153317467389573261193816000
Short name T848
Test name
Test status
Simulation time 320694338954 ps
CPU time 5193.88 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 03:29:03 PM PST 23
Peak memory 672940 kb
Host smart-c892fffa-6598-4cc7-95da-0d6ffaf64476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=7511350025608470504254798584467168597552228778510153317467389573261193816000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.kmac_test_vectors_shake_128.7511350025608470504254798584467168597552228778510153317467389573261193816000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.36146920239508768626922143180063728765628582375604473013727572222952886356157
Short name T126
Test name
Test status
Simulation time 270085708112 ps
CPU time 4337.62 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 03:15:08 PM PST 23
Peak memory 576236 kb
Host smart-ff695a09-c715-4953-9408-a48de096d8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=36146920239508768626922143180063728765628582375604473013727572222952886356157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.kmac_test_vectors_shake_256.36146920239508768626922143180063728765628582375604473013727572222952886356157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.11326585450900294140484784057989863230553996613931041705684736956993246650265
Short name T630
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 218804 kb
Host smart-15da0c06-5ad7-462e-b9b0-322dfde62663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326585450900294140484784057989863230553996613931041705684736956993246650265 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.kmac_alert_test.11326585450900294140484784057989863230553996613931041705684736956993246650265 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.81900292651637621789629619644714190065792849718663187037069233663354564783116
Short name T933
Test name
Test status
Simulation time 6076748772 ps
CPU time 100.9 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:04:31 PM PST 23
Peak memory 236180 kb
Host smart-8ecdb13f-76b0-480c-b198-904385330227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81900292651637621789629619644714190065792849718663187037069233663354564783116 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_app.81900292651637621789629619644714190065792849718663187037069233663354564783116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.72527283865445126715217176816259824508035458187123507345714417794238202940138
Short name T1076
Test name
Test status
Simulation time 14830000174 ps
CPU time 384.13 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:09:13 PM PST 23
Peak memory 243176 kb
Host smart-f2e6db33-5afb-498c-9da6-884e7de03831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72527283865445126715217176816259824508035458187123507345714417794238202940138 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.kmac_burst_write.72527283865445126715217176816259824508035458187123507345714417794238202940138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.8356364638462476289544296085967111283727942399505351865328941775146775733574
Short name T996
Test name
Test status
Simulation time 7238810904 ps
CPU time 107.49 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:04:34 PM PST 23
Peak memory 243876 kb
Host smart-55ce5822-a49a-413f-a3da-e895dbeb4e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8356364638462476289544296085967111283727942399505351865328941775146775733574 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.kmac_entropy_refresh.8356364638462476289544296085967111283727942399505351865328941775146775733574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3501047760975063900726893516155612978266276286106547437453559281939497146676
Short name T1066
Test name
Test status
Simulation time 8137821569 ps
CPU time 148.18 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:05:17 PM PST 23
Peak memory 252704 kb
Host smart-27cc2864-87e8-4d10-ac07-959bdb7e58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501047760975063900726893516155612978266276286106547437453559281939497146676 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.kmac_error.3501047760975063900726893516155612978266276286106547437453559281939497146676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.15107860875870657396004186622671524127767123829382738720132630761319389335760
Short name T733
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.7 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 219196 kb
Host smart-4f195451-4cdb-4dfb-a917-83e36da1b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15107860875870657396004186622671524127767123829382738720132630761319389335760 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.kmac_key_error.15107860875870657396004186622671524127767123829382738720132630761319389335760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.49968287937627360965328603505226823187603816092784377283920569222822497548653
Short name T745
Test name
Test status
Simulation time 72761090 ps
CPU time 1.45 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 220504 kb
Host smart-56dbfcbd-61de-4cb9-8df4-47aa1aeaf42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49968287937627360965328603505226823187603816092784377283920569222822497548653 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.kmac_lc_escalation.49968287937627360965328603505226823187603816092784377283920569222822497548653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.30057560866295417284444858666009875687434960064729939804364394054284185728897
Short name T446
Test name
Test status
Simulation time 50513696845 ps
CPU time 927.35 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:18:15 PM PST 23
Peak memory 306268 kb
Host smart-bb4180dd-6b82-4ac3-ac6d-4e4a8e5821a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057560866295417284444858666009875687434960064729939804364394054284185728897 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.300575608662954172844448586660098756874349600647299398043643940542841
85728897 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.57195247272434015814318607699575474725980934409911428314091720964246584764488
Short name T468
Test name
Test status
Simulation time 7628111361 ps
CPU time 122.41 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:32 PM PST 23
Peak memory 236184 kb
Host smart-614f1bef-cc6f-4bdf-b47e-61c48b379683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57195247272434015814318607699575474725980934409911428314091720964246584764488 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.kmac_sideload.57195247272434015814318607699575474725980934409911428314091720964246584764488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.20489545281798173257963803921932504154038441405401145533696016741775357266402
Short name T129
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.7 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:03:14 PM PST 23
Peak memory 225348 kb
Host smart-287ebbac-10e0-4e65-9db2-e138c08414ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20489545281798173257963803921932504154038441405401145533696016741775357266402 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.kmac_smoke.20489545281798173257963803921932504154038441405401145533696016741775357266402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.5198112851953510146830503063731373105286512877075928239784083056292841852186
Short name T702
Test name
Test status
Simulation time 47207151869 ps
CPU time 897.99 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:17:29 PM PST 23
Peak memory 339832 kb
Host smart-9a4536ae-5c5a-4bcb-bf77-392782d31395
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=5198112851953510146830503063731373105286512877075928239784083056292841852186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_str
ess_all.5198112851953510146830503063731373105286512877075928239784083056292841852186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.45433985270743407897072199999497980111765364548919884691625481594380219660676
Short name T123
Test name
Test status
Simulation time 322955517 ps
CPU time 5.45 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 219048 kb
Host smart-a6a4f78e-8292-4f8e-90fa-ff6291b8b8c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45433985270743407897072199999497980111765364548919884
691625481594380219660676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac.45433985270743407897072199999497980111
765364548919884691625481594380219660676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.94093059930913088919179926806016500191031527882723143670128474079462034624940
Short name T317
Test name
Test status
Simulation time 309259198 ps
CPU time 5.68 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:51 PM PST 23
Peak memory 219228 kb
Host smart-481886fe-480d-4506-891b-63c3d96efbbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94093059930913088919179926806016500191031527882723143
670128474079462034624940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.940930599309130889191799268060
16500191031527882723143670128474079462034624940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.32083905571597765477313540460769909567843947423736888011378918902347788660966
Short name T107
Test name
Test status
Simulation time 117329894454 ps
CPU time 2015.64 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:36:26 PM PST 23
Peak memory 400856 kb
Host smart-5d45a5c1-fcd7-4f74-9673-4e7b50d517a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32083905571597765477313540460769909567843947423736888011378918902347788660966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.kmac_test_vectors_sha3_224.32083905571597765477313540460769909567843947423736888011378918902347788660966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.8949413021684598623876603269404068949537401177467171114189932314845039435547
Short name T310
Test name
Test status
Simulation time 106843317633 ps
CPU time 1908.72 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:34:38 PM PST 23
Peak memory 376384 kb
Host smart-8bf311b7-d2d9-4d92-8109-1b1d8869dd81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8949413021684598623876603269404068949537401177467171114189932314845039435547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
kmac_test_vectors_sha3_256.8949413021684598623876603269404068949537401177467171114189932314845039435547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.45011187543442960059317534600903491547673643532854424847667485981249355555898
Short name T165
Test name
Test status
Simulation time 83520343504 ps
CPU time 1602.54 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:29:29 PM PST 23
Peak memory 338440 kb
Host smart-974fa004-58e2-4840-bb7f-7a1392f00cd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45011187543442960059317534600903491547673643532854424847667485981249355555898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.kmac_test_vectors_sha3_384.45011187543442960059317534600903491547673643532854424847667485981249355555898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.13469681272164411521605981773397246252108227065888978415260068150841045253506
Short name T541
Test name
Test status
Simulation time 57499426673 ps
CPU time 1241.11 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 297744 kb
Host smart-a6e68198-9f24-4c63-9c0e-45d11c41a77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=13469681272164411521605981773397246252108227065888978415260068150841045253506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.kmac_test_vectors_sha3_512.13469681272164411521605981773397246252108227065888978415260068150841045253506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.87880399041821653993118753442573214039984701752021101572380248847043621766793
Short name T963
Test name
Test status
Simulation time 320694338954 ps
CPU time 5156.76 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 03:28:46 PM PST 23
Peak memory 673508 kb
Host smart-4dd69cea-539b-4d27-aa38-faf518910718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=87880399041821653993118753442573214039984701752021101572380248847043621766793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_test_vectors_shake_128.87880399041821653993118753442573214039984701752021101572380248847043621766793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.51988697637090669834242721821157769285828482797416079423597203812585354410388
Short name T272
Test name
Test status
Simulation time 270085708112 ps
CPU time 4735.16 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 03:21:43 PM PST 23
Peak memory 577364 kb
Host smart-705978c2-086f-4262-9e1d-c51ac06a172c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=51988697637090669834242721821157769285828482797416079423597203812585354410388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_test_vectors_shake_256.51988697637090669834242721821157769285828482797416079423597203812585354410388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.48148811214777402044594171897658057460993106621977118400423556091307481419762
Short name T506
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:02:39 PM PST 23
Finished Nov 22 02:02:51 PM PST 23
Peak memory 218984 kb
Host smart-bbf3f391-6426-4352-86ec-d5b7e08d7d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48148811214777402044594171897658057460993106621977118400423556091307481419762 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.kmac_alert_test.48148811214777402044594171897658057460993106621977118400423556091307481419762 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.6098748974588369206368983562267835620577967604112477478016151319268863632391
Short name T436
Test name
Test status
Simulation time 6076748772 ps
CPU time 98.57 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:04:29 PM PST 23
Peak memory 236356 kb
Host smart-67f975cd-1cb5-4b81-b8d6-21d2f68b8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6098748974588369206368983562267835620577967604112477478016151319268863632391 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_app.6098748974588369206368983562267835620577967604112477478016151319268863632391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.94127696652203177346887325877790190890377861750669133070486114258914270797120
Short name T203
Test name
Test status
Simulation time 14830000174 ps
CPU time 389.5 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:09:15 PM PST 23
Peak memory 243216 kb
Host smart-7868b684-83b0-43c6-b387-8d1f86091837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94127696652203177346887325877790190890377861750669133070486114258914270797120 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.kmac_burst_write.94127696652203177346887325877790190890377861750669133070486114258914270797120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.39865423163370882277488106052249932085115641385373000577083510041010098425882
Short name T826
Test name
Test status
Simulation time 7238810904 ps
CPU time 114.28 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:04:44 PM PST 23
Peak memory 243880 kb
Host smart-cd382344-10f7-49e7-8097-72567fc6bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39865423163370882277488106052249932085115641385373000577083510041010098425882 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.kmac_entropy_refresh.39865423163370882277488106052249932085115641385373000577083510041010098425882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.46193047381029478520925246154305784015450501901991767767385781431128150620805
Short name T758
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.98 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:05:15 PM PST 23
Peak memory 252768 kb
Host smart-1db22015-ddce-4f16-91b8-292723b13e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46193047381029478520925246154305784015450501901991767767385781431128150620805 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.kmac_error.46193047381029478520925246154305784015450501901991767767385781431128150620805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.49364801120216658564332494483436706758956208171991631523918338308767521460304
Short name T691
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.82 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 219140 kb
Host smart-48b20057-7a36-47ef-a319-86561ab93756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49364801120216658564332494483436706758956208171991631523918338308767521460304 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.kmac_key_error.49364801120216658564332494483436706758956208171991631523918338308767521460304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.66570152233608401735346019024016935765656962034804827334720952708900110520449
Short name T659
Test name
Test status
Simulation time 72761090 ps
CPU time 1.52 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:02:50 PM PST 23
Peak memory 220512 kb
Host smart-009a62f4-39bf-4b25-a1b3-1dadaf409acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66570152233608401735346019024016935765656962034804827334720952708900110520449 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.kmac_lc_escalation.66570152233608401735346019024016935765656962034804827334720952708900110520449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.115012814311910008435623072623552554051421813763974257640409107429326483883173
Short name T1056
Test name
Test status
Simulation time 50513696845 ps
CPU time 866.75 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:17:00 PM PST 23
Peak memory 306120 kb
Host smart-832cd597-6249-4c9a-9683-87e7486fc762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115012814311910008435623072623552554051421813763974257640409107429326483883173 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.11501281431191000843562307262355255405142181376397425764040910742932
6483883173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.10441872226981301004472429958067768885163369653243976525664645293219189903549
Short name T1034
Test name
Test status
Simulation time 7628111361 ps
CPU time 133.09 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:05:00 PM PST 23
Peak memory 236364 kb
Host smart-e88b19b8-c895-471d-a6ef-ecd2c2499b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10441872226981301004472429958067768885163369653243976525664645293219189903549 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.kmac_sideload.10441872226981301004472429958067768885163369653243976525664645293219189903549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.37725641526198968248607795977338375300387222179709904350774924919151623922980
Short name T385
Test name
Test status
Simulation time 1925406983 ps
CPU time 24.67 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 225176 kb
Host smart-359ce0ee-5413-4961-97e4-dc69e1e46136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37725641526198968248607795977338375300387222179709904350774924919151623922980 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.kmac_smoke.37725641526198968248607795977338375300387222179709904350774924919151623922980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.100646405703759821749185444313386011149521917187403085894656611824569547659177
Short name T858
Test name
Test status
Simulation time 47207151869 ps
CPU time 861.43 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:17:11 PM PST 23
Peak memory 339840 kb
Host smart-e4a609d2-cd19-411a-8732-34da7aa6b275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=100646405703759821749185444313386011149521917187403085894656611824569547659177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_s
tress_all.100646405703759821749185444313386011149521917187403085894656611824569547659177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.114928530529443787780422104676618006338913489662430776292426643929684021366084
Short name T892
Test name
Test status
Simulation time 322955517 ps
CPU time 5.78 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 219260 kb
Host smart-90bfb9f9-6693-47f4-84fb-5005504b4954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492853052944378778042210467661800633891348966243077
6292426643929684021366084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac.1149285305294437877804221046766180063
38913489662430776292426643929684021366084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.23942813612446862033832676487596143926412491960244597256557619179028549685710
Short name T934
Test name
Test status
Simulation time 309259198 ps
CPU time 5.21 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:02:52 PM PST 23
Peak memory 219256 kb
Host smart-3bfaa128-93ac-4369-8d4f-dd3b84347d59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942813612446862033832676487596143926412491960244597
256557619179028549685710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.239428136124468620338326764875
96143926412491960244597256557619179028549685710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.7520594793680034909295787016711309420929711161556738907135496299531100015882
Short name T690
Test name
Test status
Simulation time 117329894454 ps
CPU time 2260.81 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:40:28 PM PST 23
Peak memory 400868 kb
Host smart-19803400-5dae-41e7-b338-16dc17b900a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=7520594793680034909295787016711309420929711161556738907135496299531100015882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
kmac_test_vectors_sha3_224.7520594793680034909295787016711309420929711161556738907135496299531100015882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.53382520372931554256579844542668130699535813671833499383917937653159366822958
Short name T782
Test name
Test status
Simulation time 106843317633 ps
CPU time 1764.57 seconds
Started Nov 22 02:02:39 PM PST 23
Finished Nov 22 02:32:15 PM PST 23
Peak memory 376184 kb
Host smart-8ad1b24a-c836-437b-a587-812a19dadd9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=53382520372931554256579844542668130699535813671833499383917937653159366822958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_256.53382520372931554256579844542668130699535813671833499383917937653159366822958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.42823215674358512354811547917961859563637157778220798737228612067590029243083
Short name T899
Test name
Test status
Simulation time 83520343504 ps
CPU time 1604.68 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:29:34 PM PST 23
Peak memory 338464 kb
Host smart-e7d7ac1a-2a7c-4d4b-a1c2-6d8bc185602a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42823215674358512354811547917961859563637157778220798737228612067590029243083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_384.42823215674358512354811547917961859563637157778220798737228612067590029243083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.62493974548565534520250384265555997063542990219406670940137485721850695868996
Short name T731
Test name
Test status
Simulation time 57499426673 ps
CPU time 1252.19 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:23:43 PM PST 23
Peak memory 297788 kb
Host smart-3c068d6b-0aca-4502-a019-eba656736fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=62493974548565534520250384265555997063542990219406670940137485721850695868996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_512.62493974548565534520250384265555997063542990219406670940137485721850695868996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.74669763268234582858902903625709017138401644661720510099217563082487610180968
Short name T477
Test name
Test status
Simulation time 320694338954 ps
CPU time 5561.6 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 03:35:31 PM PST 23
Peak memory 674348 kb
Host smart-06a623bb-17e6-4a30-8efa-a1d74dd0de24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=74669763268234582858902903625709017138401644661720510099217563082487610180968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_test_vectors_shake_128.74669763268234582858902903625709017138401644661720510099217563082487610180968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.97026953379465277868322205428920609097453335810554489642695984063503722878274
Short name T928
Test name
Test status
Simulation time 270085708112 ps
CPU time 4678.2 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 03:20:46 PM PST 23
Peak memory 577328 kb
Host smart-a8e548f2-dfcf-43a2-a72c-d92dada92eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97026953379465277868322205428920609097453335810554489642695984063503722878274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_test_vectors_shake_256.97026953379465277868322205428920609097453335810554489642695984063503722878274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.47785249621972232118023908398852190643038266752797045463560114340941402610467
Short name T881
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 218972 kb
Host smart-7074e4ac-c430-4fd5-88a8-780046f06eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47785249621972232118023908398852190643038266752797045463560114340941402610467 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.kmac_alert_test.47785249621972232118023908398852190643038266752797045463560114340941402610467 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.100498207600699588231034639618011945826877471113128581314445795798003472910103
Short name T830
Test name
Test status
Simulation time 6076748772 ps
CPU time 100.1 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:04:58 PM PST 23
Peak memory 236208 kb
Host smart-d3c862b6-d3f7-46fd-b1ab-95b82b29b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100498207600699588231034639618011945826877471113128581314445795798003472910103 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.kmac_app.100498207600699588231034639618011945826877471113128581314445795798003472910103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.88980943835937113935970817963963698973841144507881020754453323484666877092007
Short name T587
Test name
Test status
Simulation time 14830000174 ps
CPU time 383.82 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:09:11 PM PST 23
Peak memory 243212 kb
Host smart-6640cbdc-c1fa-46ab-b8a7-698c3c8b03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88980943835937113935970817963963698973841144507881020754453323484666877092007 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.kmac_burst_write.88980943835937113935970817963963698973841144507881020754453323484666877092007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.80185328306966477988457260169642266466549418276282790340583351410288245466060
Short name T228
Test name
Test status
Simulation time 7238810904 ps
CPU time 112.92 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:05:11 PM PST 23
Peak memory 243892 kb
Host smart-36a22561-9695-4431-a58b-d748c7693a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80185328306966477988457260169642266466549418276282790340583351410288245466060 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.kmac_entropy_refresh.80185328306966477988457260169642266466549418276282790340583351410288245466060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.22786539745452985293944097265336441790436285536835030315577092746618711624455
Short name T637
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.29 seconds
Started Nov 22 02:03:15 PM PST 23
Finished Nov 22 02:05:40 PM PST 23
Peak memory 252724 kb
Host smart-3fbe1be9-9fde-4c8a-aef1-79fa0d8c863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22786539745452985293944097265336441790436285536835030315577092746618711624455 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.kmac_error.22786539745452985293944097265336441790436285536835030315577092746618711624455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.89990792703833547442871854123835522454860320806195199604150101259469696868943
Short name T551
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.75 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 219224 kb
Host smart-95959626-e980-4cb0-aa73-0f0a4c30ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89990792703833547442871854123835522454860320806195199604150101259469696868943 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.kmac_key_error.89990792703833547442871854123835522454860320806195199604150101259469696868943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.36182578623430237703519365786918666626915872986785631482339314429946981907940
Short name T377
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 220424 kb
Host smart-6cd59b87-3927-4d7a-9e91-417e16a0d478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36182578623430237703519365786918666626915872986785631482339314429946981907940 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.kmac_lc_escalation.36182578623430237703519365786918666626915872986785631482339314429946981907940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.38808451959064911297311206181657389029982755969293427230109473339028164734920
Short name T975
Test name
Test status
Simulation time 50513696845 ps
CPU time 1048.92 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:20:19 PM PST 23
Peak memory 306324 kb
Host smart-3525f6f9-8101-489e-a89c-0d688878912a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808451959064911297311206181657389029982755969293427230109473339028164734920 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.388084519590649112973112061816573890299827559692934272301094733390281
64734920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.57340318191938898057224294789285346138991037818989437132593356972909103568552
Short name T1062
Test name
Test status
Simulation time 7628111361 ps
CPU time 136.3 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:05:04 PM PST 23
Peak memory 236400 kb
Host smart-4b8e40e5-c08a-42c9-87af-37bd56c5104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57340318191938898057224294789285346138991037818989437132593356972909103568552 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.kmac_sideload.57340318191938898057224294789285346138991037818989437132593356972909103568552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.112643466277366739014884412615806281199749414228486727811211555810406017546211
Short name T195
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.94 seconds
Started Nov 22 02:02:35 PM PST 23
Finished Nov 22 02:03:13 PM PST 23
Peak memory 225336 kb
Host smart-a4d55f59-762f-4062-8479-35ae7060ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112643466277366739014884412615806281199749414228486727811211555810406017546211 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.kmac_smoke.112643466277366739014884412615806281199749414228486727811211555810406017546211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.74480825166609958696797426555349288693334579989631470857864458590872521788613
Short name T594
Test name
Test status
Simulation time 47207151869 ps
CPU time 912.87 seconds
Started Nov 22 02:03:18 PM PST 23
Finished Nov 22 02:18:33 PM PST 23
Peak memory 339820 kb
Host smart-00d4b6d0-f670-4d04-a91a-9fa111a7086b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=74480825166609958696797426555349288693334579989631470857864458590872521788613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_st
ress_all.74480825166609958696797426555349288693334579989631470857864458590872521788613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.64696666908427446714017170906164593974591671791741526538132269677797908342526
Short name T1013
Test name
Test status
Simulation time 322955517 ps
CPU time 5.71 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 219284 kb
Host smart-130f9581-a8af-42ef-9a17-0d9a1dc61e83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64696666908427446714017170906164593974591671791741526
538132269677797908342526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac.64696666908427446714017170906164593974
591671791741526538132269677797908342526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.61995815390843074988475300163416625567560393780636549150672393566906134118071
Short name T688
Test name
Test status
Simulation time 309259198 ps
CPU time 5.93 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 219204 kb
Host smart-6181b740-6fe9-4647-87f7-061228694bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61995815390843074988475300163416625567560393780636549
150672393566906134118071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.619958153908430749884753001634
16625567560393780636549150672393566906134118071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.55725880587984572152151405275786148583006449697786657728392963091422431185489
Short name T846
Test name
Test status
Simulation time 117329894454 ps
CPU time 2127.73 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:38:17 PM PST 23
Peak memory 400792 kb
Host smart-4f0ae85d-abf3-4b5d-828a-b44f55d2b7fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55725880587984572152151405275786148583006449697786657728392963091422431185489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_224.55725880587984572152151405275786148583006449697786657728392963091422431185489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.103937774933249664607285393580785090983654210700897069957246597568744404064582
Short name T936
Test name
Test status
Simulation time 106843317633 ps
CPU time 1925.41 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:34:54 PM PST 23
Peak memory 376376 kb
Host smart-ae43aafe-a1f0-4694-9a23-89a547aa6cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=103937774933249664607285393580785090983654210700897069957246597568744404064582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.kmac_test_vectors_sha3_256.103937774933249664607285393580785090983654210700897069957246597568744404064582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.55605557223443916677580964915410693411012956630637449816159033561341334663477
Short name T408
Test name
Test status
Simulation time 83520343504 ps
CPU time 1596.97 seconds
Started Nov 22 02:02:38 PM PST 23
Finished Nov 22 02:29:27 PM PST 23
Peak memory 338444 kb
Host smart-5e4f8b89-9a4d-4ee1-b855-196e0f063c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55605557223443916677580964915410693411012956630637449816159033561341334663477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_384.55605557223443916677580964915410693411012956630637449816159033561341334663477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.22486699533210617283915280986463455162178652725747240181218459701830509920038
Short name T754
Test name
Test status
Simulation time 57499426673 ps
CPU time 1187.09 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 297760 kb
Host smart-b68dbcac-ef01-4193-8640-1028d7b76622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=22486699533210617283915280986463455162178652725747240181218459701830509920038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_512.22486699533210617283915280986463455162178652725747240181218459701830509920038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.42841942763479128589420514124000278152174760613049871034220112793079695285460
Short name T872
Test name
Test status
Simulation time 320694338954 ps
CPU time 5332.83 seconds
Started Nov 22 02:02:36 PM PST 23
Finished Nov 22 03:31:42 PM PST 23
Peak memory 674236 kb
Host smart-4d2ded35-4b16-4db5-9ff2-bf205646a802
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42841942763479128589420514124000278152174760613049871034220112793079695285460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.kmac_test_vectors_shake_128.42841942763479128589420514124000278152174760613049871034220112793079695285460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.34958149725834811134560337334297358570631448263337228005659533817064116552128
Short name T909
Test name
Test status
Simulation time 270085708112 ps
CPU time 4642.1 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 03:20:40 PM PST 23
Peak memory 577448 kb
Host smart-e3f9f8b0-36e3-4fad-b59b-75dff96d6dfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=34958149725834811134560337334297358570631448263337228005659533817064116552128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.kmac_test_vectors_shake_256.34958149725834811134560337334297358570631448263337228005659533817064116552128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3185995933246311987278337920624080290031729690820634946748530235968861232138
Short name T172
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:03:48 PM PST 23
Peak memory 218888 kb
Host smart-e6dac7e6-e9ce-4d58-b129-75b013d0d492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185995933246311987278337920624080290031729690820634946748530235968861232138 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.kmac_alert_test.3185995933246311987278337920624080290031729690820634946748530235968861232138 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.75764492907527525044820410208884749134998766926314833059655477502121698126521
Short name T957
Test name
Test status
Simulation time 6076748772 ps
CPU time 97.94 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:04:57 PM PST 23
Peak memory 236104 kb
Host smart-f91a6d2c-a7fc-4138-97e7-9d5cbc9d2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75764492907527525044820410208884749134998766926314833059655477502121698126521 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_app.75764492907527525044820410208884749134998766926314833059655477502121698126521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.51122629520735781192750749494775050694614253243139093623244890918333095954255
Short name T198
Test name
Test status
Simulation time 14830000174 ps
CPU time 418.89 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:10:16 PM PST 23
Peak memory 243260 kb
Host smart-ce0a6d43-0ecf-42ef-a6e9-4fcf0577c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51122629520735781192750749494775050694614253243139093623244890918333095954255 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.kmac_burst_write.51122629520735781192750749494775050694614253243139093623244890918333095954255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.19720517016072200439595028018577916022345447795591385916797520207362323814165
Short name T598
Test name
Test status
Simulation time 7238810904 ps
CPU time 111.13 seconds
Started Nov 22 02:03:18 PM PST 23
Finished Nov 22 02:05:10 PM PST 23
Peak memory 243920 kb
Host smart-98eb0ee8-8ea5-4047-867f-67163a7e7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19720517016072200439595028018577916022345447795591385916797520207362323814165 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.kmac_entropy_refresh.19720517016072200439595028018577916022345447795591385916797520207362323814165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.42610678227206058960009498542701219733636003406204856781069347530912240650497
Short name T591
Test name
Test status
Simulation time 8137821569 ps
CPU time 146.82 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:06:15 PM PST 23
Peak memory 252784 kb
Host smart-ad17d413-0615-4ca5-af37-d3a036835eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42610678227206058960009498542701219733636003406204856781069347530912240650497 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.kmac_error.42610678227206058960009498542701219733636003406204856781069347530912240650497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.32484028781081173867860122689670052561524720241976354560331729034173593160545
Short name T443
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.76 seconds
Started Nov 22 02:03:32 PM PST 23
Finished Nov 22 02:03:39 PM PST 23
Peak memory 219300 kb
Host smart-4563748f-a219-4feb-8151-19e107848b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32484028781081173867860122689670052561524720241976354560331729034173593160545 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.kmac_key_error.32484028781081173867860122689670052561524720241976354560331729034173593160545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.53511189866427426421114703816203606436463014333644433409048251385149780414014
Short name T665
Test name
Test status
Simulation time 72761090 ps
CPU time 1.48 seconds
Started Nov 22 02:03:45 PM PST 23
Finished Nov 22 02:03:47 PM PST 23
Peak memory 220368 kb
Host smart-1f820feb-a21c-4ab8-80dd-ce873f6d53b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53511189866427426421114703816203606436463014333644433409048251385149780414014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.kmac_lc_escalation.53511189866427426421114703816203606436463014333644433409048251385149780414014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.56082540984124117454990501946087331763045602352252421284829345686164224157573
Short name T741
Test name
Test status
Simulation time 50513696845 ps
CPU time 1031.98 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:21:00 PM PST 23
Peak memory 306256 kb
Host smart-cda93f50-5462-45c2-85a0-1ca1092065b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56082540984124117454990501946087331763045602352252421284829345686164224157573 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.560825409841241174549905019460873317630456023522524212848293456861642
24157573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.89701703711364316069775543929766239920216294687719301842655891366837554675753
Short name T625
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.39 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:05:37 PM PST 23
Peak memory 236380 kb
Host smart-0b2759c1-6378-4a5c-9e25-9ec4dc9e7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89701703711364316069775543929766239920216294687719301842655891366837554675753 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.kmac_sideload.89701703711364316069775543929766239920216294687719301842655891366837554675753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.10184735847660122051006322099530910520915212929143951405644213746614909045444
Short name T641
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.05 seconds
Started Nov 22 02:03:18 PM PST 23
Finished Nov 22 02:03:45 PM PST 23
Peak memory 225384 kb
Host smart-1e85f986-3370-4023-9fb2-43ab7c13e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10184735847660122051006322099530910520915212929143951405644213746614909045444 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.kmac_smoke.10184735847660122051006322099530910520915212929143951405644213746614909045444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.71100380973371743890238779972025538254136335683797232215007991678272958796568
Short name T347
Test name
Test status
Simulation time 47207151869 ps
CPU time 872.05 seconds
Started Nov 22 02:03:30 PM PST 23
Finished Nov 22 02:18:02 PM PST 23
Peak memory 339828 kb
Host smart-955969a3-2477-4f57-974f-0a36ef4a062e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=71100380973371743890238779972025538254136335683797232215007991678272958796568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_st
ress_all.71100380973371743890238779972025538254136335683797232215007991678272958796568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.26517646748542462282705155461433580320583415143262403244733255131800713876860
Short name T1030
Test name
Test status
Simulation time 322955517 ps
CPU time 6.15 seconds
Started Nov 22 02:03:15 PM PST 23
Finished Nov 22 02:03:22 PM PST 23
Peak memory 219248 kb
Host smart-40f700d8-9e95-4b87-85e3-33fcb569ebf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517646748542462282705155461433580320583415143262403
244733255131800713876860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac.26517646748542462282705155461433580320
583415143262403244733255131800713876860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.91136245308562026880406248168725257104652903441385055835921400314599460506795
Short name T904
Test name
Test status
Simulation time 309259198 ps
CPU time 5.68 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:03:23 PM PST 23
Peak memory 219192 kb
Host smart-6db9e806-e8c1-4b48-a43d-c76f52965803
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91136245308562026880406248168725257104652903441385055
835921400314599460506795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.911362453085620268804062481687
25257104652903441385055835921400314599460506795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.115417753171588720194727919440471558394209470776093038200777238672099479669326
Short name T704
Test name
Test status
Simulation time 117329894454 ps
CPU time 2033.27 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:37:27 PM PST 23
Peak memory 400892 kb
Host smart-e36d16a7-1c02-484e-bc79-74ad6825e927
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=115417753171588720194727919440471558394209470776093038200777238672099479669326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.kmac_test_vectors_sha3_224.115417753171588720194727919440471558394209470776093038200777238672099479669326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.23454224270222643944914967315227833103380704042078198834976788529378201705089
Short name T806
Test name
Test status
Simulation time 106843317633 ps
CPU time 1966.02 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:36:03 PM PST 23
Peak memory 376496 kb
Host smart-57654436-4d1c-4c9a-a00d-67f7a2a72018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=23454224270222643944914967315227833103380704042078198834976788529378201705089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.kmac_test_vectors_sha3_256.23454224270222643944914967315227833103380704042078198834976788529378201705089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.58480839047168541095912616367540575197124011621293069228801058187523817176216
Short name T951
Test name
Test status
Simulation time 83520343504 ps
CPU time 1641.63 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:30:56 PM PST 23
Peak memory 338452 kb
Host smart-2e469c12-64ac-482c-a742-b742eae7ce9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=58480839047168541095912616367540575197124011621293069228801058187523817176216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.kmac_test_vectors_sha3_384.58480839047168541095912616367540575197124011621293069228801058187523817176216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.101020463316505923288627074113283814264199205617968778958021627298868904188661
Short name T445
Test name
Test status
Simulation time 57499426673 ps
CPU time 1237.81 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:23:56 PM PST 23
Peak memory 297808 kb
Host smart-c645094b-7615-4c62-8349-b8bd04b8737d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101020463316505923288627074113283814264199205617968778958021627298868904188661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.kmac_test_vectors_sha3_512.101020463316505923288627074113283814264199205617968778958021627298868904188661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.12187759113741229403612540477767418642207864365760756755188740034784680360779
Short name T917
Test name
Test status
Simulation time 320694338954 ps
CPU time 5214.77 seconds
Started Nov 22 02:03:18 PM PST 23
Finished Nov 22 03:30:14 PM PST 23
Peak memory 674260 kb
Host smart-edeed336-4199-431a-9291-0c398aab9777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=12187759113741229403612540477767418642207864365760756755188740034784680360779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_test_vectors_shake_128.12187759113741229403612540477767418642207864365760756755188740034784680360779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.88757685862744683648843928743497020604621880866665863568741765781891056156368
Short name T720
Test name
Test status
Simulation time 270085708112 ps
CPU time 4717.64 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 03:21:57 PM PST 23
Peak memory 577380 kb
Host smart-fd76d0c8-1979-4958-bf9a-01ffa5ddbd1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=88757685862744683648843928743497020604621880866665863568741765781891056156368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_test_vectors_shake_256.88757685862744683648843928743497020604621880866665863568741765781891056156368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.99634052433355446546742474511156650328958397322992954882373436307813791949880
Short name T880
Test name
Test status
Simulation time 21118646 ps
CPU time 0.86 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:00 PM PST 23
Peak memory 219084 kb
Host smart-66b795d7-5a47-4af4-b7ce-872a52c7b389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99634052433355446546742474511156650328958397322992954882373436307813791949880 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.kmac_alert_test.99634052433355446546742474511156650328958397322992954882373436307813791949880 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.9618392979541520676286534301920822036682155212482758500349438273168320971782
Short name T171
Test name
Test status
Simulation time 6076748772 ps
CPU time 98.74 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:05:40 PM PST 23
Peak memory 236240 kb
Host smart-b77f7eec-b253-4508-9fcc-4efc8c78dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9618392979541520676286534301920822036682155212482758500349438273168320971782 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_app.9618392979541520676286534301920822036682155212482758500349438273168320971782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.37530648871627258611511348642668324830693935028080640643835841500843970949186
Short name T572
Test name
Test status
Simulation time 14830000174 ps
CPU time 391.89 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:10:06 PM PST 23
Peak memory 243188 kb
Host smart-edb5f3f3-f340-47c9-8de4-27608b809a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37530648871627258611511348642668324830693935028080640643835841500843970949186 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.kmac_burst_write.37530648871627258611511348642668324830693935028080640643835841500843970949186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.48130215727132154222386870484248644699814878040929019163511724944674411569915
Short name T784
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.4 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:05:47 PM PST 23
Peak memory 243908 kb
Host smart-29aaad4a-25ec-4b6e-9866-a41b956970c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48130215727132154222386870484248644699814878040929019163511724944674411569915 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.kmac_entropy_refresh.48130215727132154222386870484248644699814878040929019163511724944674411569915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.74428829671293120912166583884669940164517389749955050120822380711003301291344
Short name T266
Test name
Test status
Simulation time 8137821569 ps
CPU time 136.08 seconds
Started Nov 22 02:03:56 PM PST 23
Finished Nov 22 02:06:13 PM PST 23
Peak memory 252656 kb
Host smart-c3928459-b0b0-4123-9f33-42c59429cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74428829671293120912166583884669940164517389749955050120822380711003301291344 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.kmac_error.74428829671293120912166583884669940164517389749955050120822380711003301291344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.20671401930936081913765449177354373773149326658500747138482426724942458001997
Short name T564
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.68 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 219236 kb
Host smart-ead04669-5d93-4ca2-a7e7-2934c4198a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20671401930936081913765449177354373773149326658500747138482426724942458001997 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.kmac_key_error.20671401930936081913765449177354373773149326658500747138482426724942458001997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.97282653110089630402784618320043721559583674757922981716549259822932824852210
Short name T191
Test name
Test status
Simulation time 72761090 ps
CPU time 1.57 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 220500 kb
Host smart-6d1f1fe1-5bdb-466c-82da-42204e1d121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97282653110089630402784618320043721559583674757922981716549259822932824852210 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.kmac_lc_escalation.97282653110089630402784618320043721559583674757922981716549259822932824852210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.48112621825819244835780304471311816009510259088563677038797314333677853834802
Short name T988
Test name
Test status
Simulation time 50513696845 ps
CPU time 998.94 seconds
Started Nov 22 02:03:34 PM PST 23
Finished Nov 22 02:20:14 PM PST 23
Peak memory 306376 kb
Host smart-478e6dca-6493-40bf-a7ce-dfa543b08037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48112621825819244835780304471311816009510259088563677038797314333677853834802 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.481126218258192448357803044713118160095102590885636770387973143336778
53834802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.114724723252907449134668878878948772313613809933342125151404572856494495883628
Short name T361
Test name
Test status
Simulation time 7628111361 ps
CPU time 138.12 seconds
Started Nov 22 02:03:31 PM PST 23
Finished Nov 22 02:05:50 PM PST 23
Peak memory 236328 kb
Host smart-3dfc6989-26f9-4b15-9500-9745c5119be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114724723252907449134668878878948772313613809933342125151404572856494495883628 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.kmac_sideload.114724723252907449134668878878948772313613809933342125151404572856494495883628 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.98259177461711477101488711996332444527113413748241025857032601757411974909148
Short name T575
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.96 seconds
Started Nov 22 02:03:30 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 225496 kb
Host smart-195dd16c-b318-4fb9-bfd9-53255130a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98259177461711477101488711996332444527113413748241025857032601757411974909148 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.kmac_smoke.98259177461711477101488711996332444527113413748241025857032601757411974909148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.5379353124226030131127511421315535419919868650076834014945472103804811340586
Short name T961
Test name
Test status
Simulation time 47207151869 ps
CPU time 898.25 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 339708 kb
Host smart-a12b66a5-3472-4a59-989e-e190d991b00f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=5379353124226030131127511421315535419919868650076834014945472103804811340586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_str
ess_all.5379353124226030131127511421315535419919868650076834014945472103804811340586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.104729926896262508225490334216585711942860202285944420592856039382387807757002
Short name T1014
Test name
Test status
Simulation time 322955517 ps
CPU time 5.9 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 219180 kb
Host smart-a50ae6e4-0890-497c-afc2-80b3d2cfe244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472992689626250822549033421658571194286020228594442
0592856039382387807757002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac.1047299268962625082254903342165857119
42860202285944420592856039382387807757002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.98769779825889729838792980167451478444573603193325851983443481424897001251919
Short name T608
Test name
Test status
Simulation time 309259198 ps
CPU time 5.72 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 219252 kb
Host smart-b43eb6c9-8f52-4fa4-ad10-9169b1cd1f7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98769779825889729838792980167451478444573603193325851
983443481424897001251919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.987697798258897298387929801674
51478444573603193325851983443481424897001251919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.106531151196423793063375698119531239884711487685561634024279250311922754681220
Short name T852
Test name
Test status
Simulation time 117329894454 ps
CPU time 2157.16 seconds
Started Nov 22 02:03:49 PM PST 23
Finished Nov 22 02:39:47 PM PST 23
Peak memory 400856 kb
Host smart-895afa1c-b1a0-44e9-8f80-01d9a2f11fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=106531151196423793063375698119531239884711487685561634024279250311922754681220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.kmac_test_vectors_sha3_224.106531151196423793063375698119531239884711487685561634024279250311922754681220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.77323740068734653767357463793408649915940880444984687290904410985742622468739
Short name T189
Test name
Test status
Simulation time 106843317633 ps
CPU time 1928.63 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:35:43 PM PST 23
Peak memory 376408 kb
Host smart-8dcd02dc-c25c-45b1-a21b-1f86f08c84e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77323740068734653767357463793408649915940880444984687290904410985742622468739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_256.77323740068734653767357463793408649915940880444984687290904410985742622468739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.87292845249225485441730103232819153893397599319091178017525172147625582228536
Short name T561
Test name
Test status
Simulation time 83520343504 ps
CPU time 1631.85 seconds
Started Nov 22 02:03:49 PM PST 23
Finished Nov 22 02:31:01 PM PST 23
Peak memory 338432 kb
Host smart-ef8a7352-48cb-445c-a833-58cf6484225a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=87292845249225485441730103232819153893397599319091178017525172147625582228536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_384.87292845249225485441730103232819153893397599319091178017525172147625582228536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.66487990392480629411224976749932200456967808019721102869288664552685082590779
Short name T723
Test name
Test status
Simulation time 57499426673 ps
CPU time 1193.36 seconds
Started Nov 22 02:03:49 PM PST 23
Finished Nov 22 02:23:43 PM PST 23
Peak memory 297788 kb
Host smart-7f169670-8a71-46a0-9eb6-58c0154f439a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=66487990392480629411224976749932200456967808019721102869288664552685082590779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_512.66487990392480629411224976749932200456967808019721102869288664552685082590779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.26956839524033258347827469323754800876388608383651871906556448744799434065548
Short name T499
Test name
Test status
Simulation time 320694338954 ps
CPU time 5317.23 seconds
Started Nov 22 02:03:49 PM PST 23
Finished Nov 22 03:32:27 PM PST 23
Peak memory 674296 kb
Host smart-3852ef18-31df-4d1b-88fa-3ba606a6e3de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=26956839524033258347827469323754800876388608383651871906556448744799434065548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_test_vectors_shake_128.26956839524033258347827469323754800876388608383651871906556448744799434065548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.72676094630957927275604737987457141413467616531992352704184222311675628799160
Short name T894
Test name
Test status
Simulation time 270085708112 ps
CPU time 4702.91 seconds
Started Nov 22 02:03:50 PM PST 23
Finished Nov 22 03:22:15 PM PST 23
Peak memory 577372 kb
Host smart-94119bbf-169b-4831-9c8e-205414e503f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=72676094630957927275604737987457141413467616531992352704184222311675628799160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_test_vectors_shake_256.72676094630957927275604737987457141413467616531992352704184222311675628799160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.71489467434602929142814831626743432349515948459557038097764944501150030202247
Short name T451
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:03:31 PM PST 23
Finished Nov 22 02:03:33 PM PST 23
Peak memory 219000 kb
Host smart-4842ee59-d1ab-46b5-b130-cff36f8990c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71489467434602929142814831626743432349515948459557038097764944501150030202247 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.kmac_alert_test.71489467434602929142814831626743432349515948459557038097764944501150030202247 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.70940940385961645964412908784215349434992058957400515892560774363994605984923
Short name T1072
Test name
Test status
Simulation time 6076748772 ps
CPU time 103.3 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:05:00 PM PST 23
Peak memory 236200 kb
Host smart-e27c3c5c-d839-41cd-abc0-e37d9696767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70940940385961645964412908784215349434992058957400515892560774363994605984923 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_app.70940940385961645964412908784215349434992058957400515892560774363994605984923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.28350688136269532736215670628957718115636928791796024365837964126930349393612
Short name T163
Test name
Test status
Simulation time 14830000174 ps
CPU time 390.71 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:10:35 PM PST 23
Peak memory 243220 kb
Host smart-b3988f7e-89cd-4d92-b6bd-3aeca287854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28350688136269532736215670628957718115636928791796024365837964126930349393612 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.kmac_burst_write.28350688136269532736215670628957718115636928791796024365837964126930349393612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.111660033671028940213144216808269935106826434703767559787884452754055861127526
Short name T768
Test name
Test status
Simulation time 7238810904 ps
CPU time 107.29 seconds
Started Nov 22 02:03:15 PM PST 23
Finished Nov 22 02:05:02 PM PST 23
Peak memory 243968 kb
Host smart-95661de4-7cdc-4119-a384-674c643236c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111660033671028940213144216808269935106826434703767559787884452754055861127526 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_entropy_refresh.111660033671028940213144216808269935106826434703767559787884452754055861127526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.98104416009063813702356893583309967155030948443092864958866322141642732752589
Short name T297
Test name
Test status
Simulation time 8137821569 ps
CPU time 137.87 seconds
Started Nov 22 02:03:32 PM PST 23
Finished Nov 22 02:05:51 PM PST 23
Peak memory 252712 kb
Host smart-e93159bf-36bf-4ebe-aa5f-bff71f441d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98104416009063813702356893583309967155030948443092864958866322141642732752589 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.kmac_error.98104416009063813702356893583309967155030948443092864958866322141642732752589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.78693639577899106024186620739411793903269923524718208259777080869943078956162
Short name T915
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.95 seconds
Started Nov 22 02:03:48 PM PST 23
Finished Nov 22 02:03:55 PM PST 23
Peak memory 219156 kb
Host smart-662ff28d-b589-4935-9dd4-18320ef2ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78693639577899106024186620739411793903269923524718208259777080869943078956162 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.kmac_key_error.78693639577899106024186620739411793903269923524718208259777080869943078956162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.33594766266458282389251386686713913410099210134712778282524617039484463466286
Short name T332
Test name
Test status
Simulation time 72761090 ps
CPU time 1.52 seconds
Started Nov 22 02:03:31 PM PST 23
Finished Nov 22 02:03:34 PM PST 23
Peak memory 220500 kb
Host smart-3f563bb7-4fae-406d-b8fe-8b93edf9aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33594766266458282389251386686713913410099210134712778282524617039484463466286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.kmac_lc_escalation.33594766266458282389251386686713913410099210134712778282524617039484463466286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.38850588464689845390799368834727483242619968893917882422046043031651647042620
Short name T1005
Test name
Test status
Simulation time 50513696845 ps
CPU time 996.17 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:20:38 PM PST 23
Peak memory 306316 kb
Host smart-1e5c7fc9-8b47-4e57-b19f-7c69f0ac51ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38850588464689845390799368834727483242619968893917882422046043031651647042620 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.388505884646898453907993688347274832426199688939178824220460430316516
47042620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.61870660516448727173784780679790095044058887801154371798094030044104577197514
Short name T300
Test name
Test status
Simulation time 7628111361 ps
CPU time 134.93 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:06:18 PM PST 23
Peak memory 236388 kb
Host smart-4a4145dc-3b1e-4e8d-b0d1-23e507726dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61870660516448727173784780679790095044058887801154371798094030044104577197514 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.kmac_sideload.61870660516448727173784780679790095044058887801154371798094030044104577197514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.17281390908353786235428663095743320809808633752332560053813038984925858587182
Short name T786
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.79 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:24 PM PST 23
Peak memory 225260 kb
Host smart-07481e44-96c7-4920-a2a3-0f4faabbe600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17281390908353786235428663095743320809808633752332560053813038984925858587182 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.kmac_smoke.17281390908353786235428663095743320809808633752332560053813038984925858587182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.23724771948048397760241766986985036852552140583951628036525818811641779620466
Short name T694
Test name
Test status
Simulation time 47207151869 ps
CPU time 914.08 seconds
Started Nov 22 02:03:31 PM PST 23
Finished Nov 22 02:18:46 PM PST 23
Peak memory 339720 kb
Host smart-76624584-6e96-43d2-97c1-484bdb02baa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=23724771948048397760241766986985036852552140583951628036525818811641779620466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_st
ress_all.23724771948048397760241766986985036852552140583951628036525818811641779620466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.53969615100336644860423795907493055429581188658104884321372578428648770062956
Short name T812
Test name
Test status
Simulation time 322955517 ps
CPU time 5.75 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:04:06 PM PST 23
Peak memory 219176 kb
Host smart-1a433580-81e6-4f28-bff0-1e026dd2cc51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53969615100336644860423795907493055429581188658104884
321372578428648770062956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac.53969615100336644860423795907493055429
581188658104884321372578428648770062956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.41540502749982026396481512217763568074280681472837431797045248887587340210190
Short name T775
Test name
Test status
Simulation time 309259198 ps
CPU time 5.9 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 219160 kb
Host smart-8572b9ba-c6b2-4822-8c0c-28266449d42b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540502749982026396481512217763568074280681472837431
797045248887587340210190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.415405027499820263964815122177
63568074280681472837431797045248887587340210190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.55443160113300263458332390782630224076060966123722465368656772228991140392918
Short name T175
Test name
Test status
Simulation time 117329894454 ps
CPU time 2170.68 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:40:10 PM PST 23
Peak memory 400792 kb
Host smart-5ebe173e-fc64-4972-9e90-5ea31928b7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55443160113300263458332390782630224076060966123722465368656772228991140392918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_224.55443160113300263458332390782630224076060966123722465368656772228991140392918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.62027331575432962812074163981084409016282229637812510205309817598011917011048
Short name T128
Test name
Test status
Simulation time 106843317633 ps
CPU time 1897.79 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:35:36 PM PST 23
Peak memory 376496 kb
Host smart-d682d64e-8ec8-4fed-a30d-900f705d1f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=62027331575432962812074163981084409016282229637812510205309817598011917011048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_256.62027331575432962812074163981084409016282229637812510205309817598011917011048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.30654336825272269651505416645028344566145861256517170858842824015968142739785
Short name T371
Test name
Test status
Simulation time 83520343504 ps
CPU time 1603.51 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:30:45 PM PST 23
Peak memory 338472 kb
Host smart-81912cc5-f0e7-4197-8294-0cf5d6a8d429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30654336825272269651505416645028344566145861256517170858842824015968142739785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_384.30654336825272269651505416645028344566145861256517170858842824015968142739785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.79377307365384385785190969046268033024391553076678121802736909362016108082060
Short name T276
Test name
Test status
Simulation time 57499426673 ps
CPU time 1236.54 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:24:38 PM PST 23
Peak memory 297784 kb
Host smart-53752354-6379-49d7-89fe-9fd734e05ba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79377307365384385785190969046268033024391553076678121802736909362016108082060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_512.79377307365384385785190969046268033024391553076678121802736909362016108082060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.83681495701955499110880509909503294607546264348805355046280978400637079475762
Short name T155
Test name
Test status
Simulation time 320694338954 ps
CPU time 5356.47 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 03:33:21 PM PST 23
Peak memory 674280 kb
Host smart-0b2e71bc-f63e-42d0-8a45-c886ca6ca033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=83681495701955499110880509909503294607546264348805355046280978400637079475762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_test_vectors_shake_128.83681495701955499110880509909503294607546264348805355046280978400637079475762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.18052407356743241157325688499498491864356634153431620222578838126470398450197
Short name T552
Test name
Test status
Simulation time 270085708112 ps
CPU time 4565.53 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 03:20:10 PM PST 23
Peak memory 577384 kb
Host smart-71211aef-f62f-4b39-8f02-eb11931e23a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=18052407356743241157325688499498491864356634153431620222578838126470398450197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_test_vectors_shake_256.18052407356743241157325688499498491864356634153431620222578838126470398450197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.99805346324667607862164265016204895813882756787527712499484911555502454803483
Short name T75
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:03:52 PM PST 23
Finished Nov 22 02:03:54 PM PST 23
Peak memory 219004 kb
Host smart-3973bad5-b53e-4d16-95d4-2141a17ae150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99805346324667607862164265016204895813882756787527712499484911555502454803483 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.kmac_alert_test.99805346324667607862164265016204895813882756787527712499484911555502454803483 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.86636992909565542693530991233111065273855404142923273785587231558973761139004
Short name T381
Test name
Test status
Simulation time 6076748772 ps
CPU time 102.23 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:05:30 PM PST 23
Peak memory 236232 kb
Host smart-ef821393-2d30-4409-a611-a6deca3b310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86636992909565542693530991233111065273855404142923273785587231558973761139004 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_app.86636992909565542693530991233111065273855404142923273785587231558973761139004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.97757790007679533319581409270904215272156683821243260835113298195254130665963
Short name T341
Test name
Test status
Simulation time 14830000174 ps
CPU time 405.98 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:10:04 PM PST 23
Peak memory 243236 kb
Host smart-23fc7d85-30eb-4141-83e5-70f35425f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97757790007679533319581409270904215272156683821243260835113298195254130665963 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.kmac_burst_write.97757790007679533319581409270904215272156683821243260835113298195254130665963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.33166996571326260075530811513048561217966212282392448191401100345553678179920
Short name T878
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.97 seconds
Started Nov 22 02:03:48 PM PST 23
Finished Nov 22 02:05:38 PM PST 23
Peak memory 243856 kb
Host smart-280ef7f9-b472-4bea-8d44-75dab2926ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33166996571326260075530811513048561217966212282392448191401100345553678179920 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.kmac_entropy_refresh.33166996571326260075530811513048561217966212282392448191401100345553678179920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.87813074972520214148308594647715787394440935820213368287431957765060579395233
Short name T981
Test name
Test status
Simulation time 8137821569 ps
CPU time 135.73 seconds
Started Nov 22 02:03:48 PM PST 23
Finished Nov 22 02:06:05 PM PST 23
Peak memory 252752 kb
Host smart-2e197e91-9cf8-4753-bf6f-75d2a7bd5e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87813074972520214148308594647715787394440935820213368287431957765060579395233 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.kmac_error.87813074972520214148308594647715787394440935820213368287431957765060579395233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.11246413709056483958996191459811867311692330902481896080495909570446531378245
Short name T977
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.77 seconds
Started Nov 22 02:03:48 PM PST 23
Finished Nov 22 02:03:54 PM PST 23
Peak memory 219232 kb
Host smart-44b184ee-bd07-43a1-9eae-2cd28a219870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11246413709056483958996191459811867311692330902481896080495909570446531378245 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.kmac_key_error.11246413709056483958996191459811867311692330902481896080495909570446531378245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.9288555165205548024852882439298602159318671458128010579165723493666693393284
Short name T233
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:03:34 PM PST 23
Finished Nov 22 02:03:36 PM PST 23
Peak memory 220504 kb
Host smart-49423567-a127-4867-ac47-e24f5e076128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9288555165205548024852882439298602159318671458128010579165723493666693393284 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.kmac_lc_escalation.9288555165205548024852882439298602159318671458128010579165723493666693393284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.96884063125998672894558303351154458319368504470859898799349933021693245437786
Short name T269
Test name
Test status
Simulation time 50513696845 ps
CPU time 977.4 seconds
Started Nov 22 02:03:15 PM PST 23
Finished Nov 22 02:19:33 PM PST 23
Peak memory 306308 kb
Host smart-17c010e0-3055-49a2-b3f4-275a7ab33879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96884063125998672894558303351154458319368504470859898799349933021693245437786 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.968840631259986728945583033511544583193685044708598987993499330216932
45437786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.25134018112959168626455777521170227787560722821462484621089704050013766682095
Short name T752
Test name
Test status
Simulation time 7628111361 ps
CPU time 142.97 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:05:41 PM PST 23
Peak memory 236288 kb
Host smart-4c2f5bf8-8a96-4f3c-bd56-aeee2d2fdffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25134018112959168626455777521170227787560722821462484621089704050013766682095 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.kmac_sideload.25134018112959168626455777521170227787560722821462484621089704050013766682095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.98269286875620166414487876017226712412431038553375485189148701574896945328164
Short name T960
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.76 seconds
Started Nov 22 02:03:15 PM PST 23
Finished Nov 22 02:03:43 PM PST 23
Peak memory 225380 kb
Host smart-86f3b932-82af-427b-a7c9-a46f8bb9a345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98269286875620166414487876017226712412431038553375485189148701574896945328164 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.kmac_smoke.98269286875620166414487876017226712412431038553375485189148701574896945328164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.74164273950721252703469531487147479097429077326280375324895511543416000055800
Short name T89
Test name
Test status
Simulation time 47207151869 ps
CPU time 863.33 seconds
Started Nov 22 02:03:35 PM PST 23
Finished Nov 22 02:17:59 PM PST 23
Peak memory 339816 kb
Host smart-bfc6e5cc-ce27-418a-b46e-d97a92be52fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=74164273950721252703469531487147479097429077326280375324895511543416000055800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_st
ress_all.74164273950721252703469531487147479097429077326280375324895511543416000055800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.43067984807381221917371006114608992586172549160421637529458419999099856312937
Short name T205
Test name
Test status
Simulation time 322955517 ps
CPU time 5.81 seconds
Started Nov 22 02:03:18 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 219212 kb
Host smart-968b2099-2c87-49aa-8dbc-ee96776a2820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43067984807381221917371006114608992586172549160421637
529458419999099856312937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac.43067984807381221917371006114608992586
172549160421637529458419999099856312937 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.35073564582498287534537113961656268039831030509781250217677831583292349333058
Short name T240
Test name
Test status
Simulation time 309259198 ps
CPU time 5.41 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:03:23 PM PST 23
Peak memory 219260 kb
Host smart-5e5aede9-ed0a-40da-af20-fdfed94591fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35073564582498287534537113961656268039831030509781250
217677831583292349333058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.350735645824982875345371139616
56268039831030509781250217677831583292349333058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.10090468399790450547314679001681525986303026278843152719775558464455414516933
Short name T976
Test name
Test status
Simulation time 117329894454 ps
CPU time 2101.23 seconds
Started Nov 22 02:03:16 PM PST 23
Finished Nov 22 02:38:18 PM PST 23
Peak memory 400840 kb
Host smart-3efb44c4-ad27-4110-ac0d-7aa25935b0ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=10090468399790450547314679001681525986303026278843152719775558464455414516933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_224.10090468399790450547314679001681525986303026278843152719775558464455414516933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.51766270941590636749685224392683054014292597694830718177404570135784848494393
Short name T226
Test name
Test status
Simulation time 106843317633 ps
CPU time 1934.37 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 02:35:33 PM PST 23
Peak memory 376404 kb
Host smart-362cf36b-cc05-4587-845d-c3db7e4d8964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=51766270941590636749685224392683054014292597694830718177404570135784848494393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_256.51766270941590636749685224392683054014292597694830718177404570135784848494393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.60456549299388236877735557555115547731906979579491380691785834662169915158261
Short name T454
Test name
Test status
Simulation time 83520343504 ps
CPU time 1561.2 seconds
Started Nov 22 02:03:30 PM PST 23
Finished Nov 22 02:29:32 PM PST 23
Peak memory 338444 kb
Host smart-d06c9ef1-336b-405e-89df-65ed91b367c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=60456549299388236877735557555115547731906979579491380691785834662169915158261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_384.60456549299388236877735557555115547731906979579491380691785834662169915158261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.107237682613916884940167951407402553976947272029792571251026629079056828223065
Short name T108
Test name
Test status
Simulation time 57499426673 ps
CPU time 1177.89 seconds
Started Nov 22 02:03:19 PM PST 23
Finished Nov 22 02:22:58 PM PST 23
Peak memory 297788 kb
Host smart-f1f4628f-1a78-482e-ab1c-86dc84124f98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107237682613916884940167951407402553976947272029792571251026629079056828223065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.kmac_test_vectors_sha3_512.107237682613916884940167951407402553976947272029792571251026629079056828223065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.103591056376325754447279370914759399184263787945684611043041000579845207207430
Short name T1029
Test name
Test status
Simulation time 320694338954 ps
CPU time 5337.71 seconds
Started Nov 22 02:03:19 PM PST 23
Finished Nov 22 03:32:18 PM PST 23
Peak memory 673076 kb
Host smart-67db7d05-bb5f-44d1-a675-44dd6870304b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=103591056376325754447279370914759399184263787945684611043041000579845207207430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_test_vectors_shake_128.103591056376325754447279370914759399184263787945684611043041000579845207207430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.100683735711926618388869391593912224326493335793923880734686300585569746564108
Short name T249
Test name
Test status
Simulation time 270085708112 ps
CPU time 4697.98 seconds
Started Nov 22 02:03:17 PM PST 23
Finished Nov 22 03:21:37 PM PST 23
Peak memory 577416 kb
Host smart-1db67fde-018c-4f7f-9f26-1bac3548f015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=100683735711926618388869391593912224326493335793923880734686300585569746564108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_test_vectors_shake_256.100683735711926618388869391593912224326493335793923880734686300585569746564108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1026590410755283214903800951569978183959936477863558090494393350932062565016
Short name T178
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:04:02 PM PST 23
Peak memory 218992 kb
Host smart-7f153809-bbc4-4616-b45a-4b391958253e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026590410755283214903800951569978183959936477863558090494393350932062565016 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.kmac_alert_test.1026590410755283214903800951569978183959936477863558090494393350932062565016 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.46802470268677107605655355716746309510693146731251913601723654393356792453382
Short name T208
Test name
Test status
Simulation time 6076748772 ps
CPU time 93.75 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:05:29 PM PST 23
Peak memory 236212 kb
Host smart-45833870-76eb-4916-a131-f3e7c1e8719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46802470268677107605655355716746309510693146731251913601723654393356792453382 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.kmac_app.46802470268677107605655355716746309510693146731251913601723654393356792453382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.57144641013229852451987203394901013025116397930614209517926833418645642974046
Short name T212
Test name
Test status
Simulation time 14830000174 ps
CPU time 402.77 seconds
Started Nov 22 02:03:50 PM PST 23
Finished Nov 22 02:10:34 PM PST 23
Peak memory 243020 kb
Host smart-358564c1-0634-4bb2-86dc-c60628db087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57144641013229852451987203394901013025116397930614209517926833418645642974046 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.kmac_burst_write.57144641013229852451987203394901013025116397930614209517926833418645642974046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.26198452354960159724754382537524771312269662076973287453230413857083718989908
Short name T474
Test name
Test status
Simulation time 7238810904 ps
CPU time 111.73 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:05:55 PM PST 23
Peak memory 243896 kb
Host smart-5eeb3cef-4b30-4fbc-8151-9a65e0ef8e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26198452354960159724754382537524771312269662076973287453230413857083718989908 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.kmac_entropy_refresh.26198452354960159724754382537524771312269662076973287453230413857083718989908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.21077743355417182213080763716535897458924479195006240447008520248197388183936
Short name T51
Test name
Test status
Simulation time 8137821569 ps
CPU time 146.59 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:06:26 PM PST 23
Peak memory 252580 kb
Host smart-abceb163-7c1e-46d9-bc6c-afa44302f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21077743355417182213080763716535897458924479195006240447008520248197388183936 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.kmac_error.21077743355417182213080763716535897458924479195006240447008520248197388183936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.57649643938865926908562981431659671697034714418112788699069232560160641470860
Short name T407
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.94 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 219248 kb
Host smart-983af0a5-16f3-4f2e-84dd-d07dc37aa4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57649643938865926908562981431659671697034714418112788699069232560160641470860 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.kmac_key_error.57649643938865926908562981431659671697034714418112788699069232560160641470860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.70814938101183104667493033430784438070146574716751596812171009222621653636122
Short name T820
Test name
Test status
Simulation time 72761090 ps
CPU time 1.48 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 220492 kb
Host smart-e85cd2a0-c980-4476-b9ec-4c43dfedc38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70814938101183104667493033430784438070146574716751596812171009222621653636122 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.kmac_lc_escalation.70814938101183104667493033430784438070146574716751596812171009222621653636122 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.92127103947363188367107201893954472334778216619072990308191339351025608059924
Short name T259
Test name
Test status
Simulation time 50513696845 ps
CPU time 995.63 seconds
Started Nov 22 02:03:36 PM PST 23
Finished Nov 22 02:20:13 PM PST 23
Peak memory 306312 kb
Host smart-f8a3d4f3-e5e0-4f59-afdd-e5eecc1d829c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92127103947363188367107201893954472334778216619072990308191339351025608059924 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.921271039473631883671072018939544723347782166190729903081913393510256
08059924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.6303269832076011916332934954108803782034057472234749409939373226938772519860
Short name T234
Test name
Test status
Simulation time 7628111361 ps
CPU time 131.61 seconds
Started Nov 22 02:03:51 PM PST 23
Finished Nov 22 02:06:04 PM PST 23
Peak memory 236380 kb
Host smart-2bca7661-a103-42f4-9d19-9394ac84fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6303269832076011916332934954108803782034057472234749409939373226938772519860 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.kmac_sideload.6303269832076011916332934954108803782034057472234749409939373226938772519860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.35392403510839792871612379629141416427909414426715171223816447616427951377219
Short name T88
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.71 seconds
Started Nov 22 02:03:36 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 225376 kb
Host smart-118c6cb6-2e6a-4e79-92b6-22a404d3b8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35392403510839792871612379629141416427909414426715171223816447616427951377219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.kmac_smoke.35392403510839792871612379629141416427909414426715171223816447616427951377219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.11213779654045494667132955371345462569524004893983089574408513657318530769514
Short name T43
Test name
Test status
Simulation time 47207151869 ps
CPU time 880.09 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:18:39 PM PST 23
Peak memory 339872 kb
Host smart-6e9cb909-66b3-459f-bcbe-4b69324e0759
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=11213779654045494667132955371345462569524004893983089574408513657318530769514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_st
ress_all.11213779654045494667132955371345462569524004893983089574408513657318530769514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.78305393046029053614985553888664495165334283924424033347767298617402957234450
Short name T295
Test name
Test status
Simulation time 322955517 ps
CPU time 6.18 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:04:07 PM PST 23
Peak memory 219268 kb
Host smart-7ebe876e-ae9a-4222-ab52-3d15714b22c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78305393046029053614985553888664495165334283924424033
347767298617402957234450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac.78305393046029053614985553888664495165
334283924424033347767298617402957234450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.43082575278813811271218537387983226713115937551910615823156851786186930194931
Short name T306
Test name
Test status
Simulation time 309259198 ps
CPU time 6.07 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:04:07 PM PST 23
Peak memory 219232 kb
Host smart-fb5e560f-860a-4701-98ab-2f5febb81d27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43082575278813811271218537387983226713115937551910615
823156851786186930194931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.430825752788138112712185373879
83226713115937551910615823156851786186930194931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.11354324698398645414601080540409989396924932942687087303836718170928236357757
Short name T793
Test name
Test status
Simulation time 117329894454 ps
CPU time 2107.82 seconds
Started Nov 22 02:03:37 PM PST 23
Finished Nov 22 02:38:45 PM PST 23
Peak memory 400804 kb
Host smart-c5e1cf10-2ed4-496a-93a0-d2eeccbfdeb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11354324698398645414601080540409989396924932942687087303836718170928236357757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_224.11354324698398645414601080540409989396924932942687087303836718170928236357757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.41274065643602975260116346163254065183057394571863829040889055873858990282259
Short name T199
Test name
Test status
Simulation time 106843317633 ps
CPU time 1907.02 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:35:21 PM PST 23
Peak memory 376160 kb
Host smart-5ed46c6e-0daf-45db-a926-a0c3772a82c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=41274065643602975260116346163254065183057394571863829040889055873858990282259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_256.41274065643602975260116346163254065183057394571863829040889055873858990282259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.39782900882866338830811123397915871578852752343860951939143342125162558202784
Short name T488
Test name
Test status
Simulation time 83520343504 ps
CPU time 1661.49 seconds
Started Nov 22 02:03:50 PM PST 23
Finished Nov 22 02:31:33 PM PST 23
Peak memory 338304 kb
Host smart-9c74a5b3-9f75-443e-ba14-90e9705abbce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=39782900882866338830811123397915871578852752343860951939143342125162558202784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_384.39782900882866338830811123397915871578852752343860951939143342125162558202784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.25541244135805968855550371164324294685439388117877066581914693124509417128644
Short name T538
Test name
Test status
Simulation time 57499426673 ps
CPU time 1167 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 297776 kb
Host smart-8256ac1c-8004-47e8-80f1-83ff5dcce951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25541244135805968855550371164324294685439388117877066581914693124509417128644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_512.25541244135805968855550371164324294685439388117877066581914693124509417128644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.83649922215482858912628094974416903862065432879935215583771929651608443734929
Short name T992
Test name
Test status
Simulation time 320694338954 ps
CPU time 5348.36 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 03:33:08 PM PST 23
Peak memory 674252 kb
Host smart-3eae18c8-83a1-43d6-a1bb-3c66cb88a671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=83649922215482858912628094974416903862065432879935215583771929651608443734929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.kmac_test_vectors_shake_128.83649922215482858912628094974416903862065432879935215583771929651608443734929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.9988369741870402936408749878477920794699561972870117749473982439378041539393
Short name T34
Test name
Test status
Simulation time 270085708112 ps
CPU time 4385.6 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 03:17:05 PM PST 23
Peak memory 577184 kb
Host smart-7b95ecb6-5818-4fe3-8326-eb2a53f48b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=9988369741870402936408749878477920794699561972870117749473982439378041539393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.kmac_test_vectors_shake_256.9988369741870402936408749878477920794699561972870117749473982439378041539393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.64037147679489739725672915715516928936701323508276435681054350618915387516709
Short name T802
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:01:02 PM PST 23
Finished Nov 22 02:01:03 PM PST 23
Peak memory 218976 kb
Host smart-0c186d08-73f0-4fe9-8cf2-7105f9d63b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64037147679489739725672915715516928936701323508276435681054350618915387516709 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.kmac_alert_test.64037147679489739725672915715516928936701323508276435681054350618915387516709 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.4423261968825816703005993874767867300151347839043523921327961710724448129592
Short name T603
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.29 seconds
Started Nov 22 02:00:31 PM PST 23
Finished Nov 22 02:02:11 PM PST 23
Peak memory 236276 kb
Host smart-f2ad5bab-cbe4-4135-8137-2779763900fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4423261968825816703005993874767867300151347839043523921327961710724448129592 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.kmac_app.4423261968825816703005993874767867300151347839043523921327961710724448129592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.57414492578095978641262673246535325418053152767631013657752253211580717683765
Short name T736
Test name
Test status
Simulation time 7277596308 ps
CPU time 106.93 seconds
Started Nov 22 02:00:31 PM PST 23
Finished Nov 22 02:02:19 PM PST 23
Peak memory 243912 kb
Host smart-c74a8828-adf0-4f00-a054-19d09217111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57414492578095978641262673246535325418053152767631013657752253211580717683765 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_app_with_partial_data.57414492578095978641262673246535325418053152767631013657752253211580717683765 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.81388966014684506044679476692414358383976873096283999262410999459218670544219
Short name T491
Test name
Test status
Simulation time 14830000174 ps
CPU time 380.8 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 02:06:50 PM PST 23
Peak memory 243276 kb
Host smart-0ea1315d-4fa6-4c9d-97f0-eeb21c115053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81388966014684506044679476692414358383976873096283999262410999459218670544219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.kmac_burst_write.81388966014684506044679476692414358383976873096283999262410999459218670544219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.17244669093340585602182713242779748668719683982446862558851207584791580940639
Short name T355
Test name
Test status
Simulation time 62261174 ps
CPU time 1.27 seconds
Started Nov 22 02:00:42 PM PST 23
Finished Nov 22 02:00:44 PM PST 23
Peak memory 219028 kb
Host smart-9044811e-89ac-41f6-b717-291845ad13d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=17244669093340585602182713242779748668719683982446862558851207584791580940639 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.kmac_edn_timeout_error.17244669093340585602182713242779748668719683982446862558851207584791580940639 +enable_masking=1
+sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.36240107890387127842720362815070062863324623479533150154448791428391734676911
Short name T783
Test name
Test status
Simulation time 64850439 ps
CPU time 1.27 seconds
Started Nov 22 02:00:42 PM PST 23
Finished Nov 22 02:00:44 PM PST 23
Peak memory 219040 kb
Host smart-77114e4f-b83c-4e4c-b955-7ad659594f39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=36240107890387127842720362815070062863324623479533150154448791428391734676911 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.36240107890387127842720362815070062863324623479533150154448791428391734676911 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.8438792253029797862376262682763507150102285192030233245136275658182855963200
Short name T1040
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.52 seconds
Started Nov 22 02:00:36 PM PST 23
Finished Nov 22 02:00:59 PM PST 23
Peak memory 219372 kb
Host smart-bf5e6e0b-e89d-45ab-ae1e-902257229974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8438792253029797862376262682763507150102285192030233245136275658182855963200 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.kmac_entropy_ready_error.8438792253029797862376262682763507150102285192030233245136275658182855963200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.92520288420487124562592923664581170525773670630448040087711059323967329781467
Short name T727
Test name
Test status
Simulation time 7238810904 ps
CPU time 110.44 seconds
Started Nov 22 02:00:30 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 243896 kb
Host smart-019bfbe3-0a46-4023-84ce-a59393e74ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92520288420487124562592923664581170525773670630448040087711059323967329781467 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.kmac_entropy_refresh.92520288420487124562592923664581170525773670630448040087711059323967329781467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.31576551096309457311737707775399611860024408089946338085891534603334460574748
Short name T235
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.36 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:03:13 PM PST 23
Peak memory 252720 kb
Host smart-92ae296b-bdd5-4346-ac81-027bc1f34214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31576551096309457311737707775399611860024408089946338085891534603334460574748 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.kmac_error.31576551096309457311737707775399611860024408089946338085891534603334460574748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.24662891366626468810184245670397350858916008139992617879368298294023030372434
Short name T382
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.93 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:00:54 PM PST 23
Peak memory 219296 kb
Host smart-167d2dc5-ed7f-43c8-81ed-65d22a0895c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24662891366626468810184245670397350858916008139992617879368298294023030372434 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.kmac_key_error.24662891366626468810184245670397350858916008139992617879368298294023030372434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.70081080131622414458133767087503432129433344596100878371186556409026710982544
Short name T315
Test name
Test status
Simulation time 72761090 ps
CPU time 1.54 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:00:50 PM PST 23
Peak memory 220508 kb
Host smart-3d791051-1eec-480f-a6fe-12756fc5eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70081080131622414458133767087503432129433344596100878371186556409026710982544 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.kmac_lc_escalation.70081080131622414458133767087503432129433344596100878371186556409026710982544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.32489032464180853342396279239830511856723335421108531682088356198354743940280
Short name T258
Test name
Test status
Simulation time 50513696845 ps
CPU time 1011.53 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 02:17:21 PM PST 23
Peak memory 306344 kb
Host smart-1517ef19-a285-4a73-b0ef-45c339b4b733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32489032464180853342396279239830511856723335421108531682088356198354743940280 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3248903246418085334239627923983051185672333542110853168208835619835474
3940280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.41124850483422312830911676244902893307591731012387305148331089487201406007092
Short name T585
Test name
Test status
Simulation time 7712378544 ps
CPU time 133.87 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 244200 kb
Host smart-b299061f-8f20-45e7-857e-b5a8c9581cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41124850483422312830911676244902893307591731012387305148331089487201406007092 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.kmac_mubi.41124850483422312830911676244902893307591731012387305148331089487201406007092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.52683665904019433901885280845431049817691135891076095912281244863434901398758
Short name T80
Test name
Test status
Simulation time 6415496062 ps
CPU time 55.65 seconds
Started Nov 22 02:00:50 PM PST 23
Finished Nov 22 02:01:46 PM PST 23
Peak memory 277320 kb
Host smart-99fb2599-d59e-405a-887c-c432fe688292
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52683665904019433901885280845431049817691135891076095912281244863434901398758 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.kmac_sec_cm.52683665904019433901885280845431049817691135891076095912281244863434901398758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.78888143805405369997177803618154970183144420824222035303975179081675650500796
Short name T263
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.14 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:03:06 PM PST 23
Peak memory 236264 kb
Host smart-e224cf00-5d6a-43c5-9fdd-e6423107973c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78888143805405369997177803618154970183144420824222035303975179081675650500796 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.kmac_sideload.78888143805405369997177803618154970183144420824222035303975179081675650500796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.84622389732971611738417649343910693179875321561476742609029215456578041113092
Short name T1077
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.49 seconds
Started Nov 22 02:00:32 PM PST 23
Finished Nov 22 02:00:59 PM PST 23
Peak memory 225340 kb
Host smart-88701581-69a6-4ee6-b3a1-88c26d71d39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84622389732971611738417649343910693179875321561476742609029215456578041113092 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.kmac_smoke.84622389732971611738417649343910693179875321561476742609029215456578041113092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.78381270139925716217408394043162873530075541865911971479613884362566453035772
Short name T333
Test name
Test status
Simulation time 47207151869 ps
CPU time 895.9 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:15:45 PM PST 23
Peak memory 339840 kb
Host smart-6e806b2e-496a-4bfb-97dd-4652ab74376e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=78381270139925716217408394043162873530075541865911971479613884362566453035772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_str
ess_all.78381270139925716217408394043162873530075541865911971479613884362566453035772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.31805785735235369722961215980009891611202832386571134770800146827854403524378
Short name T489
Test name
Test status
Simulation time 322955517 ps
CPU time 6.09 seconds
Started Nov 22 02:00:40 PM PST 23
Finished Nov 22 02:00:47 PM PST 23
Peak memory 219292 kb
Host smart-bd9f9845-2d1c-4bdf-b9fa-da8a95f258a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805785735235369722961215980009891611202832386571134
770800146827854403524378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.318057857352353697229612159800098916112
02832386571134770800146827854403524378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.42043493655995438471853330957051334394805905571865568511321997460393405021385
Short name T220
Test name
Test status
Simulation time 309259198 ps
CPU time 5.49 seconds
Started Nov 22 02:00:27 PM PST 23
Finished Nov 22 02:00:33 PM PST 23
Peak memory 219244 kb
Host smart-71ac173b-b43f-49b6-8495-2b8f0efe6576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043493655995438471853330957051334394805905571865568
511321997460393405021385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4204349365599543847185333095705
1334394805905571865568511321997460393405021385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.90442497605780873945824453040728826502223687758073879936208961875472038248625
Short name T722
Test name
Test status
Simulation time 117329894454 ps
CPU time 2173.48 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:37:01 PM PST 23
Peak memory 400848 kb
Host smart-85fa2076-333e-4d1b-99d2-9d254ba242d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90442497605780873945824453040728826502223687758073879936208961875472038248625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_224.90442497605780873945824453040728826502223687758073879936208961875472038248625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.23113967674159254374627305814415186318159123729886048562826477793304709595207
Short name T440
Test name
Test status
Simulation time 106843317633 ps
CPU time 2010.51 seconds
Started Nov 22 02:00:34 PM PST 23
Finished Nov 22 02:34:05 PM PST 23
Peak memory 376336 kb
Host smart-b4b380c2-a7f4-4c2e-baaf-ca3f007de184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=23113967674159254374627305814415186318159123729886048562826477793304709595207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_256.23113967674159254374627305814415186318159123729886048562826477793304709595207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.92199981656913515932261523223377915426122057137032093091313950111384018615028
Short name T891
Test name
Test status
Simulation time 83520343504 ps
CPU time 1629.26 seconds
Started Nov 22 02:00:29 PM PST 23
Finished Nov 22 02:27:39 PM PST 23
Peak memory 338368 kb
Host smart-8e66c2b6-d0e4-4de8-868c-fe2b95f56a19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=92199981656913515932261523223377915426122057137032093091313950111384018615028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_384.92199981656913515932261523223377915426122057137032093091313950111384018615028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.59051466352776861981426213117544008306296367002244483031028849904691908899538
Short name T326
Test name
Test status
Simulation time 57499426673 ps
CPU time 1241.12 seconds
Started Nov 22 02:00:28 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 297756 kb
Host smart-3c21cf1a-1d4c-403c-9a18-a82ea16a2d4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59051466352776861981426213117544008306296367002244483031028849904691908899538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_512.59051466352776861981426213117544008306296367002244483031028849904691908899538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.8927236553164859064156660999155957372140580320960759038565965960037181787345
Short name T959
Test name
Test status
Simulation time 320694338954 ps
CPU time 5570.39 seconds
Started Nov 22 02:00:33 PM PST 23
Finished Nov 22 03:33:25 PM PST 23
Peak memory 672908 kb
Host smart-aaddd429-0f1b-40b4-b873-e3cdda4d6894
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=8927236553164859064156660999155957372140580320960759038565965960037181787345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.kmac_test_vectors_shake_128.8927236553164859064156660999155957372140580320960759038565965960037181787345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.23675238974983071329607997047990154575567605668320389625925991722508145984747
Short name T809
Test name
Test status
Simulation time 270085708112 ps
CPU time 4586.34 seconds
Started Nov 22 02:00:27 PM PST 23
Finished Nov 22 03:16:54 PM PST 23
Peak memory 577276 kb
Host smart-ea496e45-967e-44fb-b801-0d5ec8a0d293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=23675238974983071329607997047990154575567605668320389625925991722508145984747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.kmac_test_vectors_shake_256.23675238974983071329607997047990154575567605668320389625925991722508145984747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3761277685253094749500176473712646338192258028209856937771159671364754100705
Short name T372
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:03:48 PM PST 23
Peak memory 218896 kb
Host smart-a6104e9a-6cf5-4ce1-9139-73701b2a609b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761277685253094749500176473712646338192258028209856937771159671364754100705 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.kmac_alert_test.3761277685253094749500176473712646338192258028209856937771159671364754100705 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.12413223715151893586219838244361432923183769080182711311649841650917006400104
Short name T1047
Test name
Test status
Simulation time 6076748772 ps
CPU time 98.74 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 236264 kb
Host smart-257d1df3-5ff9-4d1c-826a-524c2c2fb959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12413223715151893586219838244361432923183769080182711311649841650917006400104 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.kmac_app.12413223715151893586219838244361432923183769080182711311649841650917006400104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.28587910487571036677514239444659741032595288976404520761889527501669535229687
Short name T32
Test name
Test status
Simulation time 14830000174 ps
CPU time 383.21 seconds
Started Nov 22 02:03:46 PM PST 23
Finished Nov 22 02:10:10 PM PST 23
Peak memory 243252 kb
Host smart-4febaa66-3451-4d8a-bda8-fddca2c589bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28587910487571036677514239444659741032595288976404520761889527501669535229687 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.kmac_burst_write.28587910487571036677514239444659741032595288976404520761889527501669535229687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.107033359530428731329134048999940731522656537446478142829524127615158007847081
Short name T345
Test name
Test status
Simulation time 7238810904 ps
CPU time 115.14 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 02:05:29 PM PST 23
Peak memory 243944 kb
Host smart-10b5ac69-316a-4496-b1d1-32a8604b7f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107033359530428731329134048999940731522656537446478142829524127615158007847081 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_entropy_refresh.107033359530428731329134048999940731522656537446478142829524127615158007847081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.96939701989679704338513376369084493107108558555200672640433661257596068807260
Short name T378
Test name
Test status
Simulation time 8137821569 ps
CPU time 143.8 seconds
Started Nov 22 02:03:46 PM PST 23
Finished Nov 22 02:06:11 PM PST 23
Peak memory 252728 kb
Host smart-f64a0416-834b-44e7-a8ca-28aa2943ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96939701989679704338513376369084493107108558555200672640433661257596068807260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.kmac_error.96939701989679704338513376369084493107108558555200672640433661257596068807260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.109737445955127533883199283817209752344811102572331180290697239550948757965798
Short name T673
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.75 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:03:53 PM PST 23
Peak memory 219264 kb
Host smart-1bf75c77-acd2-4c7a-a6da-f8d9ef59b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109737445955127533883199283817209752344811102572331180290697239550948757965798 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.kmac_key_error.109737445955127533883199283817209752344811102572331180290697239550948757965798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.28114617464558917105550464938410819592592053190474237825047827478308232086727
Short name T849
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:03:49 PM PST 23
Peak memory 220428 kb
Host smart-c8719432-6931-4473-81ab-436dbe071eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28114617464558917105550464938410819592592053190474237825047827478308232086727 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.kmac_lc_escalation.28114617464558917105550464938410819592592053190474237825047827478308232086727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.12067598438440246232226091289418137402071662797544326362866771467982684189624
Short name T633
Test name
Test status
Simulation time 50513696845 ps
CPU time 966.65 seconds
Started Nov 22 02:03:30 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 306212 kb
Host smart-c200df0a-eb8f-425d-926e-6f715cffca25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067598438440246232226091289418137402071662797544326362866771467982684189624 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.120675984384402462322260912894181374020716627975443263628667714679826
84189624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.13579206843310182069030553535707575498536717574770655263938381717114130784905
Short name T843
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.85 seconds
Started Nov 22 02:03:51 PM PST 23
Finished Nov 22 02:06:12 PM PST 23
Peak memory 236388 kb
Host smart-eb98a429-9296-46b7-8f1b-cf5860a34e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13579206843310182069030553535707575498536717574770655263938381717114130784905 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.kmac_sideload.13579206843310182069030553535707575498536717574770655263938381717114130784905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.13196810869833806295166209032312844819289549537190466139670319445313335254192
Short name T580
Test name
Test status
Simulation time 1925406983 ps
CPU time 28.55 seconds
Started Nov 22 02:03:36 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 225336 kb
Host smart-0da30442-f54c-47a2-9dd6-da5ad85d4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13196810869833806295166209032312844819289549537190466139670319445313335254192 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.kmac_smoke.13196810869833806295166209032312844819289549537190466139670319445313335254192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.100854056063085945560288508081074223592576418483143842333646233026909264242142
Short name T811
Test name
Test status
Simulation time 47207151869 ps
CPU time 869.27 seconds
Started Nov 22 02:03:36 PM PST 23
Finished Nov 22 02:18:06 PM PST 23
Peak memory 339780 kb
Host smart-61ab1665-d7a1-45f6-a3ed-73189b66734b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=100854056063085945560288508081074223592576418483143842333646233026909264242142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_s
tress_all.100854056063085945560288508081074223592576418483143842333646233026909264242142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.15794321877713984871641114087980017347653029778040125155240610911636571795868
Short name T224
Test name
Test status
Simulation time 322955517 ps
CPU time 6.05 seconds
Started Nov 22 02:03:30 PM PST 23
Finished Nov 22 02:03:37 PM PST 23
Peak memory 219272 kb
Host smart-cba973d7-ab25-4ecb-98e2-9e200d4692cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15794321877713984871641114087980017347653029778040125
155240610911636571795868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac.15794321877713984871641114087980017347
653029778040125155240610911636571795868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.25975643554895798991339080015467482495684839298479724813770853969254606672142
Short name T444
Test name
Test status
Simulation time 309259198 ps
CPU time 5.95 seconds
Started Nov 22 02:03:50 PM PST 23
Finished Nov 22 02:03:57 PM PST 23
Peak memory 219256 kb
Host smart-9f531fcd-25dc-4a8e-a787-4ddb2bb25638
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975643554895798991339080015467482495684839298479724
813770853969254606672142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.259756435548957989913390800154
67482495684839298479724813770853969254606672142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.89144433027930612102539362305145817988636537497374736737747716458610694413551
Short name T125
Test name
Test status
Simulation time 117329894454 ps
CPU time 2045.66 seconds
Started Nov 22 02:03:48 PM PST 23
Finished Nov 22 02:37:55 PM PST 23
Peak memory 400856 kb
Host smart-24a9a05a-7e12-47e1-b6f9-ec7db644d153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89144433027930612102539362305145817988636537497374736737747716458610694413551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_224.89144433027930612102539362305145817988636537497374736737747716458610694413551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.107215800529250541773053715258310421003238141074440405393253050995148865559901
Short name T485
Test name
Test status
Simulation time 106843317633 ps
CPU time 1892.41 seconds
Started Nov 22 02:03:32 PM PST 23
Finished Nov 22 02:35:06 PM PST 23
Peak memory 376392 kb
Host smart-d70b39e0-e4b5-476a-a012-425d40df00e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107215800529250541773053715258310421003238141074440405393253050995148865559901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.kmac_test_vectors_sha3_256.107215800529250541773053715258310421003238141074440405393253050995148865559901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.59468457594274220013213266020999343502422089542898526841545423034491929425827
Short name T947
Test name
Test status
Simulation time 83520343504 ps
CPU time 1545.82 seconds
Started Nov 22 02:03:32 PM PST 23
Finished Nov 22 02:29:19 PM PST 23
Peak memory 338440 kb
Host smart-1c99ee6c-ee1c-420b-860b-2b62a12e3e29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59468457594274220013213266020999343502422089542898526841545423034491929425827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_384.59468457594274220013213266020999343502422089542898526841545423034491929425827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.32083166581039304074382778352304090839516776734098936908276324586819611701499
Short name T944
Test name
Test status
Simulation time 57499426673 ps
CPU time 1158.69 seconds
Started Nov 22 02:03:36 PM PST 23
Finished Nov 22 02:22:55 PM PST 23
Peak memory 297716 kb
Host smart-0bfcb09f-bef2-4ce4-88ff-5551c488d423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32083166581039304074382778352304090839516776734098936908276324586819611701499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_512.32083166581039304074382778352304090839516776734098936908276324586819611701499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.79981486033935763851425067635787412445556809284368430393292936667509381687521
Short name T993
Test name
Test status
Simulation time 320694338954 ps
CPU time 5451.5 seconds
Started Nov 22 02:03:33 PM PST 23
Finished Nov 22 03:34:26 PM PST 23
Peak memory 674344 kb
Host smart-54b2071d-15e1-4fa1-9d3d-ec5146360690
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=79981486033935763851425067635787412445556809284368430393292936667509381687521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.kmac_test_vectors_shake_128.79981486033935763851425067635787412445556809284368430393292936667509381687521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.52303312303918984157863643916846234275045544370027806274703089975559642163940
Short name T161
Test name
Test status
Simulation time 270085708112 ps
CPU time 4761.02 seconds
Started Nov 22 02:03:31 PM PST 23
Finished Nov 22 03:22:54 PM PST 23
Peak memory 577380 kb
Host smart-ec778291-f630-4785-a1a7-8796c7a2d8df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=52303312303918984157863643916846234275045544370027806274703089975559642163940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.kmac_test_vectors_shake_256.52303312303918984157863643916846234275045544370027806274703089975559642163940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.49981602448902843187470923664579845288162689282929524555858258712701324117794
Short name T261
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:00 PM PST 23
Peak memory 219016 kb
Host smart-da51e5b8-7cb6-430f-a35a-adc4d26339d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49981602448902843187470923664579845288162689282929524555858258712701324117794 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.kmac_alert_test.49981602448902843187470923664579845288162689282929524555858258712701324117794 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.65321744702552315638262343921609945623506048437710699066190622467131226022156
Short name T1027
Test name
Test status
Simulation time 6076748772 ps
CPU time 97.9 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:05:39 PM PST 23
Peak memory 236224 kb
Host smart-d52cf37f-4563-4357-a454-b8576fb45884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65321744702552315638262343921609945623506048437710699066190622467131226022156 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.kmac_app.65321744702552315638262343921609945623506048437710699066190622467131226022156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.83766895574914298815585267807688479533443192553074183571797754264415085165680
Short name T582
Test name
Test status
Simulation time 14830000174 ps
CPU time 396.98 seconds
Started Nov 22 02:03:47 PM PST 23
Finished Nov 22 02:10:25 PM PST 23
Peak memory 243224 kb
Host smart-d55e31de-0499-42bd-9667-0e71ed531c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83766895574914298815585267807688479533443192553074183571797754264415085165680 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.kmac_burst_write.83766895574914298815585267807688479533443192553074183571797754264415085165680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.53562596351916491832350136369487525961350398939587910602031314248688155062830
Short name T433
Test name
Test status
Simulation time 7238810904 ps
CPU time 110.11 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:05:49 PM PST 23
Peak memory 243856 kb
Host smart-fe5c8be5-ce77-43a3-8359-eb32cdeb39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53562596351916491832350136369487525961350398939587910602031314248688155062830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.kmac_entropy_refresh.53562596351916491832350136369487525961350398939587910602031314248688155062830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.45164409057996578362953018063587887109669550067919092518160133537148871439956
Short name T759
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.7 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:06:22 PM PST 23
Peak memory 252728 kb
Host smart-3edececd-2bd7-4ec2-be74-18c45069e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45164409057996578362953018063587887109669550067919092518160133537148871439956 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.kmac_error.45164409057996578362953018063587887109669550067919092518160133537148871439956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.53362452883742309689367047504090297091274999646888913694420503830357238273906
Short name T984
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.87 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:04:07 PM PST 23
Peak memory 219244 kb
Host smart-642e5013-05f3-402e-bd6e-f287e7f7f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53362452883742309689367047504090297091274999646888913694420503830357238273906 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.kmac_key_error.53362452883742309689367047504090297091274999646888913694420503830357238273906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.47710998882874909122810630798762553428072650120601214924369842770996298434235
Short name T136
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:03:57 PM PST 23
Peak memory 220468 kb
Host smart-ae4a8bb1-46ab-4229-acad-32c33f67a902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47710998882874909122810630798762553428072650120601214924369842770996298434235 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.kmac_lc_escalation.47710998882874909122810630798762553428072650120601214924369842770996298434235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.36820977905444418281411985968850375128285751167562098239361747006356037234679
Short name T642
Test name
Test status
Simulation time 50513696845 ps
CPU time 1003.58 seconds
Started Nov 22 02:03:32 PM PST 23
Finished Nov 22 02:20:17 PM PST 23
Peak memory 306316 kb
Host smart-2a444cf5-7c0d-4194-9bf3-2cd3aa57e521
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36820977905444418281411985968850375128285751167562098239361747006356037234679 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.368209779054444182814119859688503751282857511675620982393617470063560
37234679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.91107812360777901435653940607595118916689539122398422338765104860182172373923
Short name T897
Test name
Test status
Simulation time 7628111361 ps
CPU time 133.48 seconds
Started Nov 22 02:03:46 PM PST 23
Finished Nov 22 02:06:01 PM PST 23
Peak memory 236300 kb
Host smart-1fd4be38-0ffb-42b4-9134-4b684e7626d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91107812360777901435653940607595118916689539122398422338765104860182172373923 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.kmac_sideload.91107812360777901435653940607595118916689539122398422338765104860182172373923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.71766608639813895195816584410761818675763469218854928853920825516806955977822
Short name T577
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.25 seconds
Started Nov 22 02:03:51 PM PST 23
Finished Nov 22 02:04:19 PM PST 23
Peak memory 225396 kb
Host smart-c1bee392-94aa-4dfd-b90d-f501a111c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71766608639813895195816584410761818675763469218854928853920825516806955977822 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.kmac_smoke.71766608639813895195816584410761818675763469218854928853920825516806955977822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.7246974839771642137736575267000475628359720388625358355654633949260234731347
Short name T311
Test name
Test status
Simulation time 47207151869 ps
CPU time 902.15 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:19:01 PM PST 23
Peak memory 339808 kb
Host smart-a40cd611-27ca-4ede-99e2-a1f032b69028
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=7246974839771642137736575267000475628359720388625358355654633949260234731347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_str
ess_all.7246974839771642137736575267000475628359720388625358355654633949260234731347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.99442441820634635443445318632962509651949280138114964863740713269946416679482
Short name T250
Test name
Test status
Simulation time 322955517 ps
CPU time 5.94 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 219260 kb
Host smart-e8f2ae03-9706-4a22-9a9f-2cde617740d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99442441820634635443445318632962509651949280138114964
863740713269946416679482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac.99442441820634635443445318632962509651
949280138114964863740713269946416679482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.103828530795858058359753880738551165072609166633020182289324986609225463552131
Short name T886
Test name
Test status
Simulation time 309259198 ps
CPU time 5.71 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 219300 kb
Host smart-f2cffbc8-d5b0-4b5a-8d06-d4ce11dc1620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382853079585805835975388073855116507260916663302018
2289324986609225463552131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.10382853079585805835975388073
8551165072609166633020182289324986609225463552131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.111222800001443600014768918423410298034263103889044654681096609796048427975601
Short name T684
Test name
Test status
Simulation time 117329894454 ps
CPU time 2099.81 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:39:01 PM PST 23
Peak memory 400868 kb
Host smart-93b22ca4-093c-4c5f-8394-c975d74a9a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=111222800001443600014768918423410298034263103889044654681096609796048427975601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.kmac_test_vectors_sha3_224.111222800001443600014768918423410298034263103889044654681096609796048427975601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.48151271762698476684083179027493086589723990172622319812681779694426339631816
Short name T875
Test name
Test status
Simulation time 106843317633 ps
CPU time 1909.49 seconds
Started Nov 22 02:03:53 PM PST 23
Finished Nov 22 02:35:44 PM PST 23
Peak memory 376348 kb
Host smart-4d75c9cd-b280-44db-bfb6-9e9a66a599d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=48151271762698476684083179027493086589723990172622319812681779694426339631816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_256.48151271762698476684083179027493086589723990172622319812681779694426339631816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.40054281463967983973611403045170144652826983961328773053524963241823472453380
Short name T497
Test name
Test status
Simulation time 83520343504 ps
CPU time 1604.77 seconds
Started Nov 22 02:03:56 PM PST 23
Finished Nov 22 02:30:42 PM PST 23
Peak memory 338348 kb
Host smart-fbd396d1-5844-4ab8-ba43-a913a4fcc0ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=40054281463967983973611403045170144652826983961328773053524963241823472453380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_384.40054281463967983973611403045170144652826983961328773053524963241823472453380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.3173599357342115173286941889594269357555643428954055160384424978514575638851
Short name T747
Test name
Test status
Simulation time 57499426673 ps
CPU time 1161.26 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:23:20 PM PST 23
Peak memory 297588 kb
Host smart-04a4e071-64ee-485b-900c-af43cc204d45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3173599357342115173286941889594269357555643428954055160384424978514575638851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
kmac_test_vectors_sha3_512.3173599357342115173286941889594269357555643428954055160384424978514575638851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.84181394117761323512592157952644064603272034572932690381943813786813309623819
Short name T522
Test name
Test status
Simulation time 320694338954 ps
CPU time 5362.73 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 03:33:24 PM PST 23
Peak memory 674212 kb
Host smart-23d0f5a8-e325-485d-a124-af24fa1421b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=84181394117761323512592157952644064603272034572932690381943813786813309623819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.kmac_test_vectors_shake_128.84181394117761323512592157952644064603272034572932690381943813786813309623819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.106552324036787219909230776300871663069972398124888506974233111771321167117044
Short name T757
Test name
Test status
Simulation time 270085708112 ps
CPU time 4401.85 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 03:17:21 PM PST 23
Peak memory 577416 kb
Host smart-fde676ff-1fdf-4dab-97f5-b238dc3b3ad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=106552324036787219909230776300871663069972398124888506974233111771321167117044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.kmac_test_vectors_shake_256.106552324036787219909230776300871663069972398124888506974233111771321167117044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.113406217171834815833158161922630142094221675884233062315581156218529308881327
Short name T1022
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:03:59 PM PST 23
Peak memory 219008 kb
Host smart-5f151c2a-1112-4bd8-8f19-5d9df2b496f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113406217171834815833158161922630142094221675884233062315581156218529308881327 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.113406217171834815833158161922630142094221675884233062315581156218529308881327 +enable_masking=1
+sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.46778860680963658408351273168740477606322639243604430543619373593662472827177
Short name T334
Test name
Test status
Simulation time 6076748772 ps
CPU time 94.63 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:05:33 PM PST 23
Peak memory 236124 kb
Host smart-7c53a522-36ac-4b97-b868-bff9c1ebcbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46778860680963658408351273168740477606322639243604430543619373593662472827177 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.kmac_app.46778860680963658408351273168740477606322639243604430543619373593662472827177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.105888331367745793791055570616312233564297592168884539336024892872895222698386
Short name T168
Test name
Test status
Simulation time 14830000174 ps
CPU time 368.34 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:10:08 PM PST 23
Peak memory 243180 kb
Host smart-dd3386eb-2125-40a8-ad66-3a9004854ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105888331367745793791055570616312233564297592168884539336024892872895222698386 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.kmac_burst_write.105888331367745793791055570616312233564297592168884539336024892872895222698386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.5643014873649595617090794895118196565722525625650129498890412056101181869132
Short name T270
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.81 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:05:49 PM PST 23
Peak memory 243860 kb
Host smart-3236404d-549b-414e-8972-5f941139c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5643014873649595617090794895118196565722525625650129498890412056101181869132 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.kmac_entropy_refresh.5643014873649595617090794895118196565722525625650129498890412056101181869132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.44716237551650419832092221275113367986071351194183713518364923635284122207633
Short name T450
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.55 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:06:24 PM PST 23
Peak memory 252792 kb
Host smart-035e05a2-971c-4f59-9a6e-fada808fa81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44716237551650419832092221275113367986071351194183713518364923635284122207633 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.kmac_error.44716237551650419832092221275113367986071351194183713518364923635284122207633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.4542044401307113228510037455163659648019949802465712252377288453611730189339
Short name T734
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.76 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:04:07 PM PST 23
Peak memory 219184 kb
Host smart-8c2cdfc7-8c92-4a67-82ca-034e70509277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4542044401307113228510037455163659648019949802465712252377288453611730189339 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.kmac_key_error.4542044401307113228510037455163659648019949802465712252377288453611730189339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.94270784247475666438472615778349495791400466122427000738738911103424740262679
Short name T1063
Test name
Test status
Simulation time 72761090 ps
CPU time 1.48 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:04:00 PM PST 23
Peak memory 220504 kb
Host smart-2095cd23-2f99-41ae-9eab-384fa05c5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94270784247475666438472615778349495791400466122427000738738911103424740262679 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.kmac_lc_escalation.94270784247475666438472615778349495791400466122427000738738911103424740262679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.9081916975700027745940691445641130171496779646608932374031026994546613747611
Short name T769
Test name
Test status
Simulation time 50513696845 ps
CPU time 1049.71 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 306344 kb
Host smart-d8dca2e5-62aa-41ce-8d2d-9bb65bbc6308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9081916975700027745940691445641130171496779646608932374031026994546613747611 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.9081916975700027745940691445641130171496779646608932374031026994546613
747611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.41683082721546017461937547547706202711508232327044348631939026751141254061491
Short name T573
Test name
Test status
Simulation time 7628111361 ps
CPU time 140.82 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:06:20 PM PST 23
Peak memory 236316 kb
Host smart-36a02380-ede8-45a2-8fe7-20fc3b519d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41683082721546017461937547547706202711508232327044348631939026751141254061491 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.kmac_sideload.41683082721546017461937547547706202711508232327044348631939026751141254061491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.57683785272857906086585846110271486513198033635524494988977862943032748033830
Short name T942
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.11 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:04:26 PM PST 23
Peak memory 225404 kb
Host smart-452fb38f-2a21-459d-ac39-3344630c512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57683785272857906086585846110271486513198033635524494988977862943032748033830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.kmac_smoke.57683785272857906086585846110271486513198033635524494988977862943032748033830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.92843518127597622297853318989144054163741776097581236993100029787819015656510
Short name T755
Test name
Test status
Simulation time 47207151869 ps
CPU time 848.29 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:18:08 PM PST 23
Peak memory 339868 kb
Host smart-55195c3d-a9e8-43ff-b4e7-b7455fd56512
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=92843518127597622297853318989144054163741776097581236993100029787819015656510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_st
ress_all.92843518127597622297853318989144054163741776097581236993100029787819015656510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.51890211540294941249487107370214810959939378676481674106486615512130224818280
Short name T448
Test name
Test status
Simulation time 322955517 ps
CPU time 5.72 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:04:01 PM PST 23
Peak memory 219216 kb
Host smart-5735cf5b-97f5-4b33-abe3-1c0733a15a52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51890211540294941249487107370214810959939378676481674
106486615512130224818280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac.51890211540294941249487107370214810959
939378676481674106486615512130224818280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.97982275236533600479495459901945049359679591200155621763369155354478300534935
Short name T439
Test name
Test status
Simulation time 309259198 ps
CPU time 5.79 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:04:02 PM PST 23
Peak memory 219252 kb
Host smart-09e833de-6d1c-42e4-8c88-149e87bf1974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97982275236533600479495459901945049359679591200155621
763369155354478300534935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.979822752365336004794954599019
45049359679591200155621763369155354478300534935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.77085885266679722471057464613753646229839040581465405137356288751795630349655
Short name T363
Test name
Test status
Simulation time 117329894454 ps
CPU time 2043.33 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:38:04 PM PST 23
Peak memory 400868 kb
Host smart-d5c64813-1dc6-4707-b55a-708c9cede9cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77085885266679722471057464613753646229839040581465405137356288751795630349655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_224.77085885266679722471057464613753646229839040581465405137356288751795630349655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.67380480379143373394077951703210153387137095370797040715808630614406954881645
Short name T483
Test name
Test status
Simulation time 106843317633 ps
CPU time 1871.74 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:35:15 PM PST 23
Peak memory 376396 kb
Host smart-c93bdcfa-475d-46f9-b2d4-d4f2ccca0b02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=67380480379143373394077951703210153387137095370797040715808630614406954881645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_256.67380480379143373394077951703210153387137095370797040715808630614406954881645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.91613235762557819597651215550310726021501058174086783098011127251215702785955
Short name T149
Test name
Test status
Simulation time 83520343504 ps
CPU time 1550.25 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:29:49 PM PST 23
Peak memory 338476 kb
Host smart-38fd262d-0dea-4397-966b-ba20c8f0befb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91613235762557819597651215550310726021501058174086783098011127251215702785955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_384.91613235762557819597651215550310726021501058174086783098011127251215702785955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.25663179378454140954109112296985843408160737936361276659684176201098630585074
Short name T985
Test name
Test status
Simulation time 57499426673 ps
CPU time 1130.69 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:22:49 PM PST 23
Peak memory 297720 kb
Host smart-15b50028-306f-4073-847a-2e3c55e16471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25663179378454140954109112296985843408160737936361276659684176201098630585074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_512.25663179378454140954109112296985843408160737936361276659684176201098630585074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.41663572130289624240167046710223295793567961861640565522756110034690032296652
Short name T611
Test name
Test status
Simulation time 320694338954 ps
CPU time 5226.32 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 03:31:06 PM PST 23
Peak memory 674340 kb
Host smart-975e5d84-5900-4600-bdfa-f9b66d270b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=41663572130289624240167046710223295793567961861640565522756110034690032296652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.kmac_test_vectors_shake_128.41663572130289624240167046710223295793567961861640565522756110034690032296652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.109506783292495000193640005613249616837242981667760464859147078401455809945414
Short name T546
Test name
Test status
Simulation time 270085708112 ps
CPU time 4551.53 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 03:19:50 PM PST 23
Peak memory 577420 kb
Host smart-54e3d695-f175-497b-8a01-be0f02c937fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=109506783292495000193640005613249616837242981667760464859147078401455809945414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.kmac_test_vectors_shake_256.109506783292495000193640005613249616837242981667760464859147078401455809945414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.10543897707999538833387177174913983757331271313729780288093167554014264153609
Short name T923
Test name
Test status
Simulation time 21118646 ps
CPU time 0.85 seconds
Started Nov 22 02:04:19 PM PST 23
Finished Nov 22 02:04:21 PM PST 23
Peak memory 219000 kb
Host smart-a9b4467f-4330-45b8-90a3-17524c36f9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543897707999538833387177174913983757331271313729780288093167554014264153609 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.kmac_alert_test.10543897707999538833387177174913983757331271313729780288093167554014264153609 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.113371381739395673375094865699588209746096855929868196136712585599264485955982
Short name T48
Test name
Test status
Simulation time 6076748772 ps
CPU time 105.82 seconds
Started Nov 22 02:04:01 PM PST 23
Finished Nov 22 02:05:48 PM PST 23
Peak memory 236316 kb
Host smart-bc648bbe-a6ec-47aa-9cf9-db538797ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113371381739395673375094865699588209746096855929868196136712585599264485955982 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.kmac_app.113371381739395673375094865699588209746096855929868196136712585599264485955982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.64345668365206952776418969733232299727929145911793188436182934016548302501364
Short name T47
Test name
Test status
Simulation time 14830000174 ps
CPU time 380.25 seconds
Started Nov 22 02:03:55 PM PST 23
Finished Nov 22 02:10:15 PM PST 23
Peak memory 243256 kb
Host smart-e26e5864-a4ef-4e43-804f-d6328f3d078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64345668365206952776418969733232299727929145911793188436182934016548302501364 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.kmac_burst_write.64345668365206952776418969733232299727929145911793188436182934016548302501364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.13847540560462117390284381778562875557362449116338597675196787176937286389118
Short name T418
Test name
Test status
Simulation time 7238810904 ps
CPU time 118.14 seconds
Started Nov 22 02:04:20 PM PST 23
Finished Nov 22 02:06:19 PM PST 23
Peak memory 243868 kb
Host smart-40d5b497-c389-4b8c-b017-94361085acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13847540560462117390284381778562875557362449116338597675196787176937286389118 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.kmac_entropy_refresh.13847540560462117390284381778562875557362449116338597675196787176937286389118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.102209043580257768469653973136655354020465509054626349485487536124828041264258
Short name T1009
Test name
Test status
Simulation time 8137821569 ps
CPU time 145.34 seconds
Started Nov 22 02:04:19 PM PST 23
Finished Nov 22 02:06:45 PM PST 23
Peak memory 252728 kb
Host smart-1c34daed-aff8-4249-89c5-11a6dee0bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102209043580257768469653973136655354020465509054626349485487536124828041264258 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.kmac_error.102209043580257768469653973136655354020465509054626349485487536124828041264258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.109021364210224359033565512356354325751402448833454250195491595236265469807928
Short name T883
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.91 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 219212 kb
Host smart-841ab76e-c6f6-4588-a690-ef76ea13e02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109021364210224359033565512356354325751402448833454250195491595236265469807928 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.kmac_key_error.109021364210224359033565512356354325751402448833454250195491595236265469807928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.104495542883498161001778827245038637703772686776863393500358961689962087002834
Short name T1042
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:04:20 PM PST 23
Finished Nov 22 02:04:22 PM PST 23
Peak memory 220400 kb
Host smart-39b52cec-db75-46df-b933-b59a3b540838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104495542883498161001778827245038637703772686776863393500358961689962087002834 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.kmac_lc_escalation.104495542883498161001778827245038637703772686776863393500358961689962087002834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.21091088783141639399144127006675006178037957299340227689200666308050876744679
Short name T810
Test name
Test status
Simulation time 50513696845 ps
CPU time 1003.44 seconds
Started Nov 22 02:04:03 PM PST 23
Finished Nov 22 02:20:47 PM PST 23
Peak memory 306300 kb
Host smart-f287f619-5b9d-4452-a23a-a3a24bdbc9e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21091088783141639399144127006675006178037957299340227689200666308050876744679 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.210910887831416393991441270066750061780379572993402276892006663080508
76744679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.17576940011407668751321436156977855978932339425645905141582189884502076486512
Short name T814
Test name
Test status
Simulation time 7628111361 ps
CPU time 138.71 seconds
Started Nov 22 02:03:58 PM PST 23
Finished Nov 22 02:06:18 PM PST 23
Peak memory 236356 kb
Host smart-dfb0cd3a-bd48-47be-b193-9227e4bf43c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17576940011407668751321436156977855978932339425645905141582189884502076486512 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.kmac_sideload.17576940011407668751321436156977855978932339425645905141582189884502076486512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.69365490316732460133231654585079933682697985242972340117618756898472868955872
Short name T607
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.68 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:04:27 PM PST 23
Peak memory 225380 kb
Host smart-05c38ecc-d7c5-41b7-8ea0-986cf4d91e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69365490316732460133231654585079933682697985242972340117618756898472868955872 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.kmac_smoke.69365490316732460133231654585079933682697985242972340117618756898472868955872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.58268973434245226456276427197707839105724980358783120510761665214402999718459
Short name T406
Test name
Test status
Simulation time 47207151869 ps
CPU time 898.77 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:19:16 PM PST 23
Peak memory 339872 kb
Host smart-afcb40f8-4caa-41f2-822d-fda59ee2b0d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=58268973434245226456276427197707839105724980358783120510761665214402999718459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_st
ress_all.58268973434245226456276427197707839105724980358783120510761665214402999718459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.24011333622549918838887600420060253474032462579991172129964333401186447485022
Short name T164
Test name
Test status
Simulation time 322955517 ps
CPU time 6.14 seconds
Started Nov 22 02:04:01 PM PST 23
Finished Nov 22 02:04:08 PM PST 23
Peak memory 219232 kb
Host smart-1b5253df-b892-40b4-90e3-ab13692e5646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24011333622549918838887600420060253474032462579991172
129964333401186447485022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac.24011333622549918838887600420060253474
032462579991172129964333401186447485022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.65279449312474093683228376868801014435343344470229253001570967405076871628975
Short name T302
Test name
Test status
Simulation time 309259198 ps
CPU time 5.83 seconds
Started Nov 22 02:03:57 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 219220 kb
Host smart-43c2bea5-b027-479e-a54a-9084c2661bb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65279449312474093683228376868801014435343344470229253
001570967405076871628975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.652794493124740936832283768688
01014435343344470229253001570967405076871628975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.74407321584414142178814043526671533886672883728469452641744438295236336566173
Short name T808
Test name
Test status
Simulation time 117329894454 ps
CPU time 2191.69 seconds
Started Nov 22 02:04:00 PM PST 23
Finished Nov 22 02:40:33 PM PST 23
Peak memory 400940 kb
Host smart-03c0d86c-1596-4021-ba99-04354f563cf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=74407321584414142178814043526671533886672883728469452641744438295236336566173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_224.74407321584414142178814043526671533886672883728469452641744438295236336566173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.20278992792280540479753808290936188207026733849355273430267107581806637972553
Short name T847
Test name
Test status
Simulation time 106843317633 ps
CPU time 1884.23 seconds
Started Nov 22 02:03:53 PM PST 23
Finished Nov 22 02:35:18 PM PST 23
Peak memory 376272 kb
Host smart-a7de9fd2-5578-40fe-a9e1-8be7a4fad8a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20278992792280540479753808290936188207026733849355273430267107581806637972553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_256.20278992792280540479753808290936188207026733849355273430267107581806637972553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.64720964205130725796051112575168021882620055759580035906502265601740954873396
Short name T703
Test name
Test status
Simulation time 83520343504 ps
CPU time 1550.68 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:29:51 PM PST 23
Peak memory 338468 kb
Host smart-fbabda11-c740-48ae-9d7c-18ac0450ca68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64720964205130725796051112575168021882620055759580035906502265601740954873396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_384.64720964205130725796051112575168021882620055759580035906502265601740954873396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.82277654901634490496363401328758142209548609244307985000819067932301580646183
Short name T156
Test name
Test status
Simulation time 57499426673 ps
CPU time 1146.8 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 297832 kb
Host smart-e0226ceb-5399-4e14-afda-6caf06cdb2e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82277654901634490496363401328758142209548609244307985000819067932301580646183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_512.82277654901634490496363401328758142209548609244307985000819067932301580646183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.73067620477743610326055945976488904005628386343307163016381181956692453156458
Short name T855
Test name
Test status
Simulation time 320694338954 ps
CPU time 5311.45 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 03:32:32 PM PST 23
Peak memory 674284 kb
Host smart-fb843035-1efd-47ce-8a54-92e2211746ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=73067620477743610326055945976488904005628386343307163016381181956692453156458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.kmac_test_vectors_shake_128.73067620477743610326055945976488904005628386343307163016381181956692453156458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.49152362854979781020489828472016924831416001918805210959767041448841812768715
Short name T651
Test name
Test status
Simulation time 270085708112 ps
CPU time 4697.29 seconds
Started Nov 22 02:03:59 PM PST 23
Finished Nov 22 03:22:18 PM PST 23
Peak memory 577392 kb
Host smart-98cde550-ae1a-4eaf-ac19-29756c87b554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=49152362854979781020489828472016924831416001918805210959767041448841812768715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.kmac_test_vectors_shake_256.49152362854979781020489828472016924831416001918805210959767041448841812768715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.7102707295947154638570704506496648150256015415266881390926308241392342918929
Short name T405
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:04:29 PM PST 23
Finished Nov 22 02:04:30 PM PST 23
Peak memory 219020 kb
Host smart-f1fbacf2-3669-4438-a2e5-15e982d80ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7102707295947154638570704506496648150256015415266881390926308241392342918929 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.kmac_alert_test.7102707295947154638570704506496648150256015415266881390926308241392342918929 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.101237192334215413800611447653047121759841016236226107816274164912134189647353
Short name T1037
Test name
Test status
Simulation time 6076748772 ps
CPU time 98.18 seconds
Started Nov 22 02:04:25 PM PST 23
Finished Nov 22 02:06:04 PM PST 23
Peak memory 236208 kb
Host smart-d162f1df-c5d1-4ae4-8ebc-bbc45a7df06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101237192334215413800611447653047121759841016236226107816274164912134189647353 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.kmac_app.101237192334215413800611447653047121759841016236226107816274164912134189647353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.52915901942431608220230197004722940454221252732285674924342373147195227481810
Short name T303
Test name
Test status
Simulation time 14830000174 ps
CPU time 381.25 seconds
Started Nov 22 02:04:15 PM PST 23
Finished Nov 22 02:10:37 PM PST 23
Peak memory 243212 kb
Host smart-33083ccd-957a-49a3-a57d-ab48d02a48a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52915901942431608220230197004722940454221252732285674924342373147195227481810 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.kmac_burst_write.52915901942431608220230197004722940454221252732285674924342373147195227481810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.63601133690207561162018072411658724310831795057919177658135299873625081872300
Short name T85
Test name
Test status
Simulation time 7238810904 ps
CPU time 109.79 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:06:08 PM PST 23
Peak memory 243680 kb
Host smart-016ae093-0e4b-478e-93af-f130c38880a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63601133690207561162018072411658724310831795057919177658135299873625081872300 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.kmac_entropy_refresh.63601133690207561162018072411658724310831795057919177658135299873625081872300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.84577028729493424908497062490979409173435315808280596363386272621120003585030
Short name T416
Test name
Test status
Simulation time 8137821569 ps
CPU time 154.48 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:06:53 PM PST 23
Peak memory 252728 kb
Host smart-dd822629-d6ec-481a-9a3f-a935f3a242cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84577028729493424908497062490979409173435315808280596363386272621120003585030 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.kmac_error.84577028729493424908497062490979409173435315808280596363386272621120003585030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.28222013602415344186311442378130925483666122637423743114885758944117950692935
Short name T927
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.67 seconds
Started Nov 22 02:04:16 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 219244 kb
Host smart-86ee5e86-c1c3-4f53-9c7e-66c2204cc42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28222013602415344186311442378130925483666122637423743114885758944117950692935 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.kmac_key_error.28222013602415344186311442378130925483666122637423743114885758944117950692935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.80551696523807033972494181753817547698929892289626696022953113245440139489623
Short name T397
Test name
Test status
Simulation time 72761090 ps
CPU time 1.51 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:19 PM PST 23
Peak memory 220420 kb
Host smart-92859d23-5039-4aa2-86b1-f0a98c98c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80551696523807033972494181753817547698929892289626696022953113245440139489623 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.kmac_lc_escalation.80551696523807033972494181753817547698929892289626696022953113245440139489623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.40741092912231637151353246239974334623507947604621310369931018577769443674189
Short name T480
Test name
Test status
Simulation time 50513696845 ps
CPU time 1006.12 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:21:04 PM PST 23
Peak memory 306312 kb
Host smart-e9c4f7c7-291c-44a4-aad7-cd22d7792232
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741092912231637151353246239974334623507947604621310369931018577769443674189 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.407410929122316371513532462399743346235079476046213103699310185777694
43674189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.69155422410154422724393737306535300238637030148229900227687433133076379780464
Short name T157
Test name
Test status
Simulation time 7628111361 ps
CPU time 142.51 seconds
Started Nov 22 02:04:16 PM PST 23
Finished Nov 22 02:06:39 PM PST 23
Peak memory 236400 kb
Host smart-17049093-87a7-4c12-a4a8-ab03617444c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69155422410154422724393737306535300238637030148229900227687433133076379780464 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.kmac_sideload.69155422410154422724393737306535300238637030148229900227687433133076379780464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.14312417201743747288775457699221221185182927753126290074966079448301657220758
Short name T588
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.9 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:45 PM PST 23
Peak memory 225300 kb
Host smart-c83325ac-2fe0-4def-96b0-4070b9e67e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14312417201743747288775457699221221185182927753126290074966079448301657220758 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.kmac_smoke.14312417201743747288775457699221221185182927753126290074966079448301657220758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.84118765623234332906023088600475309890828355577708378933793647876975068120810
Short name T339
Test name
Test status
Simulation time 47207151869 ps
CPU time 877.57 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 339800 kb
Host smart-a12ef9d6-9727-4871-aef0-35258285e603
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=84118765623234332906023088600475309890828355577708378933793647876975068120810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_st
ress_all.84118765623234332906023088600475309890828355577708378933793647876975068120810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3733684128146335942436201143940172880303360596287633149581172553448649817222
Short name T280
Test name
Test status
Simulation time 322955517 ps
CPU time 5.91 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:24 PM PST 23
Peak memory 219308 kb
Host smart-31a8eab6-3466-4ba3-a3a1-88cedf4c19aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37336841281463359424362011439401728803033605962876331
49581172553448649817222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac.373368412814633594243620114394017288030
3360596287633149581172553448649817222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.108175982757430570493129763584467800507417590072392142042749267312429972139641
Short name T989
Test name
Test status
Simulation time 309259198 ps
CPU time 5.84 seconds
Started Nov 22 02:04:41 PM PST 23
Finished Nov 22 02:04:48 PM PST 23
Peak memory 219264 kb
Host smart-5016a9e2-c64b-4b38-a85c-6e9146adb394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10817598275743057049312976358446780050741759007239214
2042749267312429972139641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.10817598275743057049312976358
4467800507417590072392142042749267312429972139641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.59913401280570098905137608495076284517405458472331708961414226038282441217938
Short name T853
Test name
Test status
Simulation time 117329894454 ps
CPU time 2080.81 seconds
Started Nov 22 02:04:19 PM PST 23
Finished Nov 22 02:39:01 PM PST 23
Peak memory 400904 kb
Host smart-8875238d-7692-40fe-8f4d-37372cbae4ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59913401280570098905137608495076284517405458472331708961414226038282441217938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_224.59913401280570098905137608495076284517405458472331708961414226038282441217938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.34773420218782696447247283194781546412099034705794492797347864932316551641801
Short name T197
Test name
Test status
Simulation time 106843317633 ps
CPU time 1989.92 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:37:30 PM PST 23
Peak memory 376408 kb
Host smart-4f512349-3f23-4eef-8486-d55692b63ed7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=34773420218782696447247283194781546412099034705794492797347864932316551641801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_256.34773420218782696447247283194781546412099034705794492797347864932316551641801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.101645557237167213091235679709296924736846412086459629327798782826588135676098
Short name T466
Test name
Test status
Simulation time 83520343504 ps
CPU time 1550.41 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:30:08 PM PST 23
Peak memory 338496 kb
Host smart-a586055a-9de5-4667-9115-015c47bac3d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101645557237167213091235679709296924736846412086459629327798782826588135676098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.kmac_test_vectors_sha3_384.101645557237167213091235679709296924736846412086459629327798782826588135676098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.91357629433933213952703470490239722864934808332101949008933424566210956450853
Short name T1051
Test name
Test status
Simulation time 57499426673 ps
CPU time 1186.39 seconds
Started Nov 22 02:04:15 PM PST 23
Finished Nov 22 02:24:02 PM PST 23
Peak memory 297788 kb
Host smart-4d48de31-c3be-4796-b001-edf7f59d32e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91357629433933213952703470490239722864934808332101949008933424566210956450853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_512.91357629433933213952703470490239722864934808332101949008933424566210956450853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.110906937021618351395079634850108923096774622825752132147968990770331858578438
Short name T144
Test name
Test status
Simulation time 320694338954 ps
CPU time 5563.38 seconds
Started Nov 22 02:04:16 PM PST 23
Finished Nov 22 03:37:00 PM PST 23
Peak memory 673072 kb
Host smart-6813a6a6-96a7-43d8-82b5-a9398a2527b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=110906937021618351395079634850108923096774622825752132147968990770331858578438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.kmac_test_vectors_shake_128.110906937021618351395079634850108923096774622825752132147968990770331858578438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.50603539303930465128103518495663916913496549350502356901717662567153318894785
Short name T1061
Test name
Test status
Simulation time 270085708112 ps
CPU time 4648.48 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 03:21:47 PM PST 23
Peak memory 577388 kb
Host smart-010843d9-d9b7-4cb9-ba8b-e723499edaa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=50603539303930465128103518495663916913496549350502356901717662567153318894785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.kmac_test_vectors_shake_256.50603539303930465128103518495663916913496549350502356901717662567153318894785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.26308027556987625431332752048432136425025134015147557866868945317251840134633
Short name T275
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:04:15 PM PST 23
Finished Nov 22 02:04:17 PM PST 23
Peak memory 218996 kb
Host smart-054f1b58-996a-402a-8038-a382a50c90d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308027556987625431332752048432136425025134015147557866868945317251840134633 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.kmac_alert_test.26308027556987625431332752048432136425025134015147557866868945317251840134633 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.60709001457298697775832220761965122588866470727207856284839298815595594051422
Short name T540
Test name
Test status
Simulation time 6076748772 ps
CPU time 93.97 seconds
Started Nov 22 02:04:20 PM PST 23
Finished Nov 22 02:05:55 PM PST 23
Peak memory 236012 kb
Host smart-dbef157c-feea-43d7-bf3f-9357794f5d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60709001457298697775832220761965122588866470727207856284839298815595594051422 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_app.60709001457298697775832220761965122588866470727207856284839298815595594051422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.52669074405408690300958023691753760670321986303757594019850482910138047319658
Short name T392
Test name
Test status
Simulation time 14830000174 ps
CPU time 400.31 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:10:58 PM PST 23
Peak memory 243200 kb
Host smart-5c9929c7-9de6-4372-8dc9-dca35bdd3180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52669074405408690300958023691753760670321986303757594019850482910138047319658 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.kmac_burst_write.52669074405408690300958023691753760670321986303757594019850482910138047319658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.106556424650132790249766074386097173214110319784387709590165701845559601682332
Short name T693
Test name
Test status
Simulation time 7238810904 ps
CPU time 113.71 seconds
Started Nov 22 02:04:23 PM PST 23
Finished Nov 22 02:06:17 PM PST 23
Peak memory 243912 kb
Host smart-00a6bde0-ae06-46da-878f-365f3dd4d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106556424650132790249766074386097173214110319784387709590165701845559601682332 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.kmac_entropy_refresh.106556424650132790249766074386097173214110319784387709590165701845559601682332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.66447247516610221710787410488765151913069410585988321324163258210431265150980
Short name T766
Test name
Test status
Simulation time 8137821569 ps
CPU time 141.12 seconds
Started Nov 22 02:04:14 PM PST 23
Finished Nov 22 02:06:36 PM PST 23
Peak memory 252740 kb
Host smart-c8e3dbaf-7062-43e2-a930-ca3092dbec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66447247516610221710787410488765151913069410585988321324163258210431265150980 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.kmac_error.66447247516610221710787410488765151913069410585988321324163258210431265150980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.52767086353572125453629357895839548057040464200482067942076731783095069713383
Short name T554
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.78 seconds
Started Nov 22 02:04:24 PM PST 23
Finished Nov 22 02:04:30 PM PST 23
Peak memory 219224 kb
Host smart-96911f99-f6ff-4fee-acb0-f499622d2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52767086353572125453629357895839548057040464200482067942076731783095069713383 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.kmac_key_error.52767086353572125453629357895839548057040464200482067942076731783095069713383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.95298179837077333550154275982548923475585427306037029715391581003898897751503
Short name T132
Test name
Test status
Simulation time 72761090 ps
CPU time 1.52 seconds
Started Nov 22 02:04:14 PM PST 23
Finished Nov 22 02:04:16 PM PST 23
Peak memory 220392 kb
Host smart-fe8f5f2d-163b-4d3a-80d6-ad0b0faa7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95298179837077333550154275982548923475585427306037029715391581003898897751503 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.kmac_lc_escalation.95298179837077333550154275982548923475585427306037029715391581003898897751503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.95988550480590357623558834831766840249035547048598460053789246749045561771664
Short name T511
Test name
Test status
Simulation time 50513696845 ps
CPU time 954.99 seconds
Started Nov 22 02:04:25 PM PST 23
Finished Nov 22 02:20:21 PM PST 23
Peak memory 306308 kb
Host smart-f196f680-3016-4960-9b22-2ee405efb773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95988550480590357623558834831766840249035547048598460053789246749045561771664 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.959885504805903576235588348317668402490355470485984600537892467490455
61771664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.40648092888329534501856028698668163372743084444697637278710997831951624433719
Short name T675
Test name
Test status
Simulation time 7628111361 ps
CPU time 142.05 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:06:40 PM PST 23
Peak memory 236376 kb
Host smart-89dd2467-779c-4b1b-a2f9-258d3c78b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40648092888329534501856028698668163372743084444697637278710997831951624433719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.kmac_sideload.40648092888329534501856028698668163372743084444697637278710997831951624433719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.8021363634677247630270652483746750958604522330970993793725382018093082755352
Short name T1043
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.14 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:04:45 PM PST 23
Peak memory 225352 kb
Host smart-496158d3-a170-4b54-8b22-a1aab9a90300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8021363634677247630270652483746750958604522330970993793725382018093082755352 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.kmac_smoke.8021363634677247630270652483746750958604522330970993793725382018093082755352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.32633263566793238909454236262023550798187884626399393798368906654083385293845
Short name T40
Test name
Test status
Simulation time 47207151869 ps
CPU time 868.19 seconds
Started Nov 22 02:04:24 PM PST 23
Finished Nov 22 02:18:53 PM PST 23
Peak memory 339792 kb
Host smart-82f1030c-83e3-4ec8-a005-53f750986422
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=32633263566793238909454236262023550798187884626399393798368906654083385293845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_st
ress_all.32633263566793238909454236262023550798187884626399393798368906654083385293845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.70221669067475301579679765954675604073572846003556043556146274257543339477332
Short name T677
Test name
Test status
Simulation time 322955517 ps
CPU time 6.17 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 219256 kb
Host smart-5afc512a-8c74-4260-9cf8-080e05ffb8b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70221669067475301579679765954675604073572846003556043
556146274257543339477332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac.70221669067475301579679765954675604073
572846003556043556146274257543339477332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.76409688435307389491533831866499606390167166856750768713262680316341224505019
Short name T698
Test name
Test status
Simulation time 309259198 ps
CPU time 5.63 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:24 PM PST 23
Peak memory 219192 kb
Host smart-601d50de-8e41-4100-8369-e1703b3d9b89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76409688435307389491533831866499606390167166856750768
713262680316341224505019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.764096884353073894915338318664
99606390167166856750768713262680316341224505019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.38241696277488891655373148426799093945205902364113099388101150635998198876823
Short name T206
Test name
Test status
Simulation time 117329894454 ps
CPU time 2081.31 seconds
Started Nov 22 02:04:14 PM PST 23
Finished Nov 22 02:38:57 PM PST 23
Peak memory 400892 kb
Host smart-22a81c3d-982b-4b1f-88e8-be5edd261603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38241696277488891655373148426799093945205902364113099388101150635998198876823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_224.38241696277488891655373148426799093945205902364113099388101150635998198876823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.69905965800590619907110340451728551830761885257674842362675641797790399202392
Short name T504
Test name
Test status
Simulation time 106843317633 ps
CPU time 1909.46 seconds
Started Nov 22 02:04:16 PM PST 23
Finished Nov 22 02:36:07 PM PST 23
Peak memory 376336 kb
Host smart-f88949bd-0553-4323-96ab-aa213e1c6855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=69905965800590619907110340451728551830761885257674842362675641797790399202392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_256.69905965800590619907110340451728551830761885257674842362675641797790399202392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.49004189549300913289296698833733263242071255700679187127216027839535299856609
Short name T441
Test name
Test status
Simulation time 83520343504 ps
CPU time 1618.26 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:31:17 PM PST 23
Peak memory 338476 kb
Host smart-7df5bd02-aaa3-4d0a-8e77-a832021d5a31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=49004189549300913289296698833733263242071255700679187127216027839535299856609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_384.49004189549300913289296698833733263242071255700679187127216027839535299856609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.105833556006629082391806588650620090256754674230282287802832493568577373629981
Short name T756
Test name
Test status
Simulation time 57499426673 ps
CPU time 1171.86 seconds
Started Nov 22 02:04:24 PM PST 23
Finished Nov 22 02:23:56 PM PST 23
Peak memory 297764 kb
Host smart-a225e380-2047-42db-a73d-90fe5e2e4c71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=105833556006629082391806588650620090256754674230282287802832493568577373629981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.kmac_test_vectors_sha3_512.105833556006629082391806588650620090256754674230282287802832493568577373629981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.26704866097725456537116459184300782679887061332635179949791104849532625374152
Short name T854
Test name
Test status
Simulation time 320694338954 ps
CPU time 5457.06 seconds
Started Nov 22 02:04:23 PM PST 23
Finished Nov 22 03:35:21 PM PST 23
Peak memory 674320 kb
Host smart-aec170b2-32f8-415f-878c-2868f5b45d7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=26704866097725456537116459184300782679887061332635179949791104849532625374152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_test_vectors_shake_128.26704866097725456537116459184300782679887061332635179949791104849532625374152 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.65182402142764456290956589914792524358367942661758000724295336293738308468077
Short name T267
Test name
Test status
Simulation time 270085708112 ps
CPU time 4626.27 seconds
Started Nov 22 02:04:23 PM PST 23
Finished Nov 22 03:21:30 PM PST 23
Peak memory 577388 kb
Host smart-4169eb8a-852b-4596-80bf-c8aa97753579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=65182402142764456290956589914792524358367942661758000724295336293738308468077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_test_vectors_shake_256.65182402142764456290956589914792524358367942661758000724295336293738308468077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.71904153503581165026038200636864415982906416569364567883036786770841039236860
Short name T735
Test name
Test status
Simulation time 21118646 ps
CPU time 0.83 seconds
Started Nov 22 02:04:40 PM PST 23
Finished Nov 22 02:04:41 PM PST 23
Peak memory 219012 kb
Host smart-ef5d1977-5385-403d-99cd-13fd38e9d42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71904153503581165026038200636864415982906416569364567883036786770841039236860 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.kmac_alert_test.71904153503581165026038200636864415982906416569364567883036786770841039236860 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.92379473630531291601270959219870707603146854055399704930784218289924972593820
Short name T838
Test name
Test status
Simulation time 6076748772 ps
CPU time 105.64 seconds
Started Nov 22 02:04:41 PM PST 23
Finished Nov 22 02:06:27 PM PST 23
Peak memory 236236 kb
Host smart-b41fd3c0-7367-4d45-a53d-c6d25100f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92379473630531291601270959219870707603146854055399704930784218289924972593820 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_app.92379473630531291601270959219870707603146854055399704930784218289924972593820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.114639717275735010503072042328612619868429695959270221349364838354318644863019
Short name T823
Test name
Test status
Simulation time 14830000174 ps
CPU time 364.35 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:10:24 PM PST 23
Peak memory 243164 kb
Host smart-e103264e-8c52-4d99-a756-87e9acf4cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114639717275735010503072042328612619868429695959270221349364838354318644863019 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.kmac_burst_write.114639717275735010503072042328612619868429695959270221349364838354318644863019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.76780396300061147439287059555886767044552445045871595461546933261802858599427
Short name T893
Test name
Test status
Simulation time 7238810904 ps
CPU time 113.88 seconds
Started Nov 22 02:04:42 PM PST 23
Finished Nov 22 02:06:37 PM PST 23
Peak memory 243868 kb
Host smart-c73b50b4-88e2-48d5-bcd8-d9e64429164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76780396300061147439287059555886767044552445045871595461546933261802858599427 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.kmac_entropy_refresh.76780396300061147439287059555886767044552445045871595461546933261802858599427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.80236776705115944517993902444364708111612821041268716686802195232074851424908
Short name T1001
Test name
Test status
Simulation time 8137821569 ps
CPU time 137.32 seconds
Started Nov 22 02:04:52 PM PST 23
Finished Nov 22 02:07:10 PM PST 23
Peak memory 252640 kb
Host smart-98d95388-6324-4400-be8a-9716fd318750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80236776705115944517993902444364708111612821041268716686802195232074851424908 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.kmac_error.80236776705115944517993902444364708111612821041268716686802195232074851424908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1631593717970852499581247883125655095217398777581715913533945624420659432022
Short name T796
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.87 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:07 PM PST 23
Peak memory 219224 kb
Host smart-01241a55-c0b8-486d-9725-85288e458fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631593717970852499581247883125655095217398777581715913533945624420659432022 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.kmac_key_error.1631593717970852499581247883125655095217398777581715913533945624420659432022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.17699560552763369593802705665312900708107906833880144329001671224324523919333
Short name T526
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:04:52 PM PST 23
Finished Nov 22 02:04:54 PM PST 23
Peak memory 220512 kb
Host smart-aa48f1b0-07cb-426d-b75b-5772a2a452ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17699560552763369593802705665312900708107906833880144329001671224324523919333 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.kmac_lc_escalation.17699560552763369593802705665312900708107906833880144329001671224324523919333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.75747769011258800701706499145492051432941917711789705048854208944044152155998
Short name T840
Test name
Test status
Simulation time 50513696845 ps
CPU time 1048.88 seconds
Started Nov 22 02:04:31 PM PST 23
Finished Nov 22 02:22:00 PM PST 23
Peak memory 306244 kb
Host smart-666c3bd7-1370-419d-aa93-d45f4389d403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75747769011258800701706499145492051432941917711789705048854208944044152155998 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.757477690112588007017064991454920514329419177117897050488542089440441
52155998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.103953854667749182666505891677979738228737499954214975509536891850834326613251
Short name T700
Test name
Test status
Simulation time 7628111361 ps
CPU time 140.64 seconds
Started Nov 22 02:04:19 PM PST 23
Finished Nov 22 02:06:41 PM PST 23
Peak memory 236304 kb
Host smart-a21fbbe0-bf55-45e9-a3ed-e0ac600cf014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103953854667749182666505891677979738228737499954214975509536891850834326613251 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.kmac_sideload.103953854667749182666505891677979738228737499954214975509536891850834326613251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.80943786676089139508176708675467480496979093730369591351675638955792439604238
Short name T841
Test name
Test status
Simulation time 1925406983 ps
CPU time 28.66 seconds
Started Nov 22 02:04:17 PM PST 23
Finished Nov 22 02:04:46 PM PST 23
Peak memory 225336 kb
Host smart-db3386b5-3ac8-411b-9444-38d8dab5b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80943786676089139508176708675467480496979093730369591351675638955792439604238 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.kmac_smoke.80943786676089139508176708675467480496979093730369591351675638955792439604238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.64500530909210923653141744791441653449741607421817967423085883526850163101632
Short name T42
Test name
Test status
Simulation time 47207151869 ps
CPU time 875.78 seconds
Started Nov 22 02:04:50 PM PST 23
Finished Nov 22 02:19:27 PM PST 23
Peak memory 339828 kb
Host smart-cd70a669-0be6-4894-87c3-658cfe6d80d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=64500530909210923653141744791441653449741607421817967423085883526850163101632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_st
ress_all.64500530909210923653141744791441653449741607421817967423085883526850163101632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.86091575381133642646633616897084464118689547377829719613359575106167133743911
Short name T305
Test name
Test status
Simulation time 322955517 ps
CPU time 6.04 seconds
Started Nov 22 02:04:34 PM PST 23
Finished Nov 22 02:04:41 PM PST 23
Peak memory 219284 kb
Host smart-0aec42e8-85fe-41b3-9fa9-74d65458c649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86091575381133642646633616897084464118689547377829719
613359575106167133743911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac.86091575381133642646633616897084464118
689547377829719613359575106167133743911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.64437429702727628202695002247714729718464815993211229001610980906681622020745
Short name T394
Test name
Test status
Simulation time 309259198 ps
CPU time 5.69 seconds
Started Nov 22 02:04:35 PM PST 23
Finished Nov 22 02:04:41 PM PST 23
Peak memory 219280 kb
Host smart-63a43cc0-b1b7-439a-9672-8744c0ca3771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64437429702727628202695002247714729718464815993211229
001610980906681622020745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.644374297027276282026950022477
14729718464815993211229001610980906681622020745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.95355414302648852429624905478496893352283206929658679591390559642079706022902
Short name T368
Test name
Test status
Simulation time 117329894454 ps
CPU time 2197.91 seconds
Started Nov 22 02:04:21 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 400840 kb
Host smart-7922e433-7e39-4d0b-ab6e-3dee57268a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=95355414302648852429624905478496893352283206929658679591390559642079706022902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_224.95355414302648852429624905478496893352283206929658679591390559642079706022902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.70578231318543215590022849427724946855174429469598061037479824873072980012240
Short name T896
Test name
Test status
Simulation time 106843317633 ps
CPU time 1905.24 seconds
Started Nov 22 02:04:32 PM PST 23
Finished Nov 22 02:36:18 PM PST 23
Peak memory 376420 kb
Host smart-cb4da1d2-2fa4-4477-be86-15677a0075f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=70578231318543215590022849427724946855174429469598061037479824873072980012240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_256.70578231318543215590022849427724946855174429469598061037479824873072980012240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.96311421229090505001337752243830374052461714568484397621622190805685799169564
Short name T236
Test name
Test status
Simulation time 83520343504 ps
CPU time 1607.17 seconds
Started Nov 22 02:04:18 PM PST 23
Finished Nov 22 02:31:06 PM PST 23
Peak memory 338396 kb
Host smart-3d2efe96-f75f-47fe-9585-e9e18eb6ec2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=96311421229090505001337752243830374052461714568484397621622190805685799169564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_384.96311421229090505001337752243830374052461714568484397621622190805685799169564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.113535467146353217674234775226120474419075657057574434948880468607065763558629
Short name T471
Test name
Test status
Simulation time 57499426673 ps
CPU time 1226.4 seconds
Started Nov 22 02:04:41 PM PST 23
Finished Nov 22 02:25:08 PM PST 23
Peak memory 297800 kb
Host smart-45ebf8eb-a3d5-46d4-b1a0-d632968a25db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113535467146353217674234775226120474419075657057574434948880468607065763558629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.kmac_test_vectors_sha3_512.113535467146353217674234775226120474419075657057574434948880468607065763558629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.48930520279914879867434736912674526624014117322189108476340888788164416217321
Short name T401
Test name
Test status
Simulation time 320694338954 ps
CPU time 5621.98 seconds
Started Nov 22 02:04:16 PM PST 23
Finished Nov 22 03:37:59 PM PST 23
Peak memory 674292 kb
Host smart-014c6d13-0db3-423a-9c34-9c06b8093478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=48930520279914879867434736912674526624014117322189108476340888788164416217321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_test_vectors_shake_128.48930520279914879867434736912674526624014117322189108476340888788164416217321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.69375316995347968541620455109593616070567909888364306514154479384244204619130
Short name T255
Test name
Test status
Simulation time 270085708112 ps
CPU time 4590.48 seconds
Started Nov 22 02:04:51 PM PST 23
Finished Nov 22 03:21:23 PM PST 23
Peak memory 577392 kb
Host smart-3e1e68d5-546b-48a9-8e41-0febbdfbf20e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=69375316995347968541620455109593616070567909888364306514154479384244204619130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_test_vectors_shake_256.69375316995347968541620455109593616070567909888364306514154479384244204619130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.15761235974660506848092512560160916380148584707465657391528770444474751424890
Short name T939
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:02 PM PST 23
Peak memory 219024 kb
Host smart-3fd0cb6b-43b1-42b2-a2eb-8f5f85b3f58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761235974660506848092512560160916380148584707465657391528770444474751424890 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.kmac_alert_test.15761235974660506848092512560160916380148584707465657391528770444474751424890 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.33448978538390535679844260695086157566006227759314970756780351171184540201602
Short name T288
Test name
Test status
Simulation time 6076748772 ps
CPU time 105.09 seconds
Started Nov 22 02:04:55 PM PST 23
Finished Nov 22 02:06:41 PM PST 23
Peak memory 236212 kb
Host smart-34b54a22-573d-43d0-b5a9-45e0db4d9b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33448978538390535679844260695086157566006227759314970756780351171184540201602 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.kmac_app.33448978538390535679844260695086157566006227759314970756780351171184540201602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.32158350184472271898743819540551252982853313276446254369518403977836658642858
Short name T879
Test name
Test status
Simulation time 14830000174 ps
CPU time 380.04 seconds
Started Nov 22 02:04:48 PM PST 23
Finished Nov 22 02:11:09 PM PST 23
Peak memory 243148 kb
Host smart-88fe8d41-b8c7-4583-ad25-2d20646b6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32158350184472271898743819540551252982853313276446254369518403977836658642858 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.kmac_burst_write.32158350184472271898743819540551252982853313276446254369518403977836658642858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.42099796223764407369678541391041812476250803141278962316611687990381878564506
Short name T605
Test name
Test status
Simulation time 7238810904 ps
CPU time 120.22 seconds
Started Nov 22 02:04:40 PM PST 23
Finished Nov 22 02:06:40 PM PST 23
Peak memory 243904 kb
Host smart-2c070594-75ca-4cfb-a057-018013a0b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42099796223764407369678541391041812476250803141278962316611687990381878564506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.kmac_entropy_refresh.42099796223764407369678541391041812476250803141278962316611687990381878564506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.60314898858146723585462754258373842796566596799154391170280356544293797306277
Short name T1069
Test name
Test status
Simulation time 8137821569 ps
CPU time 143.02 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 02:07:13 PM PST 23
Peak memory 252772 kb
Host smart-5dfb0bbd-68a6-4cb3-8877-abe60e275a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60314898858146723585462754258373842796566596799154391170280356544293797306277 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.kmac_error.60314898858146723585462754258373842796566596799154391170280356544293797306277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.90202895163644977720641400987152228621329773829841284802111220933895389983
Short name T867
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.77 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:09 PM PST 23
Peak memory 219256 kb
Host smart-8e26102c-26d6-40c2-90c7-0abdc6299184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90202895163644977720641400987152228621329773829841284802111220933895389983 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.kmac_key_error.90202895163644977720641400987152228621329773829841284802111220933895389983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.78785060460055824988582115231697485516733719764215129524475620992256161378555
Short name T1003
Test name
Test status
Simulation time 72761090 ps
CPU time 1.46 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 220444 kb
Host smart-e0e5bca7-fda2-4aa5-9905-81ea7c8c536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78785060460055824988582115231697485516733719764215129524475620992256161378555 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.kmac_lc_escalation.78785060460055824988582115231697485516733719764215129524475620992256161378555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.98405783530356334256153465012933867027123875990795415727003332715399572104387
Short name T711
Test name
Test status
Simulation time 50513696845 ps
CPU time 989.62 seconds
Started Nov 22 02:04:48 PM PST 23
Finished Nov 22 02:21:19 PM PST 23
Peak memory 306324 kb
Host smart-b35469d7-285e-46b1-8acf-5cdc2ba0f09f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98405783530356334256153465012933867027123875990795415727003332715399572104387 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.984057835303563342561534650129338670271238759907954157270033327153995
72104387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.48323560308565778207792220894281892522839115030769167891116785107809710484534
Short name T323
Test name
Test status
Simulation time 7628111361 ps
CPU time 145.02 seconds
Started Nov 22 02:04:51 PM PST 23
Finished Nov 22 02:07:17 PM PST 23
Peak memory 236396 kb
Host smart-8e5426f7-09da-4e72-9d67-f37570a8c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48323560308565778207792220894281892522839115030769167891116785107809710484534 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.kmac_sideload.48323560308565778207792220894281892522839115030769167891116785107809710484534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.46996862308861882140436150231911230049552472878148525563573004623403879412926
Short name T247
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.72 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:28 PM PST 23
Peak memory 225400 kb
Host smart-02b81eae-7610-4e05-bb0d-8fd2bcdceb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46996862308861882140436150231911230049552472878148525563573004623403879412926 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.kmac_smoke.46996862308861882140436150231911230049552472878148525563573004623403879412926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.62056754801363266400036460064784338408572872948186740471426427879941674790855
Short name T657
Test name
Test status
Simulation time 47207151869 ps
CPU time 872.84 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 02:19:23 PM PST 23
Peak memory 339824 kb
Host smart-6b62f194-ba11-43a5-96f2-419099be7e29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62056754801363266400036460064784338408572872948186740471426427879941674790855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_st
ress_all.62056754801363266400036460064784338408572872948186740471426427879941674790855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.12672839663926451662921310778809715978116216180112526660524283229646308646371
Short name T553
Test name
Test status
Simulation time 322955517 ps
CPU time 5.77 seconds
Started Nov 22 02:04:48 PM PST 23
Finished Nov 22 02:04:54 PM PST 23
Peak memory 219212 kb
Host smart-2fa49bbe-14cb-400b-bb50-49f65e9053e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12672839663926451662921310778809715978116216180112526
660524283229646308646371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac.12672839663926451662921310778809715978
116216180112526660524283229646308646371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.43545042371043881039814994619073818679163078108703385384085478232243444202571
Short name T370
Test name
Test status
Simulation time 309259198 ps
CPU time 5.73 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:05:14 PM PST 23
Peak memory 219236 kb
Host smart-d41ad7ad-751b-419a-a1af-1ca769376e41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43545042371043881039814994619073818679163078108703385
384085478232243444202571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.435450423710438810398149946190
73818679163078108703385384085478232243444202571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.15032603360530608710967713832139503677799670047469767943994495503618064566008
Short name T216
Test name
Test status
Simulation time 117329894454 ps
CPU time 2009.54 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 400872 kb
Host smart-33919a8f-4b96-48a2-9883-3a98ee5e0e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=15032603360530608710967713832139503677799670047469767943994495503618064566008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.kmac_test_vectors_sha3_224.15032603360530608710967713832139503677799670047469767943994495503618064566008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.57699602048031187411526222734784680613057398181992254174171059629943273081343
Short name T1045
Test name
Test status
Simulation time 106843317633 ps
CPU time 1995.16 seconds
Started Nov 22 02:04:52 PM PST 23
Finished Nov 22 02:38:08 PM PST 23
Peak memory 376400 kb
Host smart-d393104c-548e-453c-b924-e9d2dc6aa87e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57699602048031187411526222734784680613057398181992254174171059629943273081343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.kmac_test_vectors_sha3_256.57699602048031187411526222734784680613057398181992254174171059629943273081343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.31668313008582276210471330616372776259944524565868361364319858145817442462826
Short name T789
Test name
Test status
Simulation time 83520343504 ps
CPU time 1600.91 seconds
Started Nov 22 02:04:40 PM PST 23
Finished Nov 22 02:31:21 PM PST 23
Peak memory 338476 kb
Host smart-b1c40cb1-3dfe-46dc-9ad3-60f872c2f5f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=31668313008582276210471330616372776259944524565868361364319858145817442462826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.kmac_test_vectors_sha3_384.31668313008582276210471330616372776259944524565868361364319858145817442462826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.106643341038793545287792936924160979545177852952548973647242330815710233887786
Short name T801
Test name
Test status
Simulation time 57499426673 ps
CPU time 1173.42 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:24:35 PM PST 23
Peak memory 297792 kb
Host smart-5c5c9450-5ad7-4877-94e6-eba8b167ce33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=106643341038793545287792936924160979545177852952548973647242330815710233887786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.kmac_test_vectors_sha3_512.106643341038793545287792936924160979545177852952548973647242330815710233887786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.97767827976081264855125402487619691755166265532683971448501431315110934661290
Short name T965
Test name
Test status
Simulation time 320694338954 ps
CPU time 5379.16 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 03:34:47 PM PST 23
Peak memory 674244 kb
Host smart-42f37fee-8ffd-4a3c-8816-aa5ee0ee2509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97767827976081264855125402487619691755166265532683971448501431315110934661290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.kmac_test_vectors_shake_128.97767827976081264855125402487619691755166265532683971448501431315110934661290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.63432742781882139423585266511190408570419049927393299911853730870164412556467
Short name T799
Test name
Test status
Simulation time 270085708112 ps
CPU time 4443.08 seconds
Started Nov 22 02:04:48 PM PST 23
Finished Nov 22 03:18:52 PM PST 23
Peak memory 577328 kb
Host smart-f68caa54-bcd4-4ceb-9bac-0ef793d3a6fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=63432742781882139423585266511190408570419049927393299911853730870164412556467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.kmac_test_vectors_shake_256.63432742781882139423585266511190408570419049927393299911853730870164412556467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.15072143188845934099124233618607666487191249378626521730617046437018485840846
Short name T264
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:05 PM PST 23
Peak memory 219016 kb
Host smart-ba51b2e3-f496-4c4e-b22d-39b5d2661aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15072143188845934099124233618607666487191249378626521730617046437018485840846 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.kmac_alert_test.15072143188845934099124233618607666487191249378626521730617046437018485840846 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.20727211611611817394784538960917864228890032022889175846679076693863583607743
Short name T109
Test name
Test status
Simulation time 6076748772 ps
CPU time 103.31 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:06:48 PM PST 23
Peak memory 236236 kb
Host smart-aacbd9f7-87e6-48d7-809c-4fb3aef7dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20727211611611817394784538960917864228890032022889175846679076693863583607743 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.kmac_app.20727211611611817394784538960917864228890032022889175846679076693863583607743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.5204973247162478513067786826600703450805719605343998060580439170402107473052
Short name T948
Test name
Test status
Simulation time 14830000174 ps
CPU time 370.93 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:11:16 PM PST 23
Peak memory 243240 kb
Host smart-bb650365-ec56-40b8-a141-511cbb13aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5204973247162478513067786826600703450805719605343998060580439170402107473052 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.kmac_burst_write.5204973247162478513067786826600703450805719605343998060580439170402107473052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.23768827293721119333951747589432892377299632478414368167612709311646617487444
Short name T817
Test name
Test status
Simulation time 7238810904 ps
CPU time 114.77 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:06:54 PM PST 23
Peak memory 243908 kb
Host smart-e66be200-8eaa-4ebe-adc2-3e30f1c6e569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23768827293721119333951747589432892377299632478414368167612709311646617487444 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.kmac_entropy_refresh.23768827293721119333951747589432892377299632478414368167612709311646617487444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.68360284230958698979308374070576950289481129323653549674056869278613125078077
Short name T815
Test name
Test status
Simulation time 8137821569 ps
CPU time 147.75 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:07:30 PM PST 23
Peak memory 252776 kb
Host smart-e136e16b-d419-43c2-b1f6-f23b09671b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68360284230958698979308374070576950289481129323653549674056869278613125078077 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.kmac_error.68360284230958698979308374070576950289481129323653549674056869278613125078077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.80730548209523491350517905436873051185216135751052294752958421875417008221064
Short name T470
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.78 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219184 kb
Host smart-66c52238-0ac9-41ba-9e26-903f88fcc003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80730548209523491350517905436873051185216135751052294752958421875417008221064 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.kmac_key_error.80730548209523491350517905436873051185216135751052294752958421875417008221064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.26642961137733550062035241993426784438825691132958721982869052941746952214475
Short name T1067
Test name
Test status
Simulation time 72761090 ps
CPU time 1.54 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:05:10 PM PST 23
Peak memory 220440 kb
Host smart-3ba8ab4e-f87f-4e2a-b00d-aa7f391572d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26642961137733550062035241993426784438825691132958721982869052941746952214475 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.kmac_lc_escalation.26642961137733550062035241993426784438825691132958721982869052941746952214475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.27218928060854674171260674272205990761315607508474393120365972588453570514622
Short name T579
Test name
Test status
Simulation time 50513696845 ps
CPU time 988.96 seconds
Started Nov 22 02:04:57 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 306308 kb
Host smart-7c5720e2-c728-4af8-80ee-70cdfb9c3ee3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218928060854674171260674272205990761315607508474393120365972588453570514622 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.272189280608546741712606742722059907613156075084743931203659725884535
70514622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.6803680411101922173191545585784017914851385581234783006245630643053316775002
Short name T419
Test name
Test status
Simulation time 7628111361 ps
CPU time 142.32 seconds
Started Nov 22 02:04:55 PM PST 23
Finished Nov 22 02:07:18 PM PST 23
Peak memory 236348 kb
Host smart-fda3933e-cfec-45b5-84f9-9c574dee9422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6803680411101922173191545585784017914851385581234783006245630643053316775002 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.kmac_sideload.6803680411101922173191545585784017914851385581234783006245630643053316775002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.37753814642678727279368033767111254919401166474840328856714197512079251962363
Short name T713
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.91 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:29 PM PST 23
Peak memory 225156 kb
Host smart-d8ebb045-420b-4d63-b004-3fa7303f3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37753814642678727279368033767111254919401166474840328856714197512079251962363 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.kmac_smoke.37753814642678727279368033767111254919401166474840328856714197512079251962363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.54490774596763967619744998875064246846320791864579103134940989119277862521488
Short name T857
Test name
Test status
Simulation time 47207151869 ps
CPU time 871.97 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:19:33 PM PST 23
Peak memory 339744 kb
Host smart-7ee5f919-87be-4051-be91-f75453187bf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=54490774596763967619744998875064246846320791864579103134940989119277862521488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_st
ress_all.54490774596763967619744998875064246846320791864579103134940989119277862521488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.12894571419334480445814707463390158113257992983569096850347481180657982917122
Short name T646
Test name
Test status
Simulation time 322955517 ps
CPU time 6.04 seconds
Started Nov 22 02:04:50 PM PST 23
Finished Nov 22 02:04:57 PM PST 23
Peak memory 219140 kb
Host smart-59399e40-0de0-4633-85d7-f93d4816fc4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12894571419334480445814707463390158113257992983569096
850347481180657982917122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac.12894571419334480445814707463390158113
257992983569096850347481180657982917122 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.55260802229060395612501926861056906491007920089329379660802621486953422716710
Short name T320
Test name
Test status
Simulation time 309259198 ps
CPU time 5.74 seconds
Started Nov 22 02:04:57 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 219316 kb
Host smart-d965787c-e68b-4dec-969d-b75c182749f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55260802229060395612501926861056906491007920089329379
660802621486953422716710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.552608022290603956125019268610
56906491007920089329379660802621486953422716710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.96195860373686725872471745722091412099477037202677091757628469393746267418573
Short name T190
Test name
Test status
Simulation time 117329894454 ps
CPU time 2103.04 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 02:39:53 PM PST 23
Peak memory 400844 kb
Host smart-82cb087b-2502-4fcd-b8e7-3498ed97beb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=96195860373686725872471745722091412099477037202677091757628469393746267418573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.kmac_test_vectors_sha3_224.96195860373686725872471745722091412099477037202677091757628469393746267418573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.102595118692716901262844109416176887986606478330596771346533008626360292385950
Short name T273
Test name
Test status
Simulation time 106843317633 ps
CPU time 1899.37 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:36:39 PM PST 23
Peak memory 376460 kb
Host smart-650b45a9-4b34-473f-ad9e-bff648ebb390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=102595118692716901262844109416176887986606478330596771346533008626360292385950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.kmac_test_vectors_sha3_256.102595118692716901262844109416176887986606478330596771346533008626360292385950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.9103724255823003992073020352066722899251643391471411506769896338205974533159
Short name T537
Test name
Test status
Simulation time 83520343504 ps
CPU time 1527.73 seconds
Started Nov 22 02:04:56 PM PST 23
Finished Nov 22 02:30:24 PM PST 23
Peak memory 338480 kb
Host smart-8b546eb9-0e1d-4104-96e2-9dc379015b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=9103724255823003992073020352066722899251643391471411506769896338205974533159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
kmac_test_vectors_sha3_384.9103724255823003992073020352066722899251643391471411506769896338205974533159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.32617160456419469678115126306407218155257247042143764477230600716335101199660
Short name T749
Test name
Test status
Simulation time 57499426673 ps
CPU time 1164.21 seconds
Started Nov 22 02:04:51 PM PST 23
Finished Nov 22 02:24:16 PM PST 23
Peak memory 297804 kb
Host smart-e658617f-7773-40b0-97c0-c046b4fdbe23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32617160456419469678115126306407218155257247042143764477230600716335101199660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.kmac_test_vectors_sha3_512.32617160456419469678115126306407218155257247042143764477230600716335101199660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.46170816059618755156369286445620179675207508994124774286944815708946577015775
Short name T654
Test name
Test status
Simulation time 320694338954 ps
CPU time 5594.26 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 03:38:05 PM PST 23
Peak memory 674308 kb
Host smart-e58de306-e792-4e14-ba78-0b21378bc6f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=46170816059618755156369286445620179675207508994124774286944815708946577015775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.kmac_test_vectors_shake_128.46170816059618755156369286445620179675207508994124774286944815708946577015775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.74849641982846713580058902423900715372399162493618872644637545118688845539599
Short name T874
Test name
Test status
Simulation time 270085708112 ps
CPU time 4668.52 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 03:22:52 PM PST 23
Peak memory 577320 kb
Host smart-9b4308d4-7ed0-4634-ac57-ba0115f57d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=74849641982846713580058902423900715372399162493618872644637545118688845539599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.kmac_test_vectors_shake_256.74849641982846713580058902423900715372399162493618872644637545118688845539599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.46531243657391129422339790115061387093238301343449636337971656356761623607535
Short name T243
Test name
Test status
Simulation time 21118646 ps
CPU time 0.82 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 219008 kb
Host smart-b0d8470a-1815-4dce-abad-9591726d32be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46531243657391129422339790115061387093238301343449636337971656356761623607535 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.kmac_alert_test.46531243657391129422339790115061387093238301343449636337971656356761623607535 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.33413585273074272077882329918626973002428869549258143424296949208454616832032
Short name T743
Test name
Test status
Simulation time 6076748772 ps
CPU time 107.29 seconds
Started Nov 22 02:04:56 PM PST 23
Finished Nov 22 02:06:44 PM PST 23
Peak memory 236212 kb
Host smart-2067cea5-ba5f-4a11-886d-93d6d0341693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33413585273074272077882329918626973002428869549258143424296949208454616832032 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_app.33413585273074272077882329918626973002428869549258143424296949208454616832032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.112705724062116614530139478918275484807279226706784381777232426328821851285060
Short name T669
Test name
Test status
Simulation time 14830000174 ps
CPU time 396.18 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:11:38 PM PST 23
Peak memory 243260 kb
Host smart-a12c1cfc-df02-4d45-90f0-1197994558b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112705724062116614530139478918275484807279226706784381777232426328821851285060 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.kmac_burst_write.112705724062116614530139478918275484807279226706784381777232426328821851285060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.31779801026380639834404716726901684147261794620070312251403069064410048501714
Short name T221
Test name
Test status
Simulation time 7238810904 ps
CPU time 113.9 seconds
Started Nov 22 02:04:52 PM PST 23
Finished Nov 22 02:06:46 PM PST 23
Peak memory 243904 kb
Host smart-9123b78b-c566-4a34-93fa-240c0141e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31779801026380639834404716726901684147261794620070312251403069064410048501714 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.kmac_entropy_refresh.31779801026380639834404716726901684147261794620070312251403069064410048501714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.99911302597717693845549370280527126644554790133543176227957975622484060115079
Short name T962
Test name
Test status
Simulation time 8137821569 ps
CPU time 147.17 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:07:33 PM PST 23
Peak memory 252728 kb
Host smart-bfe4416f-656b-4db4-bfab-4f3b91e9079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99911302597717693845549370280527126644554790133543176227957975622484060115079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.kmac_error.99911302597717693845549370280527126644554790133543176227957975622484060115079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.44905023497963729769702179458628847284756693372809048635121075598904128924373
Short name T46
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.56 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:05:13 PM PST 23
Peak memory 219212 kb
Host smart-75cc75af-0cf1-41c1-962d-b80ae65cf0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44905023497963729769702179458628847284756693372809048635121075598904128924373 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.kmac_key_error.44905023497963729769702179458628847284756693372809048635121075598904128924373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.88948342630617655693720165958211440086207650864710318197216224852880470925449
Short name T929
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:04:55 PM PST 23
Finished Nov 22 02:04:58 PM PST 23
Peak memory 220388 kb
Host smart-4cec89de-7ef7-4ee4-88ea-0d95222c13f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88948342630617655693720165958211440086207650864710318197216224852880470925449 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.kmac_lc_escalation.88948342630617655693720165958211440086207650864710318197216224852880470925449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.35496220587602282504974982964885221151993724085649675498396439376492948352495
Short name T430
Test name
Test status
Simulation time 50513696845 ps
CPU time 996.02 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:21:42 PM PST 23
Peak memory 306340 kb
Host smart-5cb2b3bf-7195-43f8-8fbd-877a68271a5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496220587602282504974982964885221151993724085649675498396439376492948352495 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.354962205876022825049749829648852211519937240856496754983964393764929
48352495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.41045084149108129209496861005236732223561148420207594105380549666027826506260
Short name T423
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.56 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:07:24 PM PST 23
Peak memory 236396 kb
Host smart-834cb214-d288-48d5-8e0e-1cede6b27094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41045084149108129209496861005236732223561148420207594105380549666027826506260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.kmac_sideload.41045084149108129209496861005236732223561148420207594105380549666027826506260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.74952945538023037159605168572465309191291047058875927185032193151450496761582
Short name T695
Test name
Test status
Simulation time 1925406983 ps
CPU time 28.27 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:32 PM PST 23
Peak memory 225324 kb
Host smart-151752e4-53f3-410b-ad9f-338e190fc846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74952945538023037159605168572465309191291047058875927185032193151450496761582 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.kmac_smoke.74952945538023037159605168572465309191291047058875927185032193151450496761582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.27258291421402082288438664636790638091969297629508554338229969857560091375008
Short name T1065
Test name
Test status
Simulation time 47207151869 ps
CPU time 935.89 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:20:41 PM PST 23
Peak memory 339824 kb
Host smart-eb5ee082-e499-4f79-93a5-902c3516c150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=27258291421402082288438664636790638091969297629508554338229969857560091375008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_st
ress_all.27258291421402082288438664636790638091969297629508554338229969857560091375008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.48853750463751744738807069289801401001915296081428618515878426726223954795029
Short name T744
Test name
Test status
Simulation time 322955517 ps
CPU time 5.89 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:07 PM PST 23
Peak memory 219308 kb
Host smart-aeb08185-8fbb-4f3a-bec0-7e3bba29bd29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48853750463751744738807069289801401001915296081428618
515878426726223954795029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac.48853750463751744738807069289801401001
915296081428618515878426726223954795029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.58470505486605444385396121179005927308247126201418847262522585517468789934689
Short name T192
Test name
Test status
Simulation time 309259198 ps
CPU time 5.53 seconds
Started Nov 22 02:04:54 PM PST 23
Finished Nov 22 02:05:01 PM PST 23
Peak memory 219236 kb
Host smart-665477d0-12a9-4b3f-8bef-e3ca6404015f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58470505486605444385396121179005927308247126201418847
262522585517468789934689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.584705054866054443853961211790
05927308247126201418847262522585517468789934689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.47654893234082104748642460187265565531423892443254885261743664127811943748436
Short name T819
Test name
Test status
Simulation time 117329894454 ps
CPU time 2050.81 seconds
Started Nov 22 02:04:56 PM PST 23
Finished Nov 22 02:39:08 PM PST 23
Peak memory 400876 kb
Host smart-d33fec89-9a23-4efd-a061-ce73880a1309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47654893234082104748642460187265565531423892443254885261743664127811943748436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_224.47654893234082104748642460187265565531423892443254885261743664127811943748436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.25385496322552225186572647652194079519909231459328371105829931037233568820554
Short name T187
Test name
Test status
Simulation time 106843317633 ps
CPU time 1881.8 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:36:24 PM PST 23
Peak memory 376392 kb
Host smart-c67694c3-fa7c-4d22-831f-fcca9e0a21f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25385496322552225186572647652194079519909231459328371105829931037233568820554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_256.25385496322552225186572647652194079519909231459328371105829931037233568820554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.61722598548685088120225723089893293471734074966861420885344825799420181631746
Short name T461
Test name
Test status
Simulation time 83520343504 ps
CPU time 1627.35 seconds
Started Nov 22 02:04:49 PM PST 23
Finished Nov 22 02:31:57 PM PST 23
Peak memory 338348 kb
Host smart-e6b67d34-a430-4bfc-8ddb-e9b71aa0ca9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61722598548685088120225723089893293471734074966861420885344825799420181631746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_384.61722598548685088120225723089893293471734074966861420885344825799420181631746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.111140980113315131639948282822888313376143197206584058806357591447629805131905
Short name T285
Test name
Test status
Simulation time 57499426673 ps
CPU time 1181.49 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:24:42 PM PST 23
Peak memory 297820 kb
Host smart-a21b3c50-b3c0-410a-b8fe-e715eb3e149c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=111140980113315131639948282822888313376143197206584058806357591447629805131905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.kmac_test_vectors_sha3_512.111140980113315131639948282822888313376143197206584058806357591447629805131905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.84730203888421079273865201197038828377852574720120317008676922323448194050458
Short name T949
Test name
Test status
Simulation time 320694338954 ps
CPU time 5392.28 seconds
Started Nov 22 02:04:50 PM PST 23
Finished Nov 22 03:34:44 PM PST 23
Peak memory 674288 kb
Host smart-1f833d6b-45ac-453c-b81c-55deff0b0b8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=84730203888421079273865201197038828377852574720120317008676922323448194050458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_test_vectors_shake_128.84730203888421079273865201197038828377852574720120317008676922323448194050458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.86808360132515960619044817606977928434982413879769133909439111054893682989186
Short name T1046
Test name
Test status
Simulation time 270085708112 ps
CPU time 4675.46 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 03:22:58 PM PST 23
Peak memory 577320 kb
Host smart-93545ed2-269a-4b75-ac0e-efe77533f53b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=86808360132515960619044817606977928434982413879769133909439111054893682989186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_test_vectors_shake_256.86808360132515960619044817606977928434982413879769133909439111054893682989186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.102402983156870814937726609107081730092760241986648189495332112214327312712351
Short name T442
Test name
Test status
Simulation time 21118646 ps
CPU time 0.83 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:01:23 PM PST 23
Peak memory 218968 kb
Host smart-32ebec53-7a35-4ff8-821d-7955f91db9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102402983156870814937726609107081730092760241986648189495332112214327312712351 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.102402983156870814937726609107081730092760241986648189495332112214327312712351 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.39767306830302923389246936535749359752164256577808153845197411223666626994928
Short name T194
Test name
Test status
Simulation time 6076748772 ps
CPU time 102.23 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:02:29 PM PST 23
Peak memory 236172 kb
Host smart-74d67e11-3d51-4268-a614-7db85b7a92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39767306830302923389246936535749359752164256577808153845197411223666626994928 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.kmac_app.39767306830302923389246936535749359752164256577808153845197411223666626994928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3778849660694206131677703334742413224937727041331737918860995444470641042363
Short name T652
Test name
Test status
Simulation time 7277596308 ps
CPU time 112.46 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:02:40 PM PST 23
Peak memory 243888 kb
Host smart-a59ac528-5d58-4f48-b73d-ef4d9d065440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778849660694206131677703334742413224937727041331737918860995444470641042363 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_app_with_partial_data.3778849660694206131677703334742413224937727041331737918860995444470641042363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.19395621331118078457557125498378064205628179174110610268481359636120294628110
Short name T218
Test name
Test status
Simulation time 14830000174 ps
CPU time 401.7 seconds
Started Nov 22 02:01:02 PM PST 23
Finished Nov 22 02:07:44 PM PST 23
Peak memory 243264 kb
Host smart-bff32a63-7574-4e3b-8515-5b7466742f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19395621331118078457557125498378064205628179174110610268481359636120294628110 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.kmac_burst_write.19395621331118078457557125498378064205628179174110610268481359636120294628110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.52993499502153252758419661666814154040190126447501887756391448286115447810566
Short name T581
Test name
Test status
Simulation time 62261174 ps
CPU time 1.23 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:00:48 PM PST 23
Peak memory 219072 kb
Host smart-d7025f7d-fecc-458b-aff3-899aa32a13e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52993499502153252758419661666814154040190126447501887756391448286115447810566 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.kmac_edn_timeout_error.52993499502153252758419661666814154040190126447501887756391448286115447810566 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.30714198597768130862542735541528925850657642370490278703248179385753475951959
Short name T65
Test name
Test status
Simulation time 64850439 ps
CPU time 1.27 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 02:01:21 PM PST 23
Peak memory 218984 kb
Host smart-c27b5d99-7f60-48c9-b753-bf8bcafd0f09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30714198597768130862542735541528925850657642370490278703248179385753475951959 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.30714198597768130862542735541528925850657642370490278703248179385753475951959 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.47141966519207673896726917159904397225793525291255993663974197744448497818875
Short name T374
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.4 seconds
Started Nov 22 02:01:13 PM PST 23
Finished Nov 22 02:01:36 PM PST 23
Peak memory 219360 kb
Host smart-901ddc83-31ab-4499-a868-249e7e008ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47141966519207673896726917159904397225793525291255993663974197744448497818875 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.kmac_entropy_ready_error.47141966519207673896726917159904397225793525291255993663974197744448497818875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.100642567862881930860434457627180015916730697049432951503688300840560660442761
Short name T866
Test name
Test status
Simulation time 7238810904 ps
CPU time 105.09 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:02:46 PM PST 23
Peak memory 243892 kb
Host smart-8c7658eb-a888-4c3f-8bda-5f7799665e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100642567862881930860434457627180015916730697049432951503688300840560660442761 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.kmac_entropy_refresh.100642567862881930860434457627180015916730697049432951503688300840560660442761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.21897241447193735559241868413284242491638868899244772586096941075422487529296
Short name T346
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.14 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:03:46 PM PST 23
Peak memory 252764 kb
Host smart-f71cebdd-f575-4a5b-ac66-26b20e605c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21897241447193735559241868413284242491638868899244772586096941075422487529296 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.kmac_error.21897241447193735559241868413284242491638868899244772586096941075422487529296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.45151553034028933609070624254556985357821741935835335726468012519737141937832
Short name T559
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.69 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 219228 kb
Host smart-28ce71c8-a825-4ba1-b686-006924905084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45151553034028933609070624254556985357821741935835335726468012519737141937832 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.kmac_key_error.45151553034028933609070624254556985357821741935835335726468012519737141937832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.79126392651021989736053162454868979608489442065964930594659830967009478367099
Short name T25
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 02:01:21 PM PST 23
Peak memory 220400 kb
Host smart-7e7e8d34-d5dc-43ea-b492-19dfdcd9229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79126392651021989736053162454868979608489442065964930594659830967009478367099 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.kmac_lc_escalation.79126392651021989736053162454868979608489442065964930594659830967009478367099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.107697115198461010858944111185393703232890909526974215732593146056189725594339
Short name T414
Test name
Test status
Simulation time 50513696845 ps
CPU time 1049.58 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:18:31 PM PST 23
Peak memory 306400 kb
Host smart-7b52d1df-f329-4819-a865-2a6f6b70dc1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107697115198461010858944111185393703232890909526974215732593146056189725594339 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.107697115198461010858944111185393703232890909526974215732593146056189
725594339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.21732952781994406526472336599766323573239985037137425942553842181236123941849
Short name T647
Test name
Test status
Simulation time 7712378544 ps
CPU time 132.75 seconds
Started Nov 22 02:01:04 PM PST 23
Finished Nov 22 02:03:17 PM PST 23
Peak memory 244032 kb
Host smart-cb870259-a8e2-4a17-b53e-3154a24d7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21732952781994406526472336599766323573239985037137425942553842181236123941849 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.kmac_mubi.21732952781994406526472336599766323573239985037137425942553842181236123941849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.69291761089595444465465744680353728806169893741338857239715064305825228355561
Short name T28
Test name
Test status
Simulation time 6415496062 ps
CPU time 53.66 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 277404 kb
Host smart-fa1a354f-0373-4392-832b-0fec63f263f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69291761089595444465465744680353728806169893741338857239715064305825228355561 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.kmac_sec_cm.69291761089595444465465744680353728806169893741338857239715064305825228355561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.6657127320597036887413059537451316518248370763568022548911648788646398450652
Short name T1039
Test name
Test status
Simulation time 7628111361 ps
CPU time 134.84 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:03:01 PM PST 23
Peak memory 236356 kb
Host smart-f131eb20-a5de-46a5-aa09-f3e03948dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6657127320597036887413059537451316518248370763568022548911648788646398450652 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.kmac_sideload.6657127320597036887413059537451316518248370763568022548911648788646398450652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.79476689810556271613004321860953770621951148567212264449676149176481444961849
Short name T792
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.11 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:01:26 PM PST 23
Peak memory 225264 kb
Host smart-6c914865-57f0-426e-8f60-8e81dcbe1cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79476689810556271613004321860953770621951148567212264449676149176481444961849 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.kmac_smoke.79476689810556271613004321860953770621951148567212264449676149176481444961849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.45774872570518136417781016999191214452704450169636086419320737909564203106599
Short name T825
Test name
Test status
Simulation time 47207151869 ps
CPU time 872.8 seconds
Started Nov 22 02:01:12 PM PST 23
Finished Nov 22 02:15:47 PM PST 23
Peak memory 339812 kb
Host smart-03079933-be7a-4330-a0af-be0a3df0d8e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=45774872570518136417781016999191214452704450169636086419320737909564203106599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_str
ess_all.45774872570518136417781016999191214452704450169636086419320737909564203106599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.63807499807394143940173979251187656720148858680489573698114381740642636399929
Short name T834
Test name
Test status
Simulation time 322955517 ps
CPU time 5.79 seconds
Started Nov 22 02:00:43 PM PST 23
Finished Nov 22 02:00:50 PM PST 23
Peak memory 219276 kb
Host smart-42c6d973-a0f7-4276-a934-8250d71ae62d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63807499807394143940173979251187656720148858680489573
698114381740642636399929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.638074998073941439401739792511876567201
48858680489573698114381740642636399929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.74472221878987467257961944756678826409400858794015858183727452984755015244726
Short name T861
Test name
Test status
Simulation time 309259198 ps
CPU time 6 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:01:08 PM PST 23
Peak memory 219152 kb
Host smart-f3ec214e-227d-4d04-998f-9fe5466575ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74472221878987467257961944756678826409400858794015858
183727452984755015244726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.7447222187898746725796194475667
8826409400858794015858183727452984755015244726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.115398947750427802395961406190927288667444852083710292120489828455068066208685
Short name T623
Test name
Test status
Simulation time 117329894454 ps
CPU time 2102.69 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:35:49 PM PST 23
Peak memory 400868 kb
Host smart-a8e5d66b-dc79-4d8e-8f62-d7e03ddd929b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=115398947750427802395961406190927288667444852083710292120489828455068066208685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.kmac_test_vectors_sha3_224.115398947750427802395961406190927288667444852083710292120489828455068066208685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.4107559532005947107205718684576797498660376889452396568157787431729537953698
Short name T803
Test name
Test status
Simulation time 106843317633 ps
CPU time 1961.31 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:33:29 PM PST 23
Peak memory 376396 kb
Host smart-d1ce7be9-a56d-4236-9a5f-5782165f6e66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4107559532005947107205718684576797498660376889452396568157787431729537953698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.k
mac_test_vectors_sha3_256.4107559532005947107205718684576797498660376889452396568157787431729537953698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.15765634913484071692981451133906948849906746663480407375418286821217864883320
Short name T472
Test name
Test status
Simulation time 83520343504 ps
CPU time 1568.11 seconds
Started Nov 22 02:01:05 PM PST 23
Finished Nov 22 02:27:13 PM PST 23
Peak memory 338488 kb
Host smart-a7ccd926-3999-44e8-aaae-d19d2388a49f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=15765634913484071692981451133906948849906746663480407375418286821217864883320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_384.15765634913484071692981451133906948849906746663480407375418286821217864883320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.62632786192255849961403451919608136975810346754829026064351627684814878139363
Short name T369
Test name
Test status
Simulation time 57499426673 ps
CPU time 1185.03 seconds
Started Nov 22 02:00:48 PM PST 23
Finished Nov 22 02:20:34 PM PST 23
Peak memory 297812 kb
Host smart-c4c02af1-36db-46b9-8561-62fcc14e1983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=62632786192255849961403451919608136975810346754829026064351627684814878139363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_512.62632786192255849961403451919608136975810346754829026064351627684814878139363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.13074301334312500150965304038060614744565115506153171287382266198079406003972
Short name T521
Test name
Test status
Simulation time 320694338954 ps
CPU time 5556.59 seconds
Started Nov 22 02:00:50 PM PST 23
Finished Nov 22 03:33:28 PM PST 23
Peak memory 674280 kb
Host smart-22899c6d-004c-4378-beff-53393b6d2c38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=13074301334312500150965304038060614744565115506153171287382266198079406003972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.kmac_test_vectors_shake_128.13074301334312500150965304038060614744565115506153171287382266198079406003972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.115431762152788143456985905708405803689206249807148578775169223341643647170479
Short name T140
Test name
Test status
Simulation time 270085708112 ps
CPU time 4840.05 seconds
Started Nov 22 02:00:42 PM PST 23
Finished Nov 22 03:21:23 PM PST 23
Peak memory 577352 kb
Host smart-e79028e4-bb09-4075-99cb-2084f7feb47f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=115431762152788143456985905708405803689206249807148578775169223341643647170479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.kmac_test_vectors_shake_256.115431762152788143456985905708405803689206249807148578775169223341643647170479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.107734903718512848841895968076215403672044557082294656739032677019635418056846
Short name T271
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219024 kb
Host smart-3b426de0-74c3-4dd8-803c-6af0b9434f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107734903718512848841895968076215403672044557082294656739032677019635418056846 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.107734903718512848841895968076215403672044557082294656739032677019635418056846 +enable_masking=1
+sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.101591545486900041422018075394101144659600465571974026364739198217596698489814
Short name T204
Test name
Test status
Simulation time 6076748772 ps
CPU time 96.69 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:06:44 PM PST 23
Peak memory 236156 kb
Host smart-c2452e8f-6680-4a91-b972-74a90fdedcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101591545486900041422018075394101144659600465571974026364739198217596698489814 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.kmac_app.101591545486900041422018075394101144659600465571974026364739198217596698489814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.89315905303267878423031836279161937490641933568058470136102050313195226234433
Short name T556
Test name
Test status
Simulation time 14830000174 ps
CPU time 387.4 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:11:34 PM PST 23
Peak memory 243188 kb
Host smart-030eb545-066b-4ee7-866c-1315f10d75de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89315905303267878423031836279161937490641933568058470136102050313195226234433 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.kmac_burst_write.89315905303267878423031836279161937490641933568058470136102050313195226234433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.78556966879377479169433880132813252971826731965938274347812567015145745863295
Short name T409
Test name
Test status
Simulation time 7238810904 ps
CPU time 116.17 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:06:59 PM PST 23
Peak memory 243856 kb
Host smart-722ee8ed-e0d3-4710-a4e2-1c4b79496e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78556966879377479169433880132813252971826731965938274347812567015145745863295 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.kmac_entropy_refresh.78556966879377479169433880132813252971826731965938274347812567015145745863295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.33577015979346329661520559460310751148110712530763239809503778418481105739556
Short name T1035
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.9 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:07:34 PM PST 23
Peak memory 252724 kb
Host smart-f9fe74ef-0ee6-4544-945e-a7b760b93899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33577015979346329661520559460310751148110712530763239809503778418481105739556 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.kmac_error.33577015979346329661520559460310751148110712530763239809503778418481105739556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.23209944421418001987452361037217727680669147040534768923094817059340760493296
Short name T337
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.94 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:05:15 PM PST 23
Peak memory 219152 kb
Host smart-5e6b8dd1-c32b-4d27-a6f6-27cec85bd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23209944421418001987452361037217727680669147040534768923094817059340760493296 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.kmac_key_error.23209944421418001987452361037217727680669147040534768923094817059340760493296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.85717297587583236499366109820865928405310882377809392429284491457960291947472
Short name T26
Test name
Test status
Simulation time 72761090 ps
CPU time 1.56 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:05 PM PST 23
Peak memory 220480 kb
Host smart-769ba6b9-4441-4f0b-8655-0e964eae3325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85717297587583236499366109820865928405310882377809392429284491457960291947472 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.kmac_lc_escalation.85717297587583236499366109820865928405310882377809392429284491457960291947472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.88536313430938041534834520363535156647200346312854404779395113783028661142726
Short name T509
Test name
Test status
Simulation time 50513696845 ps
CPU time 946.26 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:20:50 PM PST 23
Peak memory 306328 kb
Host smart-f47a56b2-30c5-459d-9352-943348fc2d7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88536313430938041534834520363535156647200346312854404779395113783028661142726 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.885363134309380415348345203635351566472003463128544047793951137830286
61142726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.100008954898641561615061808397790721222792118672667326051393879091350311768878
Short name T800
Test name
Test status
Simulation time 7628111361 ps
CPU time 139.39 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:07:26 PM PST 23
Peak memory 236344 kb
Host smart-cca9b405-236b-46a0-8c5a-21ff99f7548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100008954898641561615061808397790721222792118672667326051393879091350311768878 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.kmac_sideload.100008954898641561615061808397790721222792118672667326051393879091350311768878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.101297661744211934711670056284026687463799769097043770139104658342947477408541
Short name T707
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.46 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:29 PM PST 23
Peak memory 225344 kb
Host smart-5fea0cc3-21fe-4871-b0f8-48a74b451293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101297661744211934711670056284026687463799769097043770139104658342947477408541 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.kmac_smoke.101297661744211934711670056284026687463799769097043770139104658342947477408541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.52480265177355053706951016433489105324234507181399362440428765878092661435470
Short name T568
Test name
Test status
Simulation time 47207151869 ps
CPU time 891.75 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 339732 kb
Host smart-317510fd-bf53-44d9-943c-b40b1ddec3c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=52480265177355053706951016433489105324234507181399362440428765878092661435470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_st
ress_all.52480265177355053706951016433489105324234507181399362440428765878092661435470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.108098496406007532331968767300582279218607167433270561485325070195387181217135
Short name T484
Test name
Test status
Simulation time 322955517 ps
CPU time 6.07 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:11 PM PST 23
Peak memory 219156 kb
Host smart-3d232941-facb-4afb-bde3-ec75ba0f9dff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10809849640600753233196876730058227921860716743327056
1485325070195387181217135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac.1080984964060075323319687673005822792
18607167433270561485325070195387181217135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.87752523351838584676424337788131610688774591969886176983101347987617064803514
Short name T884
Test name
Test status
Simulation time 309259198 ps
CPU time 5.72 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:09 PM PST 23
Peak memory 219280 kb
Host smart-565c5994-9a53-4df3-890e-8760aedaae4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87752523351838584676424337788131610688774591969886176
983101347987617064803514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.877525233518385846764243377881
31610688774591969886176983101347987617064803514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.621302221336462735602196889742029738832405277538626375993641362249708872590
Short name T146
Test name
Test status
Simulation time 117329894454 ps
CPU time 2063.98 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:39:33 PM PST 23
Peak memory 400832 kb
Host smart-1fcdaba0-e5ef-4ca2-94de-0980e4a13062
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=621302221336462735602196889742029738832405277538626375993641362249708872590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.k
mac_test_vectors_sha3_224.621302221336462735602196889742029738832405277538626375993641362249708872590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.30717127388412597770532453333952578985048831470229877059422233592059911765093
Short name T832
Test name
Test status
Simulation time 106843317633 ps
CPU time 1834.94 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:35:45 PM PST 23
Peak memory 376428 kb
Host smart-79317cec-98d1-486a-a0cf-80c7b02c60ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30717127388412597770532453333952578985048831470229877059422233592059911765093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_256.30717127388412597770532453333952578985048831470229877059422233592059911765093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.25642982647079391450067167730766815395531965968378622461406169130475910184043
Short name T173
Test name
Test status
Simulation time 83520343504 ps
CPU time 1543.14 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:30:53 PM PST 23
Peak memory 338440 kb
Host smart-cdd58f15-7753-4bc1-be2e-d96282ae0be8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25642982647079391450067167730766815395531965968378622461406169130475910184043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_384.25642982647079391450067167730766815395531965968378622461406169130475910184043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.90111042315147284294235401282165919129067191361557955404684667273166848803350
Short name T1071
Test name
Test status
Simulation time 57499426673 ps
CPU time 1220.57 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:25:24 PM PST 23
Peak memory 297756 kb
Host smart-84ce528a-1de8-4785-b832-390cba010648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90111042315147284294235401282165919129067191361557955404684667273166848803350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_512.90111042315147284294235401282165919129067191361557955404684667273166848803350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.34023228383273018806312716509198270380811390418735575899846840371222699916466
Short name T791
Test name
Test status
Simulation time 320694338954 ps
CPU time 5192.48 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 03:31:41 PM PST 23
Peak memory 674304 kb
Host smart-c5337857-52f9-47c4-946d-8641ff8e13b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=34023228383273018806312716509198270380811390418735575899846840371222699916466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.kmac_test_vectors_shake_128.34023228383273018806312716509198270380811390418735575899846840371222699916466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.89407013872471047097357536439804872934003224325576708173894895319308863464081
Short name T913
Test name
Test status
Simulation time 270085708112 ps
CPU time 4694.19 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 03:23:20 PM PST 23
Peak memory 577412 kb
Host smart-cc97e487-a3dc-4163-83aa-789b27510524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=89407013872471047097357536439804872934003224325576708173894895319308863464081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.kmac_test_vectors_shake_256.89407013872471047097357536439804872934003224325576708173894895319308863464081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.56698971446033380310714041666831378826947737093501600920131230052429135598808
Short name T135
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:02 PM PST 23
Peak memory 218996 kb
Host smart-ae21b7ef-b863-4792-8dd7-0b291df117cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56698971446033380310714041666831378826947737093501600920131230052429135598808 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.kmac_alert_test.56698971446033380310714041666831378826947737093501600920131230052429135598808 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.94480768742042847915904726860751366319209115825873811147371457825727290401886
Short name T860
Test name
Test status
Simulation time 6076748772 ps
CPU time 97.01 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:06:36 PM PST 23
Peak memory 236128 kb
Host smart-26bb8515-2344-4b2f-af9d-27ea2798f6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94480768742042847915904726860751366319209115825873811147371457825727290401886 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_app.94480768742042847915904726860751366319209115825873811147371457825727290401886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.91366231078439370787301646359119933816516632652971924034746307337198194654290
Short name T570
Test name
Test status
Simulation time 14830000174 ps
CPU time 393.92 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:11:42 PM PST 23
Peak memory 243260 kb
Host smart-b8c46e93-1b23-43cd-a831-a39e7fbe1e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91366231078439370787301646359119933816516632652971924034746307337198194654290 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.kmac_burst_write.91366231078439370787301646359119933816516632652971924034746307337198194654290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.105465599728879874949851809441081316577188536075889364514925381341840856701788
Short name T624
Test name
Test status
Simulation time 7238810904 ps
CPU time 106.75 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:06:51 PM PST 23
Peak memory 243936 kb
Host smart-0921f89c-63f4-4cc0-8c7e-1993049e4c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105465599728879874949851809441081316577188536075889364514925381341840856701788 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_entropy_refresh.105465599728879874949851809441081316577188536075889364514925381341840856701788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.81881467358624916391418478688671196720854075683672011685686867207179984743567
Short name T533
Test name
Test status
Simulation time 8137821569 ps
CPU time 157.67 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:07:40 PM PST 23
Peak memory 252708 kb
Host smart-d00308ad-a552-4248-8ca3-8273d98d4142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81881467358624916391418478688671196720854075683672011685686867207179984743567 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.kmac_error.81881467358624916391418478688671196720854075683672011685686867207179984743567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.86761525471136117790413307269777789054873141676882133201598363803780907159733
Short name T512
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.72 seconds
Started Nov 22 02:04:57 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 219144 kb
Host smart-5d85bb09-0600-4a62-8622-e9617a1d4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86761525471136117790413307269777789054873141676882133201598363803780907159733 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.kmac_key_error.86761525471136117790413307269777789054873141676882133201598363803780907159733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.5441802822796639507931985469355528312807384067035323609149472902708884146606
Short name T839
Test name
Test status
Simulation time 72761090 ps
CPU time 1.51 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:04 PM PST 23
Peak memory 220480 kb
Host smart-7a3e675a-d4d8-4fbc-a6a8-5cae3b4fcc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5441802822796639507931985469355528312807384067035323609149472902708884146606 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.kmac_lc_escalation.5441802822796639507931985469355528312807384067035323609149472902708884146606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.66916569031285438716556966820073107332870750207495748374111448434821462205665
Short name T797
Test name
Test status
Simulation time 50513696845 ps
CPU time 1019.74 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 306340 kb
Host smart-8fb03f61-d4e8-47ea-834e-a1dbe1513341
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66916569031285438716556966820073107332870750207495748374111448434821462205665 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.669165690312854387165569668200731073328707502074957483741114484348214
62205665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.40801378273187347687398819365790641603478697232555500642199242000672254874837
Short name T412
Test name
Test status
Simulation time 7628111361 ps
CPU time 144.4 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:07:31 PM PST 23
Peak memory 236360 kb
Host smart-2a4dbe51-6c20-4539-9d28-efcf06eba851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40801378273187347687398819365790641603478697232555500642199242000672254874837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.kmac_sideload.40801378273187347687398819365790641603478697232555500642199242000672254874837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.38669109179613689806325735479931840274946962994439625057648399513589772869995
Short name T887
Test name
Test status
Simulation time 1925406983 ps
CPU time 28.06 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:05:37 PM PST 23
Peak memory 225404 kb
Host smart-14d714ac-d816-41f0-8407-767bb95facf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38669109179613689806325735479931840274946962994439625057648399513589772869995 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.kmac_smoke.38669109179613689806325735479931840274946962994439625057648399513589772869995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.98633869287520799065428458534113791448438285189867444746676871557726299568483
Short name T475
Test name
Test status
Simulation time 47207151869 ps
CPU time 902.71 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:20:02 PM PST 23
Peak memory 339876 kb
Host smart-711fcddc-005e-4f2f-8e7f-af2e506c5fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=98633869287520799065428458534113791448438285189867444746676871557726299568483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_st
ress_all.98633869287520799065428458534113791448438285189867444746676871557726299568483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.21685157913509433415541024045772060957425054741056806283332734888102776866678
Short name T516
Test name
Test status
Simulation time 322955517 ps
CPU time 5.74 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 219272 kb
Host smart-b322a717-032a-447a-a2f7-27a69eb829e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21685157913509433415541024045772060957425054741056806
283332734888102776866678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac.21685157913509433415541024045772060957
425054741056806283332734888102776866678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.18044594477335440462516326964537051284807215201588608120869901457058391475675
Short name T90
Test name
Test status
Simulation time 309259198 ps
CPU time 5.89 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219204 kb
Host smart-02365535-bd3e-4d5c-9d04-f3ab23be6d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18044594477335440462516326964537051284807215201588608
120869901457058391475675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.180445944773354404625163269645
37051284807215201588608120869901457058391475675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.70911990659284540962394389706917681679594658756801331006276630920178985972767
Short name T325
Test name
Test status
Simulation time 117329894454 ps
CPU time 2189.23 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:41:36 PM PST 23
Peak memory 400872 kb
Host smart-d2d02b86-0367-4615-aa0c-a0e8102bdd3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=70911990659284540962394389706917681679594658756801331006276630920178985972767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_224.70911990659284540962394389706917681679594658756801331006276630920178985972767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.7840093727016997340226740398248544103623083403659327585983307781331457788689
Short name T955
Test name
Test status
Simulation time 106843317633 ps
CPU time 1959.53 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:37:48 PM PST 23
Peak memory 376476 kb
Host smart-02776155-ce89-4a7d-b061-8c7e8b2d13b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=7840093727016997340226740398248544103623083403659327585983307781331457788689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
kmac_test_vectors_sha3_256.7840093727016997340226740398248544103623083403659327585983307781331457788689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.12249286059921247271885618160783644784095962309882132703078177081682007143699
Short name T946
Test name
Test status
Simulation time 83520343504 ps
CPU time 1629.52 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:32:13 PM PST 23
Peak memory 338416 kb
Host smart-66158a92-f121-4da4-8d24-ce0be977ee4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=12249286059921247271885618160783644784095962309882132703078177081682007143699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_384.12249286059921247271885618160783644784095962309882132703078177081682007143699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.45009405875943499198286878591702999908799006476428246977694888109849731640641
Short name T907
Test name
Test status
Simulation time 57499426673 ps
CPU time 1161.88 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:24:26 PM PST 23
Peak memory 297748 kb
Host smart-beb64342-14c6-4600-8a4d-b315bf10091d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45009405875943499198286878591702999908799006476428246977694888109849731640641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_512.45009405875943499198286878591702999908799006476428246977694888109849731640641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.97317935044284423022743739119676290524554194032766209813723733593633532777562
Short name T84
Test name
Test status
Simulation time 320694338954 ps
CPU time 5513.44 seconds
Started Nov 22 02:05:16 PM PST 23
Finished Nov 22 03:37:10 PM PST 23
Peak memory 674260 kb
Host smart-cc81767c-f706-4ca3-9fa7-e56bd9325a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97317935044284423022743739119676290524554194032766209813723733593633532777562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_test_vectors_shake_128.97317935044284423022743739119676290524554194032766209813723733593633532777562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.17646951452326704997666408277514689298891790110138154449347211497353605504719
Short name T152
Test name
Test status
Simulation time 270085708112 ps
CPU time 4546.77 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 03:20:53 PM PST 23
Peak memory 577372 kb
Host smart-7007662d-e357-4e48-aef5-3c21f5ee62c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=17646951452326704997666408277514689298891790110138154449347211497353605504719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_test_vectors_shake_256.17646951452326704997666408277514689298891790110138154449347211497353605504719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.59964776208907826581475707113512512951485583919930329521380581618951319484079
Short name T558
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:05:07 PM PST 23
Peak memory 218980 kb
Host smart-99da7439-6bfd-4d4d-b0d4-d880ca7a6ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59964776208907826581475707113512512951485583919930329521380581618951319484079 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.kmac_alert_test.59964776208907826581475707113512512951485583919930329521380581618951319484079 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.80535134003952254332794082269389827169238450737366194969441021184864318985038
Short name T213
Test name
Test status
Simulation time 6076748772 ps
CPU time 102.13 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:06:52 PM PST 23
Peak memory 236188 kb
Host smart-16f061fb-485f-4d84-947c-f085dce88d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80535134003952254332794082269389827169238450737366194969441021184864318985038 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.kmac_app.80535134003952254332794082269389827169238450737366194969441021184864318985038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.83297550748326900763269066502492660173038639236401284692923563386471590383694
Short name T742
Test name
Test status
Simulation time 14830000174 ps
CPU time 389.63 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:11:29 PM PST 23
Peak memory 243240 kb
Host smart-8c8b8dc2-4a86-4474-aa8c-2e0c72485532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83297550748326900763269066502492660173038639236401284692923563386471590383694 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.kmac_burst_write.83297550748326900763269066502492660173038639236401284692923563386471590383694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.110964773124216703993551842529639411290668749399436277301274674894281294872998
Short name T248
Test name
Test status
Simulation time 7238810904 ps
CPU time 110.46 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:06:59 PM PST 23
Peak memory 243928 kb
Host smart-5abde6dc-8603-4d17-aa48-86a9e166b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110964773124216703993551842529639411290668749399436277301274674894281294872998 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_entropy_refresh.110964773124216703993551842529639411290668749399436277301274674894281294872998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.84299543748663171887137686967030068419305082287518941285003863951322730924453
Short name T828
Test name
Test status
Simulation time 8137821569 ps
CPU time 141.89 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:07:24 PM PST 23
Peak memory 252728 kb
Host smart-1cb67296-7e63-4ad5-a629-d453daf7c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84299543748663171887137686967030068419305082287518941285003863951322730924453 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.kmac_error.84299543748663171887137686967030068419305082287518941285003863951322730924453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.51839902890509638494558240010045203951736659948789401814999650610841147942420
Short name T527
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.71 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:05:16 PM PST 23
Peak memory 219200 kb
Host smart-0820ca60-2103-4579-81ac-91fe98a6fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51839902890509638494558240010045203951736659948789401814999650610841147942420 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.kmac_key_error.51839902890509638494558240010045203951736659948789401814999650610841147942420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.25564615191083349610141276279026249871057180590587269622968824028697800503702
Short name T668
Test name
Test status
Simulation time 72761090 ps
CPU time 1.52 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 220480 kb
Host smart-41bc98b8-af1e-4818-8780-c832b968fa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25564615191083349610141276279026249871057180590587269622968824028697800503702 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.kmac_lc_escalation.25564615191083349610141276279026249871057180590587269622968824028697800503702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.72687349584474880775728551483963035746554122449784272210565427028246197112125
Short name T201
Test name
Test status
Simulation time 50513696845 ps
CPU time 927.97 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:20:31 PM PST 23
Peak memory 306244 kb
Host smart-96428c5d-716a-4799-9068-8810fc97d502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72687349584474880775728551483963035746554122449784272210565427028246197112125 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.726873495844748807757285514839630357465541224497842722105654270282461
97112125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.81059548413112002518435182355518048951739396911499072851168608796586145298397
Short name T427
Test name
Test status
Simulation time 7628111361 ps
CPU time 140.21 seconds
Started Nov 22 02:04:57 PM PST 23
Finished Nov 22 02:07:18 PM PST 23
Peak memory 236388 kb
Host smart-87e394fe-b5ef-4e1f-9414-0c7ffc2827a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81059548413112002518435182355518048951739396911499072851168608796586145298397 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.kmac_sideload.81059548413112002518435182355518048951739396911499072851168608796586145298397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.70603591031159146482880002064580124618934032560577665373548825513647762608541
Short name T1026
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.7 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:05:27 PM PST 23
Peak memory 225368 kb
Host smart-216fe2c0-e60f-4115-8619-e03446431cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70603591031159146482880002064580124618934032560577665373548825513647762608541 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.kmac_smoke.70603591031159146482880002064580124618934032560577665373548825513647762608541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.45516393386059086698022216698488711645522867851860377093534208505337569094206
Short name T609
Test name
Test status
Simulation time 47207151869 ps
CPU time 871.25 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:19:34 PM PST 23
Peak memory 339732 kb
Host smart-23933e51-7658-454c-8f7b-ce23de4556ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=45516393386059086698022216698488711645522867851860377093534208505337569094206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_st
ress_all.45516393386059086698022216698488711645522867851860377093534208505337569094206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.83748834300715272810587706908615470716603542819563526249211582652957920597183
Short name T902
Test name
Test status
Simulation time 322955517 ps
CPU time 6.13 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219260 kb
Host smart-9cda6eec-2ed6-4572-828f-d8a76ab5ce8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83748834300715272810587706908615470716603542819563526
249211582652957920597183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac.83748834300715272810587706908615470716
603542819563526249211582652957920597183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.83458059931172185626046459426594366320909449422920762419913540423107162091202
Short name T237
Test name
Test status
Simulation time 309259198 ps
CPU time 5.68 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:05:06 PM PST 23
Peak memory 219052 kb
Host smart-44050ab6-f90b-41cc-ae9f-613fd12ff007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83458059931172185626046459426594366320909449422920762
419913540423107162091202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.834580599311721856260464594265
94366320909449422920762419913540423107162091202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.33051358493315958350258944925131838323588598071303918917020282554502714516035
Short name T725
Test name
Test status
Simulation time 117329894454 ps
CPU time 2144.53 seconds
Started Nov 22 02:04:57 PM PST 23
Finished Nov 22 02:40:43 PM PST 23
Peak memory 400868 kb
Host smart-36cda69f-8025-4b61-a7b2-f96c917ce748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=33051358493315958350258944925131838323588598071303918917020282554502714516035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_224.33051358493315958350258944925131838323588598071303918917020282554502714516035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.7566558261058759476906111343599248280893367086019392021276631147432022949349
Short name T639
Test name
Test status
Simulation time 106843317633 ps
CPU time 1972.58 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:37:58 PM PST 23
Peak memory 376408 kb
Host smart-1a08d9b2-3b8f-4da7-b7fd-bcf311277050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=7566558261058759476906111343599248280893367086019392021276631147432022949349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
kmac_test_vectors_sha3_256.7566558261058759476906111343599248280893367086019392021276631147432022949349 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.75317694832692755282268223227947189873452555776972283917115618843362967272124
Short name T494
Test name
Test status
Simulation time 83520343504 ps
CPU time 1516.49 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:30:16 PM PST 23
Peak memory 338432 kb
Host smart-912d8ef0-d95d-4947-b052-ae1c50dd5df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=75317694832692755282268223227947189873452555776972283917115618843362967272124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_384.75317694832692755282268223227947189873452555776972283917115618843362967272124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.91459018621720254801501571371897433631962219305251971747906558215716252146325
Short name T1007
Test name
Test status
Simulation time 57499426673 ps
CPU time 1197.72 seconds
Started Nov 22 02:04:58 PM PST 23
Finished Nov 22 02:24:57 PM PST 23
Peak memory 297788 kb
Host smart-02083db5-bcf7-4e1a-a867-ef9aa672af00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91459018621720254801501571371897433631962219305251971747906558215716252146325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_512.91459018621720254801501571371897433631962219305251971747906558215716252146325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.12885239555471841444350394619618177881353288105001866835623006249615429129067
Short name T672
Test name
Test status
Simulation time 320694338954 ps
CPU time 5286.47 seconds
Started Nov 22 02:04:56 PM PST 23
Finished Nov 22 03:33:04 PM PST 23
Peak memory 674328 kb
Host smart-f4e3a484-9267-4d27-9f67-69769ee3f413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=12885239555471841444350394619618177881353288105001866835623006249615429129067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.kmac_test_vectors_shake_128.12885239555471841444350394619618177881353288105001866835623006249615429129067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.58058755700368475897647089046005950113448512320266846633196376274887704610732
Short name T200
Test name
Test status
Simulation time 270085708112 ps
CPU time 4449.26 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 03:19:10 PM PST 23
Peak memory 577400 kb
Host smart-ceea0d0c-ce1c-42b5-8563-fd7c2fd7494a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=58058755700368475897647089046005950113448512320266846633196376274887704610732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.kmac_test_vectors_shake_256.58058755700368475897647089046005950113448512320266846633196376274887704610732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.15553527972755706722193233047942936525012580097878272104540285759940740845581
Short name T141
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:06 PM PST 23
Peak memory 218956 kb
Host smart-4675a7a2-fcae-40c2-bb04-f1744dbd3641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553527972755706722193233047942936525012580097878272104540285759940740845581 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.kmac_alert_test.15553527972755706722193233047942936525012580097878272104540285759940740845581 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.108458487176105673711222856101030348998423317722818875212254507650428742270750
Short name T231
Test name
Test status
Simulation time 6076748772 ps
CPU time 103.06 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:06:43 PM PST 23
Peak memory 236224 kb
Host smart-159faa50-b217-42fb-b625-93075d6cbe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108458487176105673711222856101030348998423317722818875212254507650428742270750 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.kmac_app.108458487176105673711222856101030348998423317722818875212254507650428742270750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.9416921208638175745509448548085142356800704473181217615439532470873207026508
Short name T379
Test name
Test status
Simulation time 14830000174 ps
CPU time 393.76 seconds
Started Nov 22 02:04:59 PM PST 23
Finished Nov 22 02:11:34 PM PST 23
Peak memory 243172 kb
Host smart-ef1a6534-3460-45a4-b11e-2217bbb55f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9416921208638175745509448548085142356800704473181217615439532470873207026508 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.kmac_burst_write.9416921208638175745509448548085142356800704473181217615439532470873207026508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.112385923436851093125126157208317075669475964370140709148351486813272515814328
Short name T636
Test name
Test status
Simulation time 7238810904 ps
CPU time 111.34 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:06:55 PM PST 23
Peak memory 243864 kb
Host smart-ec3aad82-d1cc-4c12-968c-5d3e12242a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112385923436851093125126157208317075669475964370140709148351486813272515814328 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_entropy_refresh.112385923436851093125126157208317075669475964370140709148351486813272515814328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.41464451073754771626158438051551932087622825541540929472366393297730043656057
Short name T496
Test name
Test status
Simulation time 8137821569 ps
CPU time 139.88 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:07:27 PM PST 23
Peak memory 252852 kb
Host smart-03489c45-8f93-455d-b9ad-6a5b518a7c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41464451073754771626158438051551932087622825541540929472366393297730043656057 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.kmac_error.41464451073754771626158438051551932087622825541540929472366393297730043656057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.54953378653946606411280192116305276666882075642536890401697340726408358880728
Short name T316
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.89 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:07 PM PST 23
Peak memory 219156 kb
Host smart-6648bc21-b9f6-4dcb-9392-3c56d59c9545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54953378653946606411280192116305276666882075642536890401697340726408358880728 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.kmac_key_error.54953378653946606411280192116305276666882075642536890401697340726408358880728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.112286735728872892790174559799812396360589058155562287395140598874351865702485
Short name T83
Test name
Test status
Simulation time 72761090 ps
CPU time 1.53 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:05 PM PST 23
Peak memory 220456 kb
Host smart-317073bb-bbf7-46fc-9de5-827d223e0afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112286735728872892790174559799812396360589058155562287395140598874351865702485 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.kmac_lc_escalation.112286735728872892790174559799812396360589058155562287395140598874351865702485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.70178309587766356408723410634164411243103399421487115190953967448838839452095
Short name T139
Test name
Test status
Simulation time 50513696845 ps
CPU time 1005.08 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:21:53 PM PST 23
Peak memory 306316 kb
Host smart-a5fdd112-2192-4a2f-a701-693f277ffb62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70178309587766356408723410634164411243103399421487115190953967448838839452095 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.701783095877663564087234106341644112431033994214871151909539674488388
39452095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.83623930404775736225208940752522939795711858068024410571160400482999276707070
Short name T597
Test name
Test status
Simulation time 7628111361 ps
CPU time 144.47 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:07:34 PM PST 23
Peak memory 236420 kb
Host smart-33b0a766-edea-4dda-9ccf-ede89a1050db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83623930404775736225208940752522939795711858068024410571160400482999276707070 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.kmac_sideload.83623930404775736225208940752522939795711858068024410571160400482999276707070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.104119266930632485825714329031059175886345543793133673016642320529828827416232
Short name T539
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.82 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:05:36 PM PST 23
Peak memory 225400 kb
Host smart-8850978d-25ed-4003-b9d5-c32005a37472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104119266930632485825714329031059175886345543793133673016642320529828827416232 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.kmac_smoke.104119266930632485825714329031059175886345543793133673016642320529828827416232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.65963430780419555126907428337634152237284904050987318037734189839947654079318
Short name T954
Test name
Test status
Simulation time 47207151869 ps
CPU time 900.44 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:20:07 PM PST 23
Peak memory 339876 kb
Host smart-cee3f861-6aeb-4560-908c-161cc54937c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=65963430780419555126907428337634152237284904050987318037734189839947654079318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_st
ress_all.65963430780419555126907428337634152237284904050987318037734189839947654079318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.30513761366307114328821347465762230195977843122544420847736498236373935269149
Short name T209
Test name
Test status
Simulation time 322955517 ps
CPU time 6.36 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:05:14 PM PST 23
Peak memory 219176 kb
Host smart-3b8aa19b-66b7-419d-9068-4dc992a1103c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513761366307114328821347465762230195977843122544420
847736498236373935269149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac.30513761366307114328821347465762230195
977843122544420847736498236373935269149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.93232480757573384616184376462512858874100859004492327047833436434744299491571
Short name T528
Test name
Test status
Simulation time 309259198 ps
CPU time 5.91 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:13 PM PST 23
Peak memory 219256 kb
Host smart-1ada01c0-b8a7-4c57-85ea-c839cb650435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93232480757573384616184376462512858874100859004492327
047833436434744299491571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.932324807575733846161843764625
12858874100859004492327047833436434744299491571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.46671624703994117383649063870998114291971945078848421730246845443829620111732
Short name T613
Test name
Test status
Simulation time 117329894454 ps
CPU time 2116.09 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:40:23 PM PST 23
Peak memory 400836 kb
Host smart-89f9d403-661e-4f33-81b6-8be58c3111a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=46671624703994117383649063870998114291971945078848421730246845443829620111732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_224.46671624703994117383649063870998114291971945078848421730246845443829620111732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.30869778645001347394653945083037995666861390062370999938683936983255628017479
Short name T953
Test name
Test status
Simulation time 106843317633 ps
CPU time 1934.18 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:37:19 PM PST 23
Peak memory 376368 kb
Host smart-a3958f29-cf71-44f0-a22b-8e82e7fd8373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30869778645001347394653945083037995666861390062370999938683936983255628017479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_256.30869778645001347394653945083037995666861390062370999938683936983255628017479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.4364404633032870292828045604057799153854163631432569831635099739615726011655
Short name T767
Test name
Test status
Simulation time 83520343504 ps
CPU time 1519.44 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:30:30 PM PST 23
Peak memory 338492 kb
Host smart-02a89dce-fad7-4c27-aafa-e2dcf807754b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4364404633032870292828045604057799153854163631432569831635099739615726011655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
kmac_test_vectors_sha3_384.4364404633032870292828045604057799153854163631432569831635099739615726011655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.113168682531588048306185292674640060184491657148576778999529939043867265067167
Short name T256
Test name
Test status
Simulation time 57499426673 ps
CPU time 1176.8 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:24:40 PM PST 23
Peak memory 297820 kb
Host smart-cd6bfb3e-ad5a-4396-8e02-547f54a4ba78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113168682531588048306185292674640060184491657148576778999529939043867265067167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.kmac_test_vectors_sha3_512.113168682531588048306185292674640060184491657148576778999529939043867265067167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.36823078315887144265295131837809417873529792867306848215500713319663063464646
Short name T697
Test name
Test status
Simulation time 320694338954 ps
CPU time 5415.89 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 03:35:19 PM PST 23
Peak memory 674284 kb
Host smart-0dd675f7-700d-4ec4-b7a0-52672758733d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=36823078315887144265295131837809417873529792867306848215500713319663063464646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.kmac_test_vectors_shake_128.36823078315887144265295131837809417873529792867306848215500713319663063464646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.40420143845716543161586187184010545690383064480511506864534922133429269191890
Short name T356
Test name
Test status
Simulation time 270085708112 ps
CPU time 4673.33 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 03:22:55 PM PST 23
Peak memory 577252 kb
Host smart-d9dfe0a4-c7ed-40c3-b247-5a54130e71a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=40420143845716543161586187184010545690383064480511506864534922133429269191890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.kmac_test_vectors_shake_256.40420143845716543161586187184010545690383064480511506864534922133429269191890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.62016850155889646053973883880030262678811226065214186040884689441889914903976
Short name T938
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219084 kb
Host smart-35298b47-64d9-4e01-ac25-daf4a937bdf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62016850155889646053973883880030262678811226065214186040884689441889914903976 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.kmac_alert_test.62016850155889646053973883880030262678811226065214186040884689441889914903976 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.88606915219853636046735227080737110812946664741680591048739833843693761285638
Short name T393
Test name
Test status
Simulation time 6076748772 ps
CPU time 91.78 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:06:36 PM PST 23
Peak memory 236156 kb
Host smart-88106bee-4157-403f-9663-dcbc553d1920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88606915219853636046735227080737110812946664741680591048739833843693761285638 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_app.88606915219853636046735227080737110812946664741680591048739833843693761285638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.9672938971439513013563688645392565516446759421951319013670290661002819754861
Short name T606
Test name
Test status
Simulation time 14830000174 ps
CPU time 380.04 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:11:27 PM PST 23
Peak memory 243272 kb
Host smart-f4fc4240-92c5-4633-a03f-a290809f1c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9672938971439513013563688645392565516446759421951319013670290661002819754861 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.kmac_burst_write.9672938971439513013563688645392565516446759421951319013670290661002819754861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.34410942997595257162996402861833150304379570887919452527538019238117499727295
Short name T952
Test name
Test status
Simulation time 7238810904 ps
CPU time 108.13 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:06:52 PM PST 23
Peak memory 243856 kb
Host smart-052e3be4-f417-4dfd-8e96-4e192bd9bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34410942997595257162996402861833150304379570887919452527538019238117499727295 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.kmac_entropy_refresh.34410942997595257162996402861833150304379570887919452527538019238117499727295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.64681013231438099904508937597090663672371776758062083624632849280296329287219
Short name T510
Test name
Test status
Simulation time 8137821569 ps
CPU time 147.48 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:07:30 PM PST 23
Peak memory 252760 kb
Host smart-f5442fae-461f-4d5f-b62a-f3cdee631de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64681013231438099904508937597090663672371776758062083624632849280296329287219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.kmac_error.64681013231438099904508937597090663672371776758062083624632849280296329287219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.53208819760090038123647518173834609013980690640937181946983297520330624098644
Short name T348
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.83 seconds
Started Nov 22 02:05:01 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219264 kb
Host smart-90e83a13-4278-4a3b-8852-e8536d5eb72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53208819760090038123647518173834609013980690640937181946983297520330624098644 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.kmac_key_error.53208819760090038123647518173834609013980690640937181946983297520330624098644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.6070006531683623795501983148843478281650464613262666675720280812998393847760
Short name T660
Test name
Test status
Simulation time 72761090 ps
CPU time 1.5 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:05:02 PM PST 23
Peak memory 220396 kb
Host smart-fc2f43f3-7941-48a1-b47e-9b717319ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6070006531683623795501983148843478281650464613262666675720280812998393847760 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.kmac_lc_escalation.6070006531683623795501983148843478281650464613262666675720280812998393847760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.115453371350817833071957304845371800753661902945973835454512846590104645247730
Short name T366
Test name
Test status
Simulation time 50513696845 ps
CPU time 992.99 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:21:41 PM PST 23
Peak memory 306336 kb
Host smart-cea0413b-4b59-4932-8805-62885b5e450c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115453371350817833071957304845371800753661902945973835454512846590104645247730 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.11545337135081783307195730484537180075366190294597383545451284659010
4645247730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.27828665373972677967488799166267966820323873754850286456739012544418496087668
Short name T1032
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.71 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:07:21 PM PST 23
Peak memory 236412 kb
Host smart-6ce412c8-ad89-4b86-b0a6-e9eec9118a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27828665373972677967488799166267966820323873754850286456739012544418496087668 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.kmac_sideload.27828665373972677967488799166267966820323873754850286456739012544418496087668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.34702346513620137328751303222282947351661544343378547653760291906299844840442
Short name T979
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.43 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:34 PM PST 23
Peak memory 225392 kb
Host smart-42fa252c-0a21-41ac-8474-1a010b0f7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34702346513620137328751303222282947351661544343378547653760291906299844840442 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.kmac_smoke.34702346513620137328751303222282947351661544343378547653760291906299844840442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.7636364577270059534549528211890787637895684211528624099246428634542696115694
Short name T724
Test name
Test status
Simulation time 47207151869 ps
CPU time 851.64 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:19:16 PM PST 23
Peak memory 339864 kb
Host smart-1107cdae-11c0-41ff-86c3-00e2558b786d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=7636364577270059534549528211890787637895684211528624099246428634542696115694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_str
ess_all.7636364577270059534549528211890787637895684211528624099246428634542696115694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.64332557717904715919900894212488108319666593566387177499789170852710624734739
Short name T780
Test name
Test status
Simulation time 322955517 ps
CPU time 5.76 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 219196 kb
Host smart-e8812314-e874-4480-b207-8b5ec6547569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64332557717904715919900894212488108319666593566387177
499789170852710624734739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac.64332557717904715919900894212488108319
666593566387177499789170852710624734739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.106869039309379924102429085905247518209938857511333709620806579595097388977609
Short name T260
Test name
Test status
Simulation time 309259198 ps
CPU time 5.91 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:05:10 PM PST 23
Peak memory 219272 kb
Host smart-132cefa4-e602-41fe-8491-4e972f5a6d0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686903930937992410242908590524751820993885751133370
9620806579595097388977609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.10686903930937992410242908590
5247518209938857511333709620806579595097388977609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.111386249705030647736250463746432801785967639463464000497891830779453955407364
Short name T309
Test name
Test status
Simulation time 117329894454 ps
CPU time 2108.59 seconds
Started Nov 22 02:05:03 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 400900 kb
Host smart-cc540631-1bb6-4a3b-b919-a0c68d0d9a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=111386249705030647736250463746432801785967639463464000497891830779453955407364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.kmac_test_vectors_sha3_224.111386249705030647736250463746432801785967639463464000497891830779453955407364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.6599625333485897541420215398540322591561444580024039862776229245206014444796
Short name T358
Test name
Test status
Simulation time 106843317633 ps
CPU time 1868.36 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 02:36:11 PM PST 23
Peak memory 376364 kb
Host smart-4909b8e6-4696-4a16-b2af-69e7259c261f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=6599625333485897541420215398540322591561444580024039862776229245206014444796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
kmac_test_vectors_sha3_256.6599625333485897541420215398540322591561444580024039862776229245206014444796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.45098308633987676274966480963121682369912101868434509649744456761407582046310
Short name T286
Test name
Test status
Simulation time 83520343504 ps
CPU time 1548.73 seconds
Started Nov 22 02:05:00 PM PST 23
Finished Nov 22 02:30:50 PM PST 23
Peak memory 338460 kb
Host smart-6807a46e-d061-4851-851c-fb09c25c9a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45098308633987676274966480963121682369912101868434509649744456761407582046310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.kmac_test_vectors_sha3_384.45098308633987676274966480963121682369912101868434509649744456761407582046310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.73616151133256240280386860518284021785200686941933930928875486710322098184689
Short name T542
Test name
Test status
Simulation time 57499426673 ps
CPU time 1185.68 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:24:53 PM PST 23
Peak memory 297764 kb
Host smart-a927d837-6852-4ab7-91fa-74b59d6269cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=73616151133256240280386860518284021785200686941933930928875486710322098184689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.kmac_test_vectors_sha3_512.73616151133256240280386860518284021785200686941933930928875486710322098184689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.27381649677513410907321283774804351097431919746487386881256123291964792012240
Short name T351
Test name
Test status
Simulation time 320694338954 ps
CPU time 5393.86 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 03:34:57 PM PST 23
Peak memory 674268 kb
Host smart-d3f88673-7ae0-4e84-a45d-37cb11c9be19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=27381649677513410907321283774804351097431919746487386881256123291964792012240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_test_vectors_shake_128.27381649677513410907321283774804351097431919746487386881256123291964792012240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.90252991411681567522912981492267326942084555886204460106838422939022404553370
Short name T729
Test name
Test status
Simulation time 270085708112 ps
CPU time 4555.22 seconds
Started Nov 22 02:05:02 PM PST 23
Finished Nov 22 03:20:59 PM PST 23
Peak memory 577308 kb
Host smart-acd50a13-aca3-4cb0-9bbd-0e48beb3308d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=90252991411681567522912981492267326942084555886204460106838422939022404553370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_test_vectors_shake_256.90252991411681567522912981492267326942084555886204460106838422939022404553370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.111683495254441131301268441297770372172284429911922012085546482943628253325400
Short name T956
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:05:13 PM PST 23
Peak memory 218996 kb
Host smart-66d52472-f87b-4dd4-b00e-eb9f234560b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111683495254441131301268441297770372172284429911922012085546482943628253325400 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.111683495254441131301268441297770372172284429911922012085546482943628253325400 +enable_masking=1
+sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3708680926617744406435743667345949613203061879721275544227215305092157401459
Short name T1060
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.18 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:06:55 PM PST 23
Peak memory 236212 kb
Host smart-af926a0a-fdfb-4783-ba8e-03d15cc2d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708680926617744406435743667345949613203061879721275544227215305092157401459 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_app.3708680926617744406435743667345949613203061879721275544227215305092157401459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.93098875718375493557651177092258964176149664496837716076707279714436969404850
Short name T869
Test name
Test status
Simulation time 14830000174 ps
CPU time 375.29 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:11:31 PM PST 23
Peak memory 243220 kb
Host smart-66e4b2ae-ff61-4b5f-9f79-295202c70bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93098875718375493557651177092258964176149664496837716076707279714436969404850 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.kmac_burst_write.93098875718375493557651177092258964176149664496837716076707279714436969404850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.52482652249856661128134558589617605636024856341277935041842837564584937636956
Short name T391
Test name
Test status
Simulation time 7238810904 ps
CPU time 111.74 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:07:04 PM PST 23
Peak memory 243708 kb
Host smart-bc588523-4e4a-4339-8e5c-5f1b0ebbfc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52482652249856661128134558589617605636024856341277935041842837564584937636956 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.kmac_entropy_refresh.52482652249856661128134558589617605636024856341277935041842837564584937636956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.66105983074033605361816606019715872039335186282999271015063563061518486357735
Short name T574
Test name
Test status
Simulation time 8137821569 ps
CPU time 148.89 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:07:39 PM PST 23
Peak memory 252856 kb
Host smart-0e1fb3a2-6f74-46ce-90ef-e5e9eb0ef454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66105983074033605361816606019715872039335186282999271015063563061518486357735 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.kmac_error.66105983074033605361816606019715872039335186282999271015063563061518486357735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.103754003668425201168793711971964368955985533861141019242738382512865082587105
Short name T282
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.86 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 02:05:13 PM PST 23
Peak memory 219216 kb
Host smart-bf2d553f-16bd-4e6b-8c5c-ffdd067fe0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103754003668425201168793711971964368955985533861141019242738382512865082587105 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.kmac_key_error.103754003668425201168793711971964368955985533861141019242738382512865082587105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.16246585433051757650565170976160138362394421927457325752259116903496703612999
Short name T353
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:05:11 PM PST 23
Peak memory 220584 kb
Host smart-5ce976dc-af7c-46df-9eac-075c3d35cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16246585433051757650565170976160138362394421927457325752259116903496703612999 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.kmac_lc_escalation.16246585433051757650565170976160138362394421927457325752259116903496703612999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.21547304716713931412663750329514755692965952616919013849991408713632961522073
Short name T254
Test name
Test status
Simulation time 50513696845 ps
CPU time 1000.06 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:21:53 PM PST 23
Peak memory 306144 kb
Host smart-d63318d5-f549-4ecf-9e18-82361dd6550c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21547304716713931412663750329514755692965952616919013849991408713632961522073 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.215473047167139314126637503295147556929659526169190138499914087136329
61522073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.81798762382876117159298686401949594966175289894999288729107028943333403877229
Short name T685
Test name
Test status
Simulation time 7628111361 ps
CPU time 133.19 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 02:07:20 PM PST 23
Peak memory 236436 kb
Host smart-0e5f3478-62fe-4baf-b0da-b5d86a0c6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81798762382876117159298686401949594966175289894999288729107028943333403877229 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.kmac_sideload.81798762382876117159298686401949594966175289894999288729107028943333403877229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.57937271312568407348948335069171004839416751005324929964497114581934054568317
Short name T462
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.09 seconds
Started Nov 22 02:05:05 PM PST 23
Finished Nov 22 02:05:32 PM PST 23
Peak memory 225368 kb
Host smart-5a6e7103-cd00-40d4-b465-4c4b4b56549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57937271312568407348948335069171004839416751005324929964497114581934054568317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.kmac_smoke.57937271312568407348948335069171004839416751005324929964497114581934054568317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.110261304964161461498748487781759939188559256025297243994424209301994093406707
Short name T686
Test name
Test status
Simulation time 47207151869 ps
CPU time 906.68 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:20:18 PM PST 23
Peak memory 339732 kb
Host smart-eb87ad68-eadf-4f61-a5c1-43d624b68233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=110261304964161461498748487781759939188559256025297243994424209301994093406707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_s
tress_all.110261304964161461498748487781759939188559256025297243994424209301994093406707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.28805163941143724093623206772693473084926862723013829271116908673849077538540
Short name T794
Test name
Test status
Simulation time 322955517 ps
CPU time 6.14 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:05:22 PM PST 23
Peak memory 219236 kb
Host smart-67dc2447-3dcf-4f09-9a59-e9af02a63491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805163941143724093623206772693473084926862723013829
271116908673849077538540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac.28805163941143724093623206772693473084
926862723013829271116908673849077538540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.64536129423120207493268922915144044570779273451050636434038348632565383195760
Short name T997
Test name
Test status
Simulation time 309259198 ps
CPU time 5.99 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:05:16 PM PST 23
Peak memory 219340 kb
Host smart-222e1399-5670-4f93-af4a-ab9b3d95f4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64536129423120207493268922915144044570779273451050636
434038348632565383195760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.645361294231202074932689229151
44044570779273451050636434038348632565383195760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.30095648614322987038868725159459899526930537116328646015250419495901423987050
Short name T296
Test name
Test status
Simulation time 117329894454 ps
CPU time 2071.17 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:39:39 PM PST 23
Peak memory 400848 kb
Host smart-6a223831-b2c8-4bf8-b8de-4d7068f727b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30095648614322987038868725159459899526930537116328646015250419495901423987050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_224.30095648614322987038868725159459899526930537116328646015250419495901423987050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.102780561361626146376809658454733913131647091741348513870291236389930465110750
Short name T434
Test name
Test status
Simulation time 106843317633 ps
CPU time 2006.64 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:38:43 PM PST 23
Peak memory 376424 kb
Host smart-7c0b0eb3-1a93-4bcb-8f54-7207580425e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=102780561361626146376809658454733913131647091741348513870291236389930465110750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.kmac_test_vectors_sha3_256.102780561361626146376809658454733913131647091741348513870291236389930465110750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.108422762045851353808104438993489880181381971116122778303417660550871229636717
Short name T287
Test name
Test status
Simulation time 83520343504 ps
CPU time 1586.54 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:31:38 PM PST 23
Peak memory 338388 kb
Host smart-3d02f10c-eeb0-44f8-8a68-644feb3fe5d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=108422762045851353808104438993489880181381971116122778303417660550871229636717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.kmac_test_vectors_sha3_384.108422762045851353808104438993489880181381971116122778303417660550871229636717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.38454985624955741137732131208606031524745868913809977317431423174129222486716
Short name T20
Test name
Test status
Simulation time 57499426673 ps
CPU time 1187.95 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:24:58 PM PST 23
Peak memory 297852 kb
Host smart-8c07ff72-8b9f-4c2a-8e34-8090f8deaa63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38454985624955741137732131208606031524745868913809977317431423174129222486716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_512.38454985624955741137732131208606031524745868913809977317431423174129222486716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.75613446497805015350158787044527967951651670041303149483413088056604973196394
Short name T873
Test name
Test status
Simulation time 320694338954 ps
CPU time 5486.7 seconds
Started Nov 22 02:05:04 PM PST 23
Finished Nov 22 03:36:32 PM PST 23
Peak memory 674268 kb
Host smart-08e1c9c0-de82-4839-b0b7-16164d448e79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=75613446497805015350158787044527967951651670041303149483413088056604973196394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_test_vectors_shake_128.75613446497805015350158787044527967951651670041303149483413088056604973196394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.17980725291378474248837274495637059230412787495502051212558221074507802032999
Short name T1002
Test name
Test status
Simulation time 270085708112 ps
CPU time 4656.39 seconds
Started Nov 22 02:05:06 PM PST 23
Finished Nov 22 03:22:44 PM PST 23
Peak memory 577320 kb
Host smart-fd34531b-66e2-4900-b810-882d5e211e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=17980725291378474248837274495637059230412787495502051212558221074507802032999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_test_vectors_shake_256.17980725291378474248837274495637059230412787495502051212558221074507802032999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.93684882473856296700989222891928525776314566826222088280227759920595355570914
Short name T851
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:05:11 PM PST 23
Peak memory 218892 kb
Host smart-6a4910e7-c931-4bb8-8d87-a0b2c93c5137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93684882473856296700989222891928525776314566826222088280227759920595355570914 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.kmac_alert_test.93684882473856296700989222891928525776314566826222088280227759920595355570914 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.8617216499532825044981754755762258514802967686093539569894932869379575038569
Short name T342
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.32 seconds
Started Nov 22 02:05:20 PM PST 23
Finished Nov 22 02:07:00 PM PST 23
Peak memory 236240 kb
Host smart-3cf281b5-e442-4b39-a9ea-999baced1344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8617216499532825044981754755762258514802967686093539569894932869379575038569 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_app.8617216499532825044981754755762258514802967686093539569894932869379575038569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.49139158760994022173663064595079808045032367612302842079945164594205790060595
Short name T616
Test name
Test status
Simulation time 14830000174 ps
CPU time 399.1 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:11:48 PM PST 23
Peak memory 243324 kb
Host smart-0dfdbb9e-eeff-40a2-aa4f-e4332f29ba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49139158760994022173663064595079808045032367612302842079945164594205790060595 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.kmac_burst_write.49139158760994022173663064595079808045032367612302842079945164594205790060595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.43184961275006208459055952523216066690937545299881473879037469457157951840666
Short name T837
Test name
Test status
Simulation time 7238810904 ps
CPU time 110.81 seconds
Started Nov 22 02:05:20 PM PST 23
Finished Nov 22 02:07:12 PM PST 23
Peak memory 243936 kb
Host smart-13b53361-f9dd-49fd-a48e-cb197ce23c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43184961275006208459055952523216066690937545299881473879037469457157951840666 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.kmac_entropy_refresh.43184961275006208459055952523216066690937545299881473879037469457157951840666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.945891347652059446878487338753901270517393096347692206417056553455519120498
Short name T214
Test name
Test status
Simulation time 8137821569 ps
CPU time 147.01 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:07:39 PM PST 23
Peak memory 252756 kb
Host smart-87fb6bd8-c68d-4db9-b633-8a58d62cbb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945891347652059446878487338753901270517393096347692206417056553455519120498 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_error.945891347652059446878487338753901270517393096347692206417056553455519120498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.38637892308253330018438049176863293535218219466810792780037862823635053566666
Short name T520
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.71 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:05:21 PM PST 23
Peak memory 219224 kb
Host smart-dc0dbd6c-2ec5-402a-b89b-8e145662d01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38637892308253330018438049176863293535218219466810792780037862823635053566666 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.kmac_key_error.38637892308253330018438049176863293535218219466810792780037862823635053566666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.5124960147067498738929410367919976797354408578114584152503594996037166584903
Short name T193
Test name
Test status
Simulation time 72761090 ps
CPU time 1.53 seconds
Started Nov 22 02:05:21 PM PST 23
Finished Nov 22 02:05:23 PM PST 23
Peak memory 220512 kb
Host smart-cfc58730-93c9-499a-ace5-d21cf10d111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5124960147067498738929410367919976797354408578114584152503594996037166584903 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.kmac_lc_escalation.5124960147067498738929410367919976797354408578114584152503594996037166584903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.84172270742537510580622716829344508329429955792001014713007290359614010138462
Short name T148
Test name
Test status
Simulation time 50513696845 ps
CPU time 1033.75 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 306144 kb
Host smart-23678610-6c72-42bf-a7d8-bcd6efeded0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84172270742537510580622716829344508329429955792001014713007290359614010138462 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.841722707425375105806227168293445083294299557920010147130072903596140
10138462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.71672253173117861842131410995627760648003827765031673806983982099185477163374
Short name T447
Test name
Test status
Simulation time 7628111361 ps
CPU time 140.77 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:07:33 PM PST 23
Peak memory 236196 kb
Host smart-e0d71a5e-ef03-4c54-8794-1ead6138fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71672253173117861842131410995627760648003827765031673806983982099185477163374 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.kmac_sideload.71672253173117861842131410995627760648003827765031673806983982099185477163374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.47190857727083251543998606103987701695807990284954729452694399374316511075366
Short name T532
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.58 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:05:38 PM PST 23
Peak memory 225296 kb
Host smart-4facadc9-8e95-414b-8c9b-4f232bcec63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47190857727083251543998606103987701695807990284954729452694399374316511075366 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.kmac_smoke.47190857727083251543998606103987701695807990284954729452694399374316511075366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.113418864426961922967764387035375184882918870333535235172354334363306445617940
Short name T781
Test name
Test status
Simulation time 47207151869 ps
CPU time 843.03 seconds
Started Nov 22 02:05:16 PM PST 23
Finished Nov 22 02:19:19 PM PST 23
Peak memory 339776 kb
Host smart-a89bc833-185c-47b0-b799-0a6ea0bc692d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=113418864426961922967764387035375184882918870333535235172354334363306445617940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_s
tress_all.113418864426961922967764387035375184882918870333535235172354334363306445617940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.88552852967282500687673889511606968242404514298033403569969129859421109293229
Short name T762
Test name
Test status
Simulation time 322955517 ps
CPU time 5.81 seconds
Started Nov 22 02:05:07 PM PST 23
Finished Nov 22 02:05:14 PM PST 23
Peak memory 219244 kb
Host smart-0e8c97b6-9365-45f6-bdde-ccb5b1b5aaf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88552852967282500687673889511606968242404514298033403
569969129859421109293229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac.88552852967282500687673889511606968242
404514298033403569969129859421109293229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1835259833437456708027154500648168330054594450911240220556309185788497005676
Short name T787
Test name
Test status
Simulation time 309259198 ps
CPU time 5.67 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:05:18 PM PST 23
Peak memory 219252 kb
Host smart-fbba665a-adf7-429c-b574-3b6a0ed2e7bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352598334374567080271545006481683300545944509112402
20556309185788497005676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1835259833437456708027154500648
168330054594450911240220556309185788497005676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.60095545181671387269528068304262692554190644107763358162173268254971184651810
Short name T836
Test name
Test status
Simulation time 117329894454 ps
CPU time 2033.43 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:39:03 PM PST 23
Peak memory 400956 kb
Host smart-9b0d1410-31f6-4a63-a26c-0bf5bd70617f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=60095545181671387269528068304262692554190644107763358162173268254971184651810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_224.60095545181671387269528068304262692554190644107763358162173268254971184651810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.16385156138770512304841570532883560925329116258091098323689835376188173009310
Short name T900
Test name
Test status
Simulation time 106843317633 ps
CPU time 1958.28 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:37:49 PM PST 23
Peak memory 376280 kb
Host smart-c3055f47-1d5b-45a3-a3e2-7422ec640f27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16385156138770512304841570532883560925329116258091098323689835376188173009310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_256.16385156138770512304841570532883560925329116258091098323689835376188173009310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.86145290518457061436576821378947041875451928343914176758043140992155781845880
Short name T943
Test name
Test status
Simulation time 83520343504 ps
CPU time 1545.49 seconds
Started Nov 22 02:05:09 PM PST 23
Finished Nov 22 02:30:55 PM PST 23
Peak memory 338448 kb
Host smart-7380de68-5073-4015-9c4b-cab7360c4594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86145290518457061436576821378947041875451928343914176758043140992155781845880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_384.86145290518457061436576821378947041875451928343914176758043140992155781845880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.8414629702566290860210095955832986541817778528732319893709724172253760472566
Short name T870
Test name
Test status
Simulation time 57499426673 ps
CPU time 1260.49 seconds
Started Nov 22 02:05:08 PM PST 23
Finished Nov 22 02:26:10 PM PST 23
Peak memory 297792 kb
Host smart-b3f61756-fd24-4c93-a49c-31d756f6ba9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8414629702566290860210095955832986541817778528732319893709724172253760472566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
kmac_test_vectors_sha3_512.8414629702566290860210095955832986541817778528732319893709724172253760472566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.14905940911283053001038758704887495738733819224649347748715544559284002767987
Short name T664
Test name
Test status
Simulation time 320694338954 ps
CPU time 5417.38 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 03:35:30 PM PST 23
Peak memory 674084 kb
Host smart-5865a016-6fc8-43a1-bc5d-cb5791e368bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=14905940911283053001038758704887495738733819224649347748715544559284002767987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_test_vectors_shake_128.14905940911283053001038758704887495738733819224649347748715544559284002767987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.111921786205005958900040999831482807940901710879463192929212499110960519396095
Short name T916
Test name
Test status
Simulation time 270085708112 ps
CPU time 4533.37 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 03:20:45 PM PST 23
Peak memory 577216 kb
Host smart-904e0221-f5a1-4577-a8eb-5729833d09d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=111921786205005958900040999831482807940901710879463192929212499110960519396095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_test_vectors_shake_256.111921786205005958900040999831482807940901710879463192929212499110960519396095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.53301370098355535440826456589078821932675226678240687575059386724263571315063
Short name T501
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 02:05:18 PM PST 23
Finished Nov 22 02:05:19 PM PST 23
Peak memory 219016 kb
Host smart-9668fabf-f1c6-4795-92dc-b794097611d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53301370098355535440826456589078821932675226678240687575059386724263571315063 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.kmac_alert_test.53301370098355535440826456589078821932675226678240687575059386724263571315063 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.105873842806966202728726439095141744185900659573903900026731365987054836727711
Short name T154
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.85 seconds
Started Nov 22 02:05:13 PM PST 23
Finished Nov 22 02:06:54 PM PST 23
Peak memory 236256 kb
Host smart-7ddd7a97-8c86-4944-acc7-5cc11652dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105873842806966202728726439095141744185900659573903900026731365987054836727711 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.kmac_app.105873842806966202728726439095141744185900659573903900026731365987054836727711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.62181942000245725613654001689555840125645820837471691373298539369796403567428
Short name T626
Test name
Test status
Simulation time 14830000174 ps
CPU time 379.59 seconds
Started Nov 22 02:05:15 PM PST 23
Finished Nov 22 02:11:36 PM PST 23
Peak memory 243240 kb
Host smart-00b6a077-fb34-4b68-8e79-632ce3103bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62181942000245725613654001689555840125645820837471691373298539369796403567428 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.kmac_burst_write.62181942000245725613654001689555840125645820837471691373298539369796403567428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.67474161253630096046843154953460426966495557769056970103202075162289968734541
Short name T750
Test name
Test status
Simulation time 7238810904 ps
CPU time 114.91 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:07:07 PM PST 23
Peak memory 243908 kb
Host smart-e4db50d8-ce8d-4c04-b872-db594dd80a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67474161253630096046843154953460426966495557769056970103202075162289968734541 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.kmac_entropy_refresh.67474161253630096046843154953460426966495557769056970103202075162289968734541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.98200540773103054733714821717963224923449500708970410131308047863362360090858
Short name T644
Test name
Test status
Simulation time 8137821569 ps
CPU time 139.08 seconds
Started Nov 22 02:05:17 PM PST 23
Finished Nov 22 02:07:37 PM PST 23
Peak memory 252784 kb
Host smart-8a6ecc4d-745c-4add-a0c7-5a6046fc9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98200540773103054733714821717963224923449500708970410131308047863362360090858 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.kmac_error.98200540773103054733714821717963224923449500708970410131308047863362360090858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.56149692722746594982069513625446211209738280056393994320997291310433258740467
Short name T562
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.89 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:05:19 PM PST 23
Peak memory 219224 kb
Host smart-b9092573-2972-4f3d-9487-c9ff99a8d8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56149692722746594982069513625446211209738280056393994320997291310433258740467 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.kmac_key_error.56149692722746594982069513625446211209738280056393994320997291310433258740467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.114474719416961935700892937182748499316176064536140605562277026256699479199915
Short name T706
Test name
Test status
Simulation time 72761090 ps
CPU time 1.49 seconds
Started Nov 22 02:05:20 PM PST 23
Finished Nov 22 02:05:22 PM PST 23
Peak memory 220516 kb
Host smart-28fc1c7f-e32b-4696-8ed2-603a683c6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114474719416961935700892937182748499316176064536140605562277026256699479199915 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.kmac_lc_escalation.114474719416961935700892937182748499316176064536140605562277026256699479199915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.104648462157337693392161454718293857397855024155723014078933729871669315167618
Short name T290
Test name
Test status
Simulation time 50513696845 ps
CPU time 991.53 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:21:45 PM PST 23
Peak memory 306260 kb
Host smart-853e7084-ec2c-4d34-9a69-1c02e90226e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104648462157337693392161454718293857397855024155723014078933729871669315167618 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.10464846215733769339216145471829385739785502415572301407893372987166
9315167618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.109256634439698853149731156400901220758779293426030625963119780126773363701186
Short name T196
Test name
Test status
Simulation time 7628111361 ps
CPU time 132.93 seconds
Started Nov 22 02:05:14 PM PST 23
Finished Nov 22 02:07:28 PM PST 23
Peak memory 236336 kb
Host smart-f426b1c0-b1d2-4c58-90bd-65a6d4bc7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109256634439698853149731156400901220758779293426030625963119780126773363701186 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.kmac_sideload.109256634439698853149731156400901220758779293426030625963119780126773363701186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.93353403492204900452168994470506548802744679849077659713578783627677293679894
Short name T905
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.06 seconds
Started Nov 22 02:05:17 PM PST 23
Finished Nov 22 02:05:45 PM PST 23
Peak memory 225396 kb
Host smart-37fa52f2-2fcb-4274-be40-5a324d70f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93353403492204900452168994470506548802744679849077659713578783627677293679894 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.kmac_smoke.93353403492204900452168994470506548802744679849077659713578783627677293679894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.110306487947283664729020739314691830961561063395732517956994326970463886035124
Short name T514
Test name
Test status
Simulation time 47207151869 ps
CPU time 872.63 seconds
Started Nov 22 02:05:17 PM PST 23
Finished Nov 22 02:19:51 PM PST 23
Peak memory 339848 kb
Host smart-f261a898-7d52-4aec-8a50-842a1227a127
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=110306487947283664729020739314691830961561063395732517956994326970463886035124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_s
tress_all.110306487947283664729020739314691830961561063395732517956994326970463886035124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.37218734393632043275470290780909302746194584278277607226828042222333547201307
Short name T983
Test name
Test status
Simulation time 322955517 ps
CPU time 5.87 seconds
Started Nov 22 02:05:20 PM PST 23
Finished Nov 22 02:05:26 PM PST 23
Peak memory 219300 kb
Host smart-678146bc-3e3d-4db7-b29c-e925156b6052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37218734393632043275470290780909302746194584278277607
226828042222333547201307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac.37218734393632043275470290780909302746
194584278277607226828042222333547201307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.43537495741820139318084465879113549525088023551305831177501021890039834956568
Short name T180
Test name
Test status
Simulation time 309259198 ps
CPU time 5.55 seconds
Started Nov 22 02:05:14 PM PST 23
Finished Nov 22 02:05:20 PM PST 23
Peak memory 219176 kb
Host smart-87b6be4a-ed8f-4b55-a6e8-41c602182ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43537495741820139318084465879113549525088023551305831
177501021890039834956568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.435374957418201393180844658791
13549525088023551305831177501021890039834956568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.82362414277534470876191440725677325470092707271436202099356269934841635148113
Short name T871
Test name
Test status
Simulation time 117329894454 ps
CPU time 2075.53 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:39:49 PM PST 23
Peak memory 400784 kb
Host smart-61c9a23c-f50f-40f4-b275-5495aadd2572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82362414277534470876191440725677325470092707271436202099356269934841635148113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_224.82362414277534470876191440725677325470092707271436202099356269934841635148113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.78850259240653702996858292431029138610220860118821392816820338348313425159325
Short name T375
Test name
Test status
Simulation time 106843317633 ps
CPU time 1897 seconds
Started Nov 22 02:05:13 PM PST 23
Finished Nov 22 02:36:51 PM PST 23
Peak memory 376316 kb
Host smart-c38c1b51-973e-4927-a44a-e26cc93b75b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=78850259240653702996858292431029138610220860118821392816820338348313425159325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_256.78850259240653702996858292431029138610220860118821392816820338348313425159325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.16108653928477682703494191531773357060905896533461115251621137269339670404626
Short name T998
Test name
Test status
Simulation time 83520343504 ps
CPU time 1624.29 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:32:15 PM PST 23
Peak memory 338452 kb
Host smart-963279cb-afa4-4d35-950f-07d171a65115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16108653928477682703494191531773357060905896533461115251621137269339670404626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_384.16108653928477682703494191531773357060905896533461115251621137269339670404626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.81983622722594415991602967103485719136917141802386521297734065962522565127943
Short name T877
Test name
Test status
Simulation time 57499426673 ps
CPU time 1164.33 seconds
Started Nov 22 02:05:16 PM PST 23
Finished Nov 22 02:24:41 PM PST 23
Peak memory 297736 kb
Host smart-95839db0-969b-4ef0-bbd3-a9e5b6312650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=81983622722594415991602967103485719136917141802386521297734065962522565127943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_512.81983622722594415991602967103485719136917141802386521297734065962522565127943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.54213597568741046341544700226908656878325622900802224271523096039596960399531
Short name T398
Test name
Test status
Simulation time 320694338954 ps
CPU time 5376.34 seconds
Started Nov 22 02:05:19 PM PST 23
Finished Nov 22 03:34:56 PM PST 23
Peak memory 674316 kb
Host smart-1b2afb45-8b1b-4ba1-af21-dbb055e5b984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=54213597568741046341544700226908656878325622900802224271523096039596960399531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.kmac_test_vectors_shake_128.54213597568741046341544700226908656878325622900802224271523096039596960399531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.64453497881494225821178196769493305513942163161997180713953817205879403708723
Short name T417
Test name
Test status
Simulation time 270085708112 ps
CPU time 4444.05 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 03:19:17 PM PST 23
Peak memory 577260 kb
Host smart-1520ab3a-339e-4484-84be-6ee5e0821514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=64453497881494225821178196769493305513942163161997180713953817205879403708723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.kmac_test_vectors_shake_256.64453497881494225821178196769493305513942163161997180713953817205879403708723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.69889715595539216172685809206411783668199084743020821601777732699231786894404
Short name T138
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:59 PM PST 23
Finished Nov 22 02:06:00 PM PST 23
Peak memory 219112 kb
Host smart-db00f8a6-441d-433c-be2a-9eb142efeff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69889715595539216172685809206411783668199084743020821601777732699231786894404 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.kmac_alert_test.69889715595539216172685809206411783668199084743020821601777732699231786894404 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.25472220163827146956245073520426987910629282639827942608116925353916135113339
Short name T515
Test name
Test status
Simulation time 6076748772 ps
CPU time 106.83 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:07:43 PM PST 23
Peak memory 236252 kb
Host smart-98daef0a-4b13-448a-bae1-c224aa15c34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25472220163827146956245073520426987910629282639827942608116925353916135113339 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.kmac_app.25472220163827146956245073520426987910629282639827942608116925353916135113339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.27566768940263455027569031670080977374993053012342110970399506029137350834053
Short name T822
Test name
Test status
Simulation time 14830000174 ps
CPU time 391.53 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:11:44 PM PST 23
Peak memory 243300 kb
Host smart-59e1c79d-d055-41f4-8f84-3633d55530a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27566768940263455027569031670080977374993053012342110970399506029137350834053 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.kmac_burst_write.27566768940263455027569031670080977374993053012342110970399506029137350834053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.43678738992322456492238992002612038856415844665192293977859703192149546962141
Short name T184
Test name
Test status
Simulation time 7238810904 ps
CPU time 104.09 seconds
Started Nov 22 02:06:20 PM PST 23
Finished Nov 22 02:08:06 PM PST 23
Peak memory 243816 kb
Host smart-01da098f-0a56-4337-82a3-70a964a53eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43678738992322456492238992002612038856415844665192293977859703192149546962141 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.kmac_entropy_refresh.43678738992322456492238992002612038856415844665192293977859703192149546962141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.82948790083588516037841130844220196249231955718766935019740182465699614635427
Short name T473
Test name
Test status
Simulation time 8137821569 ps
CPU time 142.89 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:08:18 PM PST 23
Peak memory 252768 kb
Host smart-cad6bebf-96f2-4316-8868-2b76e83d9810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82948790083588516037841130844220196249231955718766935019740182465699614635427 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.kmac_error.82948790083588516037841130844220196249231955718766935019740182465699614635427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.112735418108359367497250298007374817261683392249213315690582482310183439334209
Short name T76
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.82 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:06:01 PM PST 23
Peak memory 219244 kb
Host smart-32a20bbd-4bb6-4ea7-b405-db412c123fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112735418108359367497250298007374817261683392249213315690582482310183439334209 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.kmac_key_error.112735418108359367497250298007374817261683392249213315690582482310183439334209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.30505857193407219978662308257873207989931403314072708258668351611269497196683
Short name T924
Test name
Test status
Simulation time 72761090 ps
CPU time 1.59 seconds
Started Nov 22 02:06:06 PM PST 23
Finished Nov 22 02:06:08 PM PST 23
Peak memory 220508 kb
Host smart-9bcc31da-2a95-4d87-aa6b-d21214935be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30505857193407219978662308257873207989931403314072708258668351611269497196683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.kmac_lc_escalation.30505857193407219978662308257873207989931403314072708258668351611269497196683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.88238316344710055642450655826381095245627188498964805475722691844366571517045
Short name T919
Test name
Test status
Simulation time 50513696845 ps
CPU time 972.83 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:21:26 PM PST 23
Peak memory 306344 kb
Host smart-eab6bacc-3cad-4f01-abe0-a58eaac993e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88238316344710055642450655826381095245627188498964805475722691844366571517045 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.882383163447100556424506558263810952456271884989648054757226918443665
71517045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.67068034811088457644045849646738743769655386729323437324145522088038107561107
Short name T566
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.59 seconds
Started Nov 22 02:05:18 PM PST 23
Finished Nov 22 02:07:36 PM PST 23
Peak memory 236392 kb
Host smart-4a834d53-df43-4654-92fb-d1d599724c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67068034811088457644045849646738743769655386729323437324145522088038107561107 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.kmac_sideload.67068034811088457644045849646738743769655386729323437324145522088038107561107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.7759060491509504519784706457633821518558532579186725327998413746026361518297
Short name T210
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.24 seconds
Started Nov 22 02:05:10 PM PST 23
Finished Nov 22 02:05:39 PM PST 23
Peak memory 225492 kb
Host smart-07554b7d-6567-4850-8367-a9a5a88fa5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7759060491509504519784706457633821518558532579186725327998413746026361518297 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.kmac_smoke.7759060491509504519784706457633821518558532579186725327998413746026361518297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.111527718901056775327204965482816954440115748714933319679882652781806172949810
Short name T45
Test name
Test status
Simulation time 47207151869 ps
CPU time 903.29 seconds
Started Nov 22 02:05:52 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 339824 kb
Host smart-e5babbb7-5708-4f20-93d5-711dcc3dc81e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=111527718901056775327204965482816954440115748714933319679882652781806172949810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_s
tress_all.111527718901056775327204965482816954440115748714933319679882652781806172949810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.112928368775875541160979395028218990557256070656878218727373926462125302705837
Short name T131
Test name
Test status
Simulation time 322955517 ps
CPU time 6.03 seconds
Started Nov 22 02:06:05 PM PST 23
Finished Nov 22 02:06:11 PM PST 23
Peak memory 219312 kb
Host smart-e8274a27-8115-4a71-b2ac-c256ebb1b6b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292836877587554116097939502821899055725607065687821
8727373926462125302705837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac.1129283687758755411609793950282189905
57256070656878218727373926462125302705837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.35242317779828761578496056885573862530718311447466939434023811228225404294725
Short name T428
Test name
Test status
Simulation time 309259198 ps
CPU time 6.06 seconds
Started Nov 22 02:05:51 PM PST 23
Finished Nov 22 02:05:58 PM PST 23
Peak memory 219268 kb
Host smart-69b5bb13-4ad3-45e2-9865-81974e2347e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35242317779828761578496056885573862530718311447466939
434023811228225404294725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.352423177798287615784960568855
73862530718311447466939434023811228225404294725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.109090495465005448128407275096341176523780674981541856290822732022806922420310
Short name T534
Test name
Test status
Simulation time 117329894454 ps
CPU time 2065.8 seconds
Started Nov 22 02:05:13 PM PST 23
Finished Nov 22 02:39:40 PM PST 23
Peak memory 400848 kb
Host smart-cc3e0516-6326-46f4-b063-00eb7151b0d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=109090495465005448128407275096341176523780674981541856290822732022806922420310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.kmac_test_vectors_sha3_224.109090495465005448128407275096341176523780674981541856290822732022806922420310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.42038463594407359836210471645658631545802205118456437900710963228927413302560
Short name T386
Test name
Test status
Simulation time 106843317633 ps
CPU time 1838.66 seconds
Started Nov 22 02:05:18 PM PST 23
Finished Nov 22 02:35:57 PM PST 23
Peak memory 376488 kb
Host smart-c2b91adc-7564-4a6f-b451-0696afb4e318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42038463594407359836210471645658631545802205118456437900710963228927413302560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_256.42038463594407359836210471645658631545802205118456437900710963228927413302560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.15180904739157806370833902216085438555126915926515099902918828818592019647664
Short name T914
Test name
Test status
Simulation time 83520343504 ps
CPU time 1569.81 seconds
Started Nov 22 02:05:11 PM PST 23
Finished Nov 22 02:31:22 PM PST 23
Peak memory 338460 kb
Host smart-bc830ed5-7bdd-4116-a4dc-7104e7ef1bcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=15180904739157806370833902216085438555126915926515099902918828818592019647664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_384.15180904739157806370833902216085438555126915926515099902918828818592019647664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.7397341304118344428535377562689703969406845972474166566843777451449076674112
Short name T576
Test name
Test status
Simulation time 57499426673 ps
CPU time 1216.3 seconds
Started Nov 22 02:05:12 PM PST 23
Finished Nov 22 02:25:29 PM PST 23
Peak memory 297744 kb
Host smart-88fa5483-7837-47b9-b920-9cf3763f6278
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=7397341304118344428535377562689703969406845972474166566843777451449076674112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
kmac_test_vectors_sha3_512.7397341304118344428535377562689703969406845972474166566843777451449076674112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.41949749908526779554825177631794202993658473936470478682008385643516662308175
Short name T438
Test name
Test status
Simulation time 320694338954 ps
CPU time 5531.93 seconds
Started Nov 22 02:05:14 PM PST 23
Finished Nov 22 03:37:27 PM PST 23
Peak memory 674320 kb
Host smart-8bfbd6df-5c82-4767-9815-19658cc2bb04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=41949749908526779554825177631794202993658473936470478682008385643516662308175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.kmac_test_vectors_shake_128.41949749908526779554825177631794202993658473936470478682008385643516662308175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.70976435854341446144682484994953265820517423558206942203676681734107907316714
Short name T670
Test name
Test status
Simulation time 270085708112 ps
CPU time 4707.55 seconds
Started Nov 22 02:06:06 PM PST 23
Finished Nov 22 03:24:35 PM PST 23
Peak memory 577396 kb
Host smart-66100c52-7a8a-47c4-b980-9133a70e7703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=70976435854341446144682484994953265820517423558206942203676681734107907316714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.kmac_test_vectors_shake_256.70976435854341446144682484994953265820517423558206942203676681734107907316714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.55299603055984900077089423858403476628534892222563235554602507759756276298855
Short name T479
Test name
Test status
Simulation time 21118646 ps
CPU time 0.8 seconds
Started Nov 22 02:05:51 PM PST 23
Finished Nov 22 02:05:52 PM PST 23
Peak memory 218964 kb
Host smart-0d32a1b8-ebe2-4a7f-8ae5-293d56f5b58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55299603055984900077089423858403476628534892222563235554602507759756276298855 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.kmac_alert_test.55299603055984900077089423858403476628534892222563235554602507759756276298855 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.64121803936208181234024448183991590152233827072735604327428636557238849775260
Short name T277
Test name
Test status
Simulation time 6076748772 ps
CPU time 105.71 seconds
Started Nov 22 02:06:00 PM PST 23
Finished Nov 22 02:07:46 PM PST 23
Peak memory 236136 kb
Host smart-0909e7af-f691-47a3-97e1-6fe71e7430c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64121803936208181234024448183991590152233827072735604327428636557238849775260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.kmac_app.64121803936208181234024448183991590152233827072735604327428636557238849775260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.59913976186274742502549599584478431929370263928967827770457725963275222100899
Short name T1031
Test name
Test status
Simulation time 14830000174 ps
CPU time 406.36 seconds
Started Nov 22 02:05:56 PM PST 23
Finished Nov 22 02:12:43 PM PST 23
Peak memory 243256 kb
Host smart-2f9b157a-c0e2-49bf-8d0f-76615b1edbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59913976186274742502549599584478431929370263928967827770457725963275222100899 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.kmac_burst_write.59913976186274742502549599584478431929370263928967827770457725963275222100899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.57875362509892085587108262976541052271994315620509716545250790388910235543604
Short name T350
Test name
Test status
Simulation time 7238810904 ps
CPU time 108.15 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:07:44 PM PST 23
Peak memory 243848 kb
Host smart-993f2d9f-fb12-4f54-a71e-9eec07ca215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57875362509892085587108262976541052271994315620509716545250790388910235543604 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.kmac_entropy_refresh.57875362509892085587108262976541052271994315620509716545250790388910235543604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.64033993503442210926035021741288839867470936251816907736229533454280861305746
Short name T816
Test name
Test status
Simulation time 8137821569 ps
CPU time 152.12 seconds
Started Nov 22 02:05:52 PM PST 23
Finished Nov 22 02:08:25 PM PST 23
Peak memory 252724 kb
Host smart-e5fac8a6-b4cb-45c2-85fd-e6b7d9056c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64033993503442210926035021741288839867470936251816907736229533454280861305746 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.kmac_error.64033993503442210926035021741288839867470936251816907736229533454280861305746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.25330819275785988932176420985871681867483571187380488572897863062736855835809
Short name T54
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.77 seconds
Started Nov 22 02:06:06 PM PST 23
Finished Nov 22 02:06:13 PM PST 23
Peak memory 219228 kb
Host smart-d30e6204-7d85-4ff2-839b-c5615c6ef610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25330819275785988932176420985871681867483571187380488572897863062736855835809 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.kmac_key_error.25330819275785988932176420985871681867483571187380488572897863062736855835809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.80200310535794889379218229431600561439813433578199156193992631186490200072125
Short name T567
Test name
Test status
Simulation time 72761090 ps
CPU time 1.53 seconds
Started Nov 22 02:05:53 PM PST 23
Finished Nov 22 02:05:55 PM PST 23
Peak memory 220436 kb
Host smart-f347c5a6-7b0d-4da7-8686-0e1912bfeb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80200310535794889379218229431600561439813433578199156193992631186490200072125 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.kmac_lc_escalation.80200310535794889379218229431600561439813433578199156193992631186490200072125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.84004000016792751700837301076553162800029693791322288972135460115385105114525
Short name T513
Test name
Test status
Simulation time 50513696845 ps
CPU time 1015.85 seconds
Started Nov 22 02:05:52 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 306348 kb
Host smart-19bbbbd5-4dfd-4809-92a7-81b696a72004
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84004000016792751700837301076553162800029693791322288972135460115385105114525 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.840040000167927517008373010765531628000296937913222889721354601153851
05114525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.51071594606590759267616834859692522216856357165067356467882436361433395394287
Short name T265
Test name
Test status
Simulation time 7628111361 ps
CPU time 133.81 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:08:09 PM PST 23
Peak memory 236368 kb
Host smart-acf8ec7f-5f23-4bfc-9df8-dad30cde2441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51071594606590759267616834859692522216856357165067356467882436361433395394287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.kmac_sideload.51071594606590759267616834859692522216856357165067356467882436361433395394287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.84799893013717739424336020360539885503249957436008479727082376903799669833819
Short name T844
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.53 seconds
Started Nov 22 02:05:44 PM PST 23
Finished Nov 22 02:06:12 PM PST 23
Peak memory 225404 kb
Host smart-70dbd86a-363e-4aa1-a7fb-efbee70cc12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84799893013717739424336020360539885503249957436008479727082376903799669833819 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.kmac_smoke.84799893013717739424336020360539885503249957436008479727082376903799669833819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.76979066951516638038884464731175096789937622341120499339265044990593862888401
Short name T666
Test name
Test status
Simulation time 47207151869 ps
CPU time 924.6 seconds
Started Nov 22 02:05:52 PM PST 23
Finished Nov 22 02:21:17 PM PST 23
Peak memory 339804 kb
Host smart-cb627ed3-649e-4ef1-8f01-6674b3e5ba9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=76979066951516638038884464731175096789937622341120499339265044990593862888401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_st
ress_all.76979066951516638038884464731175096789937622341120499339265044990593862888401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.81810499280991609108432013235055593644231773427111032618121430927628299992203
Short name T420
Test name
Test status
Simulation time 322955517 ps
CPU time 6.24 seconds
Started Nov 22 02:06:06 PM PST 23
Finished Nov 22 02:06:13 PM PST 23
Peak memory 219268 kb
Host smart-719bfa75-a589-407a-9636-7831272ad845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81810499280991609108432013235055593644231773427111032
618121430927628299992203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac.81810499280991609108432013235055593644
231773427111032618121430927628299992203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.5904625666225461946694753877466964296252517192988719119344773254837509055387
Short name T229
Test name
Test status
Simulation time 309259198 ps
CPU time 6.18 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:06:02 PM PST 23
Peak memory 219260 kb
Host smart-d68a8124-2875-4f7a-aeae-b64adeb1bf9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59046256662254619466947538774669642962525171929887191
19344773254837509055387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.5904625666225461946694753877466
964296252517192988719119344773254837509055387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.19698012472276494439128466646204971840278189552834448331970638266949044637246
Short name T859
Test name
Test status
Simulation time 117329894454 ps
CPU time 2161.04 seconds
Started Nov 22 02:05:53 PM PST 23
Finished Nov 22 02:41:54 PM PST 23
Peak memory 400816 kb
Host smart-194902ef-81ea-4ffc-b753-3c4d730f3635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=19698012472276494439128466646204971840278189552834448331970638266949044637246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_224.19698012472276494439128466646204971840278189552834448331970638266949044637246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.71639917343508885575183188710875588872808442193910383964517466649177808958894
Short name T593
Test name
Test status
Simulation time 106843317633 ps
CPU time 1854.8 seconds
Started Nov 22 02:05:58 PM PST 23
Finished Nov 22 02:36:53 PM PST 23
Peak memory 376408 kb
Host smart-2cb96f68-e993-49d1-8c5e-b16b361eebb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=71639917343508885575183188710875588872808442193910383964517466649177808958894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_256.71639917343508885575183188710875588872808442193910383964517466649177808958894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.91824114449880415160978367746782620097638952149845025349000011735203030438124
Short name T278
Test name
Test status
Simulation time 83520343504 ps
CPU time 1609.12 seconds
Started Nov 22 02:05:53 PM PST 23
Finished Nov 22 02:32:43 PM PST 23
Peak memory 338348 kb
Host smart-0742e8e2-8b50-49e7-a974-f5a1b4037792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91824114449880415160978367746782620097638952149845025349000011735203030438124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_384.91824114449880415160978367746782620097638952149845025349000011735203030438124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.17257545128637075016392180851449894824245939228555875845699354999244055414537
Short name T298
Test name
Test status
Simulation time 57499426673 ps
CPU time 1149.09 seconds
Started Nov 22 02:05:55 PM PST 23
Finished Nov 22 02:25:05 PM PST 23
Peak memory 297752 kb
Host smart-b6b37f6a-439d-4ac9-9e51-72edd2e4e460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17257545128637075016392180851449894824245939228555875845699354999244055414537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_512.17257545128637075016392180851449894824245939228555875845699354999244055414537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.26979225795816982231121740589491526511592969699818485756623500176208669238325
Short name T147
Test name
Test status
Simulation time 320694338954 ps
CPU time 5453.65 seconds
Started Nov 22 02:05:51 PM PST 23
Finished Nov 22 03:36:46 PM PST 23
Peak memory 674268 kb
Host smart-6f818f59-d479-475a-9dbc-88513c1ef7d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=26979225795816982231121740589491526511592969699818485756623500176208669238325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.kmac_test_vectors_shake_128.26979225795816982231121740589491526511592969699818485756623500176208669238325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.64998530932337278799271241327901479971236366787733451773597684238752804550269
Short name T467
Test name
Test status
Simulation time 270085708112 ps
CPU time 4466.36 seconds
Started Nov 22 02:06:21 PM PST 23
Finished Nov 22 03:20:49 PM PST 23
Peak memory 577340 kb
Host smart-1bfd9803-c116-4dfb-938a-421bbefd25d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=64998530932337278799271241327901479971236366787733451773597684238752804550269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.kmac_test_vectors_shake_256.64998530932337278799271241327901479971236366787733451773597684238752804550269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.22168650215156433336980492036193816049393992412661709563363624644196855607269
Short name T177
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 02:02:03 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 218948 kb
Host smart-8581f588-f7d2-4388-ae77-426af3db30c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168650215156433336980492036193816049393992412661709563363624644196855607269 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.kmac_alert_test.22168650215156433336980492036193816049393992412661709563363624644196855607269 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.9457231432910078752065535135996052154981737794405607342039589017252169383103
Short name T813
Test name
Test status
Simulation time 6076748772 ps
CPU time 96.79 seconds
Started Nov 22 02:01:57 PM PST 23
Finished Nov 22 02:04:01 PM PST 23
Peak memory 236012 kb
Host smart-111dee85-7aa2-42b2-a49b-83ffba761953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9457231432910078752065535135996052154981737794405607342039589017252169383103 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.kmac_app.9457231432910078752065535135996052154981737794405607342039589017252169383103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.23473608059074627178741541104982075040846706699518534015065224265271754366641
Short name T932
Test name
Test status
Simulation time 7277596308 ps
CPU time 108.01 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 243856 kb
Host smart-36611793-dd02-4f4c-99cf-af4462ce264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23473608059074627178741541104982075040846706699518534015065224265271754366641 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_app_with_partial_data.23473608059074627178741541104982075040846706699518534015065224265271754366641 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.77671552633856307076968379117636265138488636906328990836626898968326673439841
Short name T50
Test name
Test status
Simulation time 14830000174 ps
CPU time 390.36 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 02:07:50 PM PST 23
Peak memory 243244 kb
Host smart-363bc938-e7bf-4276-930a-c3af4a0f301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77671552633856307076968379117636265138488636906328990836626898968326673439841 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.kmac_burst_write.77671552633856307076968379117636265138488636906328990836626898968326673439841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.93111850507545649105501450629064679752574978822940635716108846563153563293300
Short name T1074
Test name
Test status
Simulation time 62261174 ps
CPU time 1.25 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 218980 kb
Host smart-02f881ad-b33e-42e3-9e28-5d62a2c15a75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93111850507545649105501450629064679752574978822940635716108846563153563293300 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.kmac_edn_timeout_error.93111850507545649105501450629064679752574978822940635716108846563153563293300 +enable_masking=1
+sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.34728032690775335247252486343329661806234258261144204881688291747543472287
Short name T778
Test name
Test status
Simulation time 64850439 ps
CPU time 1.28 seconds
Started Nov 22 02:02:02 PM PST 23
Finished Nov 22 02:02:26 PM PST 23
Peak memory 218940 kb
Host smart-304b657f-09ea-4522-8f36-8fdcf532ec44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=34728032690775335247252486343329661806234258261144204881688291747543472287 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.kmac_entropy_mode_error.34728032690775335247252486343329661806234258261144204881688291747543472287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.84612004000894521464971511178792068578100795356106552866280698442250149382572
Short name T536
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.27 seconds
Started Nov 22 02:02:37 PM PST 23
Finished Nov 22 02:03:12 PM PST 23
Peak memory 219336 kb
Host smart-c0b2a56d-8700-4b64-948a-250c091c7fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84612004000894521464971511178792068578100795356106552866280698442250149382572 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.kmac_entropy_ready_error.84612004000894521464971511178792068578100795356106552866280698442250149382572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.49309680153186722561875836765115231277475462600778274047153157960457109454607
Short name T958
Test name
Test status
Simulation time 7238810904 ps
CPU time 112.93 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 02:03:29 PM PST 23
Peak memory 243940 kb
Host smart-8b6b5cd4-ce47-4e6f-bc4d-3d46429df54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49309680153186722561875836765115231277475462600778274047153157960457109454607 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.kmac_entropy_refresh.49309680153186722561875836765115231277475462600778274047153157960457109454607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.86122111421369857298479146061901406808208292896193520360240265552312442258946
Short name T498
Test name
Test status
Simulation time 8137821569 ps
CPU time 146.69 seconds
Started Nov 22 02:01:54 PM PST 23
Finished Nov 22 02:04:21 PM PST 23
Peak memory 252788 kb
Host smart-a795f020-a7fc-43eb-ac20-8b981dbece2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86122111421369857298479146061901406808208292896193520360240265552312442258946 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.kmac_error.86122111421369857298479146061901406808208292896193520360240265552312442258946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.96862672361989903573710221596887045318654942724458222619624455589253571765802
Short name T518
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.77 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:01:43 PM PST 23
Peak memory 219140 kb
Host smart-eafb142a-2e6f-479d-89f6-be2a75776417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96862672361989903573710221596887045318654942724458222619624455589253571765802 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.kmac_key_error.96862672361989903573710221596887045318654942724458222619624455589253571765802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.111913144307888714998324439879248765054687102027890328444270630344710238396598
Short name T565
Test name
Test status
Simulation time 72761090 ps
CPU time 1.46 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 220500 kb
Host smart-b1182e46-55b7-4766-800f-e2350e6bc394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111913144307888714998324439879248765054687102027890328444270630344710238396598 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.kmac_lc_escalation.111913144307888714998324439879248765054687102027890328444270630344710238396598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.58714214288591456964104965472433066959403054035617626486842122249496835277207
Short name T410
Test name
Test status
Simulation time 50513696845 ps
CPU time 977.59 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:17:54 PM PST 23
Peak memory 306280 kb
Host smart-17befbac-ffab-4191-a056-529e8ed56866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58714214288591456964104965472433066959403054035617626486842122249496835277207 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.5871421428859145696410496547243306695940305403561762648684212224949683
5277207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.103867033618211235438667601686325050385493953111183811029953447236860650432828
Short name T649
Test name
Test status
Simulation time 7712378544 ps
CPU time 136.2 seconds
Started Nov 22 02:01:41 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 244008 kb
Host smart-2c3900f9-1003-4855-81d4-78038d2e1ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103867033618211235438667601686325050385493953111183811029953447236860650432828 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.kmac_mubi.103867033618211235438667601686325050385493953111183811029953447236860650432828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.50191927316328191752324053709290555875915488799800071228795652866402302082719
Short name T990
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.38 seconds
Started Nov 22 02:02:02 PM PST 23
Finished Nov 22 02:04:42 PM PST 23
Peak memory 236300 kb
Host smart-5ce35152-f739-4533-adba-e8cf0513ed9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50191927316328191752324053709290555875915488799800071228795652866402302082719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.kmac_sideload.50191927316328191752324053709290555875915488799800071228795652866402302082719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.19639504886130804930157181729899286719685332866204547216994287690325619184734
Short name T166
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.53 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:02:04 PM PST 23
Peak memory 225404 kb
Host smart-2113fcd3-25d9-4787-ae69-858591ee6b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19639504886130804930157181729899286719685332866204547216994287690325619184734 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.kmac_smoke.19639504886130804930157181729899286719685332866204547216994287690325619184734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.238456790570259424865664633903109656712674162261885032873504443965563567489
Short name T299
Test name
Test status
Simulation time 47207151869 ps
CPU time 855.96 seconds
Started Nov 22 02:01:17 PM PST 23
Finished Nov 22 02:15:34 PM PST 23
Peak memory 339800 kb
Host smart-e8436241-92db-49ee-bb35-78f6fe9eb2f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=238456790570259424865664633903109656712674162261885032873504443965563567489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=
kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stres
s_all.238456790570259424865664633903109656712674162261885032873504443965563567489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.67529573180355772244149875720724837092043447576240956165892199033271953151385
Short name T246
Test name
Test status
Simulation time 322955517 ps
CPU time 6 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 219256 kb
Host smart-2532aa8c-2cab-4ba8-93fb-9d6ffdcd1344
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67529573180355772244149875720724837092043447576240956
165892199033271953151385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac.675295731803557722441498757207248370920
43447576240956165892199033271953151385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.32656607166184350343565738903463685716034844111956208999174385121868427693328
Short name T868
Test name
Test status
Simulation time 309259198 ps
CPU time 5.51 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 219188 kb
Host smart-cd125e83-9dbf-4007-becc-f50b4f9dcc4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656607166184350343565738903463685716034844111956208
999174385121868427693328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3265660716618435034356573890346
3685716034844111956208999174385121868427693328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.51193585292380575999726241519761102547398661857555180484197315832537026024067
Short name T23
Test name
Test status
Simulation time 117329894454 ps
CPU time 2095.45 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:36:17 PM PST 23
Peak memory 400836 kb
Host smart-f8a67980-f7f1-4b44-9c07-e799216946b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=51193585292380575999726241519761102547398661857555180484197315832537026024067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_224.51193585292380575999726241519761102547398661857555180484197315832537026024067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.19813677881126677913576900814297713883253124883408226118305139539415309230035
Short name T367
Test name
Test status
Simulation time 106843317633 ps
CPU time 1947.87 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:33:47 PM PST 23
Peak memory 376372 kb
Host smart-b8f51e2c-afef-4350-813a-d0801825c965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=19813677881126677913576900814297713883253124883408226118305139539415309230035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_256.19813677881126677913576900814297713883253124883408226118305139539415309230035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.13651458561798914210001910456788474208976273161658475902452177772505952130325
Short name T835
Test name
Test status
Simulation time 83520343504 ps
CPU time 1553.35 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:27:25 PM PST 23
Peak memory 338472 kb
Host smart-2b46cf83-11e9-4a47-8b02-e2dc8781653c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=13651458561798914210001910456788474208976273161658475902452177772505952130325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_384.13651458561798914210001910456788474208976273161658475902452177772505952130325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.83588452121806798206021197985038040722965216081740496850198293334545197807801
Short name T174
Test name
Test status
Simulation time 57499426673 ps
CPU time 1240.1 seconds
Started Nov 22 02:01:40 PM PST 23
Finished Nov 22 02:22:21 PM PST 23
Peak memory 297772 kb
Host smart-0451dff2-7764-4fb1-a256-fe4edb6f5e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83588452121806798206021197985038040722965216081740496850198293334545197807801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_512.83588452121806798206021197985038040722965216081740496850198293334545197807801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.7199030127060866870547024169869791540902307637115775589354993731314188582146
Short name T805
Test name
Test status
Simulation time 320694338954 ps
CPU time 5359.28 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 03:30:54 PM PST 23
Peak memory 672932 kb
Host smart-77f74a70-4bd9-4f70-81b8-1fb0ff299ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=7199030127060866870547024169869791540902307637115775589354993731314188582146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.kmac_test_vectors_shake_128.7199030127060866870547024169869791540902307637115775589354993731314188582146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.2709067641713448529105813619133505000475363583535887449398875485273505628632
Short name T133
Test name
Test status
Simulation time 270085708112 ps
CPU time 4433.39 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 03:15:30 PM PST 23
Peak memory 577112 kb
Host smart-1de3fac1-2492-490b-8fa7-4b2fce1eccd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2709067641713448529105813619133505000475363583535887449398875485273505628632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.kmac_test_vectors_shake_256.2709067641713448529105813619133505000475363583535887449398875485273505628632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.30074490261894726250275848073757250834722541106938062626459468028807801371963
Short name T505
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:01:13 PM PST 23
Finished Nov 22 02:01:15 PM PST 23
Peak memory 218932 kb
Host smart-4bd58893-4ff1-4794-a032-3c6cbd275ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30074490261894726250275848073757250834722541106938062626459468028807801371963 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.kmac_alert_test.30074490261894726250275848073757250834722541106938062626459468028807801371963 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.50625860226508634533027717690282425387944377256727884490013871210433062549890
Short name T973
Test name
Test status
Simulation time 6076748772 ps
CPU time 100.34 seconds
Started Nov 22 02:00:49 PM PST 23
Finished Nov 22 02:02:30 PM PST 23
Peak memory 236240 kb
Host smart-1dc2ac53-d95d-4db3-a5d3-4abc8d31562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50625860226508634533027717690282425387944377256727884490013871210433062549890 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_app.50625860226508634533027717690282425387944377256727884490013871210433062549890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.62606637256189536176960383979052304445482962826475480561695402290108339547237
Short name T600
Test name
Test status
Simulation time 7277596308 ps
CPU time 112.59 seconds
Started Nov 22 02:01:16 PM PST 23
Finished Nov 22 02:03:10 PM PST 23
Peak memory 243860 kb
Host smart-f6710b23-86d1-4341-9a20-70cdf8456c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62606637256189536176960383979052304445482962826475480561695402290108339547237 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_app_with_partial_data.62606637256189536176960383979052304445482962826475480561695402290108339547237 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.92129645253273107453210942781943232110928960553242365316407679759159628204835
Short name T696
Test name
Test status
Simulation time 14830000174 ps
CPU time 382.13 seconds
Started Nov 22 02:01:03 PM PST 23
Finished Nov 22 02:07:26 PM PST 23
Peak memory 243296 kb
Host smart-b5a32ca3-f04d-479e-aeed-d0115f088c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92129645253273107453210942781943232110928960553242365316407679759159628204835 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.kmac_burst_write.92129645253273107453210942781943232110928960553242365316407679759159628204835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.36003644922817171521407731428470431037578561061994790416365294552274568093422
Short name T785
Test name
Test status
Simulation time 62261174 ps
CPU time 1.27 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:01:22 PM PST 23
Peak memory 219088 kb
Host smart-33272a20-c85e-4a31-a430-f26b03f4e830
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=36003644922817171521407731428470431037578561061994790416365294552274568093422 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.kmac_edn_timeout_error.36003644922817171521407731428470431037578561061994790416365294552274568093422 +enable_masking=1
+sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.46334191535408665469896296293769588776306863679286220033036024727274871919798
Short name T36
Test name
Test status
Simulation time 64850439 ps
CPU time 1.27 seconds
Started Nov 22 02:00:50 PM PST 23
Finished Nov 22 02:00:52 PM PST 23
Peak memory 219084 kb
Host smart-a088f66f-65fc-47b3-a596-1a9777bc32fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=46334191535408665469896296293769588776306863679286220033036024727274871919798 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.46334191535408665469896296293769588776306863679286220033036024727274871919798 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.55245320162510480888466642275589407789075888855521358140888875742841098477221
Short name T58
Test name
Test status
Simulation time 3179093382 ps
CPU time 21.7 seconds
Started Nov 22 02:01:04 PM PST 23
Finished Nov 22 02:01:26 PM PST 23
Peak memory 219284 kb
Host smart-b2b1d5c1-1545-4855-a655-c912e26aec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55245320162510480888466642275589407789075888855521358140888875742841098477221 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.kmac_entropy_ready_error.55245320162510480888466642275589407789075888855521358140888875742841098477221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.24544244472944266373126922444520807261509217924983986199826017291870450820558
Short name T60
Test name
Test status
Simulation time 7238810904 ps
CPU time 112.14 seconds
Started Nov 22 02:01:15 PM PST 23
Finished Nov 22 02:03:09 PM PST 23
Peak memory 243936 kb
Host smart-e26eb269-de55-42c8-91ed-eef183e4dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24544244472944266373126922444520807261509217924983986199826017291870450820558 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.kmac_entropy_refresh.24544244472944266373126922444520807261509217924983986199826017291870450820558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.78619093158392808320373251885055335603432214191970690506800206818866837420856
Short name T179
Test name
Test status
Simulation time 8137821569 ps
CPU time 146.57 seconds
Started Nov 22 02:02:27 PM PST 23
Finished Nov 22 02:05:00 PM PST 23
Peak memory 252760 kb
Host smart-8854ba08-47c7-4949-9a83-b106971c0138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78619093158392808320373251885055335603432214191970690506800206818866837420856 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.kmac_error.78619093158392808320373251885055335603432214191970690506800206818866837420856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.16453314416684139953549780848644070661257478632941639105190756780272107779438
Short name T737
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.76 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:01:28 PM PST 23
Peak memory 219248 kb
Host smart-de2d08e6-f1f2-4da0-bfe1-b8b8c4e8e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16453314416684139953549780848644070661257478632941639105190756780272107779438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.kmac_key_error.16453314416684139953549780848644070661257478632941639105190756780272107779438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.53517782169977533162709949397036957485235443736862138682714099240838438589683
Short name T359
Test name
Test status
Simulation time 72761090 ps
CPU time 1.65 seconds
Started Nov 22 02:01:19 PM PST 23
Finished Nov 22 02:01:22 PM PST 23
Peak memory 220292 kb
Host smart-ec42a972-f09c-4306-acb4-ce5cc56490d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53517782169977533162709949397036957485235443736862138682714099240838438589683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.kmac_lc_escalation.53517782169977533162709949397036957485235443736862138682714099240838438589683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.25280792451487765744362757643111127870609757629859024878191531918765316014387
Short name T435
Test name
Test status
Simulation time 50513696845 ps
CPU time 984.76 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:17:11 PM PST 23
Peak memory 306212 kb
Host smart-90d35b9e-4321-4900-9a70-4259a893ab63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25280792451487765744362757643111127870609757629859024878191531918765316014387 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2528079245148776574436275764311112787060975762985902487819153191876531
6014387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.59302826861439788760549856541461622403277450381489685321722337832582655916051
Short name T1028
Test name
Test status
Simulation time 7712378544 ps
CPU time 134.14 seconds
Started Nov 22 02:01:04 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 244088 kb
Host smart-2345c35f-136d-479a-aba0-ae758116e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59302826861439788760549856541461622403277450381489685321722337832582655916051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.kmac_mubi.59302826861439788760549856541461622403277450381489685321722337832582655916051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.55962279194567352542142040767280083725443759636521691439094797272895055755590
Short name T1058
Test name
Test status
Simulation time 7628111361 ps
CPU time 132.03 seconds
Started Nov 22 02:00:43 PM PST 23
Finished Nov 22 02:02:55 PM PST 23
Peak memory 236140 kb
Host smart-c5edcec1-bc01-4238-9d7f-a5884a00527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55962279194567352542142040767280083725443759636521691439094797272895055755590 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.kmac_sideload.55962279194567352542142040767280083725443759636521691439094797272895055755590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.12685473017300968659727477931725704941258597129764721410684779346553119478795
Short name T547
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.87 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:01:28 PM PST 23
Peak memory 225384 kb
Host smart-0aaa9f3b-233a-49e8-a3c2-e2cb9e70c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12685473017300968659727477931725704941258597129764721410684779346553119478795 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.kmac_smoke.12685473017300968659727477931725704941258597129764721410684779346553119478795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.335236305313623184568685812605173039478102974532657601437551141910571309303
Short name T37
Test name
Test status
Simulation time 47207151869 ps
CPU time 935.3 seconds
Started Nov 22 02:01:15 PM PST 23
Finished Nov 22 02:16:52 PM PST 23
Peak memory 339832 kb
Host smart-1e4ac4f8-96da-48d6-9a00-9dd8e19e37be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=335236305313623184568685812605173039478102974532657601437551141910571309303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=
kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stres
s_all.335236305313623184568685812605173039478102974532657601437551141910571309303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.31704927331813563495314793227715201867372991395686480676449902207092018251708
Short name T763
Test name
Test status
Simulation time 322955517 ps
CPU time 5.72 seconds
Started Nov 22 02:00:47 PM PST 23
Finished Nov 22 02:00:54 PM PST 23
Peak memory 219284 kb
Host smart-34266564-810f-4a47-9d70-f24503645b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704927331813563495314793227715201867372991395686480
676449902207092018251708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac.317049273318135634953147932277152018673
72991395686480676449902207092018251708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.51852305330250882305496165532868679811461026351205383433005368500894171372038
Short name T153
Test name
Test status
Simulation time 309259198 ps
CPU time 5.61 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 02:01:08 PM PST 23
Peak memory 219236 kb
Host smart-92c57f04-4c49-4bf0-a29f-69f094adc1d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51852305330250882305496165532868679811461026351205383
433005368500894171372038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.5185230533025088230549616553286
8679811461026351205383433005368500894171372038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.16958839800061327027105009051487021397735494740623693341319362865352588473317
Short name T774
Test name
Test status
Simulation time 117329894454 ps
CPU time 2195.09 seconds
Started Nov 22 02:00:43 PM PST 23
Finished Nov 22 02:37:19 PM PST 23
Peak memory 400872 kb
Host smart-2c91917e-f906-4bac-9a2f-f9b68b0ed926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16958839800061327027105009051487021397735494740623693341319362865352588473317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
kmac_test_vectors_sha3_224.16958839800061327027105009051487021397735494740623693341319362865352588473317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.9464854770127573033212485373162814606815865438143428381374998137420999240433
Short name T388
Test name
Test status
Simulation time 106843317633 ps
CPU time 1933.42 seconds
Started Nov 22 02:00:46 PM PST 23
Finished Nov 22 02:33:00 PM PST 23
Peak memory 376400 kb
Host smart-19cd2261-df7a-41d5-b4bf-1289fc5c0ade
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=9464854770127573033212485373162814606815865438143428381374998137420999240433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.k
mac_test_vectors_sha3_256.9464854770127573033212485373162814606815865438143428381374998137420999240433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.102392417074565267184854073577388629005041220796300484917783743823254125839736
Short name T373
Test name
Test status
Simulation time 83520343504 ps
CPU time 1550.91 seconds
Started Nov 22 02:00:49 PM PST 23
Finished Nov 22 02:26:41 PM PST 23
Peak memory 338448 kb
Host smart-1eaae7e2-aa0a-4840-8fd3-150a0487697f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=102392417074565267184854073577388629005041220796300484917783743823254125839736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.kmac_test_vectors_sha3_384.102392417074565267184854073577388629005041220796300484917783743823254125839736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.114345249155044903483810848874440083207120556114708726110129132319783766888766
Short name T1018
Test name
Test status
Simulation time 57499426673 ps
CPU time 1256.57 seconds
Started Nov 22 02:00:44 PM PST 23
Finished Nov 22 02:21:41 PM PST 23
Peak memory 297780 kb
Host smart-50ae8ea8-4314-4ee2-a356-2c2dfebd3e75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114345249155044903483810848874440083207120556114708726110129132319783766888766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.kmac_test_vectors_sha3_512.114345249155044903483810848874440083207120556114708726110129132319783766888766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.22095072892903972200763597489675714651140046980140396717374499785618451070409
Short name T645
Test name
Test status
Simulation time 320694338954 ps
CPU time 5400.39 seconds
Started Nov 22 02:00:50 PM PST 23
Finished Nov 22 03:30:51 PM PST 23
Peak memory 674268 kb
Host smart-24c53901-6e3a-480d-968c-577cfd75f762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=22095072892903972200763597489675714651140046980140396717374499785618451070409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_test_vectors_shake_128.22095072892903972200763597489675714651140046980140396717374499785618451070409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.44614287468227355205726856527520984617387446701936065707749343318972599987462
Short name T1020
Test name
Test status
Simulation time 270085708112 ps
CPU time 4710.38 seconds
Started Nov 22 02:01:01 PM PST 23
Finished Nov 22 03:19:33 PM PST 23
Peak memory 577256 kb
Host smart-5af7b484-d3a3-47fe-ae78-36bc4937dcf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=44614287468227355205726856527520984617387446701936065707749343318972599987462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_test_vectors_shake_256.44614287468227355205726856527520984617387446701936065707749343318972599987462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.77220733703909395456543711996327202347945982454660982934989224303043166891367
Short name T589
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 02:01:38 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 219012 kb
Host smart-b0043a84-95b3-41ff-880b-b505663f07ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77220733703909395456543711996327202347945982454660982934989224303043166891367 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.kmac_alert_test.77220733703909395456543711996327202347945982454660982934989224303043166891367 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.27065178456544867232657515178640563609383092469177346955031554178937423248271
Short name T33
Test name
Test status
Simulation time 6076748772 ps
CPU time 99.86 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:03:14 PM PST 23
Peak memory 236272 kb
Host smart-1298fd61-58c8-4f56-bcb9-e8229b894316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27065178456544867232657515178640563609383092469177346955031554178937423248271 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.kmac_app.27065178456544867232657515178640563609383092469177346955031554178937423248271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.28521480870862900448143444436555034156078173529874366290113613875494723046927
Short name T274
Test name
Test status
Simulation time 7277596308 ps
CPU time 113.31 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:03:31 PM PST 23
Peak memory 243880 kb
Host smart-ea03d9e1-4984-4691-a31d-f71007055dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28521480870862900448143444436555034156078173529874366290113613875494723046927 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_app_with_partial_data.28521480870862900448143444436555034156078173529874366290113613875494723046927 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.89893737459373175689150623052229194938906223698722057567841393107076480434933
Short name T223
Test name
Test status
Simulation time 14830000174 ps
CPU time 371.93 seconds
Started Nov 22 02:01:14 PM PST 23
Finished Nov 22 02:07:26 PM PST 23
Peak memory 243348 kb
Host smart-30e130b4-97e2-41b0-9896-1521126850a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89893737459373175689150623052229194938906223698722057567841393107076480434933 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.kmac_burst_write.89893737459373175689150623052229194938906223698722057567841393107076480434933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.94664764373900200919023103847070706709692459006799604315810606800074088023943
Short name T632
Test name
Test status
Simulation time 62261174 ps
CPU time 1.32 seconds
Started Nov 22 02:01:53 PM PST 23
Finished Nov 22 02:01:55 PM PST 23
Peak memory 219084 kb
Host smart-2a9da6fb-e1a8-40cd-b3f4-50ac848e3523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=94664764373900200919023103847070706709692459006799604315810606800074088023943 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.kmac_edn_timeout_error.94664764373900200919023103847070706709692459006799604315810606800074088023943 +enable_masking=1
+sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.47360334888611918155313890868973262428314536907915685367539581801166152646116
Short name T676
Test name
Test status
Simulation time 64850439 ps
CPU time 1.22 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 218864 kb
Host smart-6037c9fa-ac6e-49e5-84c2-ec4dd6bc071a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47360334888611918155313890868973262428314536907915685367539581801166152646116 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.47360334888611918155313890868973262428314536907915685367539581801166152646116 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.112329203414360910258608493979648164758657192073011211351800450861231511046497
Short name T653
Test name
Test status
Simulation time 7238810904 ps
CPU time 112.88 seconds
Started Nov 22 02:01:37 PM PST 23
Finished Nov 22 02:03:30 PM PST 23
Peak memory 243796 kb
Host smart-98d548bb-c431-4259-9c50-c31c5a3521ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112329203414360910258608493979648164758657192073011211351800450861231511046497 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_entropy_refresh.112329203414360910258608493979648164758657192073011211351800450861231511046497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.22029238950640471588810865173174785977691735956387114019258063987588561064626
Short name T145
Test name
Test status
Simulation time 8137821569 ps
CPU time 144.55 seconds
Started Nov 22 02:02:08 PM PST 23
Finished Nov 22 02:04:49 PM PST 23
Peak memory 252768 kb
Host smart-9398a87b-9979-4c90-8919-fa2d517485fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22029238950640471588810865173174785977691735956387114019258063987588561064626 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.kmac_error.22029238950640471588810865173174785977691735956387114019258063987588561064626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.12964768439741018013878958587651206840317385048907672420259347175025646565175
Short name T241
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.62 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:41 PM PST 23
Peak memory 219232 kb
Host smart-8efe94e4-094e-49e8-8499-807dcdac5796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12964768439741018013878958587651206840317385048907672420259347175025646565175 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.kmac_key_error.12964768439741018013878958587651206840317385048907672420259347175025646565175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.92223579637756252903561313767563828277979888303943433798508099421875822144561
Short name T548
Test name
Test status
Simulation time 72761090 ps
CPU time 1.53 seconds
Started Nov 22 02:01:38 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 220504 kb
Host smart-93d4a9c3-fc97-4e60-b279-158ced91dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92223579637756252903561313767563828277979888303943433798508099421875822144561 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.kmac_lc_escalation.92223579637756252903561313767563828277979888303943433798508099421875822144561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.51224302043597669260871507127619697577984527592150212082454476396126766016869
Short name T49
Test name
Test status
Simulation time 50513696845 ps
CPU time 1039.03 seconds
Started Nov 22 02:01:17 PM PST 23
Finished Nov 22 02:18:37 PM PST 23
Peak memory 306360 kb
Host smart-b39d88c9-76a7-4fad-8e53-567c701e0d19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51224302043597669260871507127619697577984527592150212082454476396126766016869 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.5122430204359766926087150712761969757798452759215021208245447639612676
6016869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.30299704166788073382532646826816387248130820998748595638377599671460899182043
Short name T777
Test name
Test status
Simulation time 7712378544 ps
CPU time 140.97 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 244072 kb
Host smart-42303448-ae53-4be7-86dd-23d9bfe76d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30299704166788073382532646826816387248130820998748595638377599671460899182043 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.kmac_mubi.30299704166788073382532646826816387248130820998748595638377599671460899182043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.67170223819723729396954409618604485900737207515850787260737561317877873180388
Short name T262
Test name
Test status
Simulation time 7628111361 ps
CPU time 137.71 seconds
Started Nov 22 02:01:03 PM PST 23
Finished Nov 22 02:03:21 PM PST 23
Peak memory 236276 kb
Host smart-119fbba9-cabd-46e3-8392-07d67f30e51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67170223819723729396954409618604485900737207515850787260737561317877873180388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.kmac_sideload.67170223819723729396954409618604485900737207515850787260737561317877873180388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.56196769462290600319296003554189719154521700465823223272436832585106148075588
Short name T253
Test name
Test status
Simulation time 1925406983 ps
CPU time 25.74 seconds
Started Nov 22 02:02:25 PM PST 23
Finished Nov 22 02:02:58 PM PST 23
Peak memory 225404 kb
Host smart-a1d7782c-c80e-4643-9f20-b3ada3ff7a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56196769462290600319296003554189719154521700465823223272436832585106148075588 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.kmac_smoke.56196769462290600319296003554189719154521700465823223272436832585106148075588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.18272503929804797378547631649942589508999839116203610054577738863177788618066
Short name T307
Test name
Test status
Simulation time 47207151869 ps
CPU time 920.02 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:16:54 PM PST 23
Peak memory 339836 kb
Host smart-1884b324-ebdd-492c-ae7d-62ecd721642f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=18272503929804797378547631649942589508999839116203610054577738863177788618066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_str
ess_all.18272503929804797378547631649942589508999839116203610054577738863177788618066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.48915454438526420024593129014158478903269861452712996194932916467021579562199
Short name T500
Test name
Test status
Simulation time 322955517 ps
CPU time 5.96 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 219240 kb
Host smart-fefeedec-9282-4468-a8b7-52aa7eba676f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48915454438526420024593129014158478903269861452712996
194932916467021579562199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac.489154544385264200245931290141584789032
69861452712996194932916467021579562199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.106612540885875426219079047317439646825388248179826622175857572141309853958284
Short name T137
Test name
Test status
Simulation time 309259198 ps
CPU time 5.76 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 219292 kb
Host smart-6e8127f1-f2ec-47f2-921b-b1b32cb5cbeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661254088587542621907904731743964682538824817982662
2175857572141309853958284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.106612540885875426219079047317
439646825388248179826622175857572141309853958284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.62440642230183637460096142454342779436042637199397538517988100301452902538145
Short name T257
Test name
Test status
Simulation time 117329894454 ps
CPU time 2203.76 seconds
Started Nov 22 02:01:20 PM PST 23
Finished Nov 22 02:38:05 PM PST 23
Peak memory 400812 kb
Host smart-74cc0276-8783-42ff-a067-a7fc93b7aa8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=62440642230183637460096142454342779436042637199397538517988100301452902538145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_sha3_224.62440642230183637460096142454342779436042637199397538517988100301452902538145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.8490783769055445722511162316416015069668732217910324830685996154400532554026
Short name T991
Test name
Test status
Simulation time 106843317633 ps
CPU time 1865.07 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:32:23 PM PST 23
Peak memory 376316 kb
Host smart-04e3ac96-d6d8-4918-a7bf-446586a7164c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8490783769055445722511162316416015069668732217910324830685996154400532554026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.k
mac_test_vectors_sha3_256.8490783769055445722511162316416015069668732217910324830685996154400532554026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.40977801896795333964381188943509688804359533113192397819224983904127640033002
Short name T995
Test name
Test status
Simulation time 83520343504 ps
CPU time 1597.32 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:28:13 PM PST 23
Peak memory 338460 kb
Host smart-6f9c9e47-7f12-42b0-afe4-9783d12a4b2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=40977801896795333964381188943509688804359533113192397819224983904127640033002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_sha3_384.40977801896795333964381188943509688804359533113192397819224983904127640033002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.37964488507684033284335879881273665068982350333487745680111842015398693816464
Short name T922
Test name
Test status
Simulation time 57499426673 ps
CPU time 1094.5 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:19:48 PM PST 23
Peak memory 297796 kb
Host smart-4b63030a-45eb-4e2d-8029-a28e1694df66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=37964488507684033284335879881273665068982350333487745680111842015398693816464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_sha3_512.37964488507684033284335879881273665068982350333487745680111842015398693816464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.126836093189127054992813723212981465404604441074412368643834150252083401131
Short name T182
Test name
Test status
Simulation time 320694338954 ps
CPU time 5381.58 seconds
Started Nov 22 02:01:17 PM PST 23
Finished Nov 22 03:31:00 PM PST 23
Peak memory 672944 kb
Host smart-f42eda33-5a03-4685-85cc-64fb0a2ea0e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=126836093189127054992813723212981465404604441074412368643834150252083401131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_shake_128.126836093189127054992813723212981465404604441074412368643834150252083401131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.33980682420899505615905526884399491839517377661842804624917855654318239114971
Short name T294
Test name
Test status
Simulation time 270085708112 ps
CPU time 4556.64 seconds
Started Nov 22 02:01:57 PM PST 23
Finished Nov 22 03:18:21 PM PST 23
Peak memory 576992 kb
Host smart-a531ad64-ea22-45b5-87f8-3df3cbb08dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=33980682420899505615905526884399491839517377661842804624917855654318239114971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.kmac_test_vectors_shake_256.33980682420899505615905526884399491839517377661842804624917855654318239114971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.62481966064612169659277328249538282201380323627072442995643370280783297403047
Short name T185
Test name
Test status
Simulation time 21118646 ps
CPU time 0.81 seconds
Started Nov 22 02:01:14 PM PST 23
Finished Nov 22 02:01:15 PM PST 23
Peak memory 218972 kb
Host smart-0c4523b4-2a99-49f2-a247-ea4be2a373e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62481966064612169659277328249538282201380323627072442995643370280783297403047 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.kmac_alert_test.62481966064612169659277328249538282201380323627072442995643370280783297403047 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.112539513758318188191059030159906106044391487469209984649980030178127352970965
Short name T906
Test name
Test status
Simulation time 6076748772 ps
CPU time 101.06 seconds
Started Nov 22 02:02:33 PM PST 23
Finished Nov 22 02:04:19 PM PST 23
Peak memory 236240 kb
Host smart-377f310a-55cd-4ff3-b609-25fc4b2530eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112539513758318188191059030159906106044391487469209984649980030178127352970965 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.kmac_app.112539513758318188191059030159906106044391487469209984649980030178127352970965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.104175051644949831265763968705578309711993329382918443888405625524258455041905
Short name T312
Test name
Test status
Simulation time 7277596308 ps
CPU time 114.38 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 02:04:22 PM PST 23
Peak memory 243868 kb
Host smart-f5f223bb-7784-4f83-8924-4ca2e37c6edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104175051644949831265763968705578309711993329382918443888405625524258455041905 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_app_with_partial_data.104175051644949831265763968705578309711993329382918443888405625524258455041905 +enable_masking=1
+sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.35806735354853061162284478413895431201422178822534919341242947582708033628091
Short name T376
Test name
Test status
Simulation time 14830000174 ps
CPU time 397.71 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 02:08:25 PM PST 23
Peak memory 243284 kb
Host smart-5c30e6d4-d7a0-4115-abb0-db2c0f0aaca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35806735354853061162284478413895431201422178822534919341242947582708033628091 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.kmac_burst_write.35806735354853061162284478413895431201422178822534919341242947582708033628091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.75527562468466657916997805752254661371369908451637880403469889953259013217533
Short name T62
Test name
Test status
Simulation time 62261174 ps
CPU time 1.26 seconds
Started Nov 22 02:01:14 PM PST 23
Finished Nov 22 02:01:17 PM PST 23
Peak memory 219084 kb
Host smart-05d4c21c-2f01-41a6-969d-8b2e7cc1b9cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75527562468466657916997805752254661371369908451637880403469889953259013217533 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.kmac_edn_timeout_error.75527562468466657916997805752254661371369908451637880403469889953259013217533 +enable_masking=1
+sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.95190101054344147061957434204794745892460278062478884970480527363636792507455
Short name T889
Test name
Test status
Simulation time 64850439 ps
CPU time 1.25 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:29 PM PST 23
Peak memory 219084 kb
Host smart-7c9285a6-61d5-4445-ab94-2e69135f1423
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=95190101054344147061957434204794745892460278062478884970480527363636792507455 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.95190101054344147061957434204794745892460278062478884970480527363636792507455 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3812017545046779042473033868632337020270799248117275521267182380340795746082
Short name T449
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.18 seconds
Started Nov 22 02:01:02 PM PST 23
Finished Nov 22 02:01:25 PM PST 23
Peak memory 219304 kb
Host smart-345bfebf-8747-4f92-b0ef-92f294af4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812017545046779042473033868632337020270799248117275521267182380340795746082 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.kmac_entropy_ready_error.3812017545046779042473033868632337020270799248117275521267182380340795746082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.108763924520305710298327390426947427135653453107921400942353963065139945520888
Short name T86
Test name
Test status
Simulation time 7238810904 ps
CPU time 102.8 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:04:14 PM PST 23
Peak memory 243812 kb
Host smart-e8fe7cfc-14c1-4132-b88b-54ea8ead2744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108763924520305710298327390426947427135653453107921400942353963065139945520888 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.kmac_entropy_refresh.108763924520305710298327390426947427135653453107921400942353963065139945520888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.68987789317823025495740569933021738124290371818303012538984804225493633485210
Short name T687
Test name
Test status
Simulation time 8137821569 ps
CPU time 149.33 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:04:06 PM PST 23
Peak memory 252764 kb
Host smart-ce8e06c9-a40e-4ce1-a551-88aedbae939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68987789317823025495740569933021738124290371818303012538984804225493633485210 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.kmac_error.68987789317823025495740569933021738124290371818303012538984804225493633485210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.27281484709252052977914545710241165172500533864831336123590172147217695923117
Short name T284
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.58 seconds
Started Nov 22 02:01:13 PM PST 23
Finished Nov 22 02:01:20 PM PST 23
Peak memory 219228 kb
Host smart-6b907245-0594-430e-ab21-32dc618cf854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27281484709252052977914545710241165172500533864831336123590172147217695923117 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.kmac_key_error.27281484709252052977914545710241165172500533864831336123590172147217695923117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.25138385192817306575957159053396989398161850504793634317048771184544166100901
Short name T1050
Test name
Test status
Simulation time 72761090 ps
CPU time 1.42 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:01:21 PM PST 23
Peak memory 220496 kb
Host smart-d98972cf-40fb-4274-bfe2-8b8be3c3ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25138385192817306575957159053396989398161850504793634317048771184544166100901 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.kmac_lc_escalation.25138385192817306575957159053396989398161850504793634317048771184544166100901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.57913161178863636424501605565538279180575457010689816958897721611568770447193
Short name T708
Test name
Test status
Simulation time 50513696845 ps
CPU time 996.68 seconds
Started Nov 22 02:01:39 PM PST 23
Finished Nov 22 02:18:17 PM PST 23
Peak memory 306356 kb
Host smart-879a19cc-aa27-4431-aad3-fce5e1c637e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57913161178863636424501605565538279180575457010689816958897721611568770447193 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.5791316117886363642450160556553827918057545701068981695889772161156877
0447193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.35613409573986437513720876034629880121509702335165776752496029414745352917542
Short name T456
Test name
Test status
Simulation time 7712378544 ps
CPU time 141.4 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:04:54 PM PST 23
Peak memory 244124 kb
Host smart-65d0eec7-c00b-4891-b2a3-c969ccb5c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35613409573986437513720876034629880121509702335165776752496029414745352917542 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.kmac_mubi.35613409573986437513720876034629880121509702335165776752496029414745352917542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.36146429970272760444502925015940296728022647187441340486395440943271985535332
Short name T1064
Test name
Test status
Simulation time 7628111361 ps
CPU time 143.19 seconds
Started Nov 22 02:01:44 PM PST 23
Finished Nov 22 02:04:08 PM PST 23
Peak memory 235828 kb
Host smart-47a0a1df-88f9-46df-ae75-52b14ccc9337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36146429970272760444502925015940296728022647187441340486395440943271985535332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.kmac_sideload.36146429970272760444502925015940296728022647187441340486395440943271985535332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.67171371341941789803341745177403977028011396115450812884232814637057555145582
Short name T969
Test name
Test status
Simulation time 1925406983 ps
CPU time 26.68 seconds
Started Nov 22 02:02:22 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 225492 kb
Host smart-0665a8ba-bc9e-4e78-a4dd-c139b2b5005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67171371341941789803341745177403977028011396115450812884232814637057555145582 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.kmac_smoke.67171371341941789803341745177403977028011396115450812884232814637057555145582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.4745304436689544471982220954233785391161241455380365014049015966002082458827
Short name T44
Test name
Test status
Simulation time 47207151869 ps
CPU time 909.96 seconds
Started Nov 22 02:01:17 PM PST 23
Finished Nov 22 02:16:27 PM PST 23
Peak memory 339876 kb
Host smart-d43e8e01-7b17-47d7-a3c5-1289545f2b7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4745304436689544471982220954233785391161241455380365014049015966002082458827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stre
ss_all.4745304436689544471982220954233785391161241455380365014049015966002082458827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.56763733199774687695855278484804665544872988765064548298173741355988279366888
Short name T795
Test name
Test status
Simulation time 322955517 ps
CPU time 5.88 seconds
Started Nov 22 02:00:51 PM PST 23
Finished Nov 22 02:00:58 PM PST 23
Peak memory 219204 kb
Host smart-2d21c398-d863-41fe-8f89-9fe88f8b797d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56763733199774687695855278484804665544872988765064548
298173741355988279366888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac.567637331997746876958552784848046655448
72988765064548298173741355988279366888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.79639596710893318921716348948204916253252507732276529119049649686355785602867
Short name T935
Test name
Test status
Simulation time 309259198 ps
CPU time 5.97 seconds
Started Nov 22 02:02:26 PM PST 23
Finished Nov 22 02:02:39 PM PST 23
Peak memory 219256 kb
Host smart-a1f5b4eb-f7c1-40f7-90e3-feb6dd4478a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79639596710893318921716348948204916253252507732276529
119049649686355785602867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.7963959671089331892171634894820
4916253252507732276529119049649686355785602867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.55113934848666948414317410546205311704431885404204304127908661738391076798203
Short name T525
Test name
Test status
Simulation time 117329894454 ps
CPU time 2047.79 seconds
Started Nov 22 02:02:08 PM PST 23
Finished Nov 22 02:36:32 PM PST 23
Peak memory 400760 kb
Host smart-2b45da3c-b0b7-4814-852e-e0946f05492d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55113934848666948414317410546205311704431885404204304127908661738391076798203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_224.55113934848666948414317410546205311704431885404204304127908661738391076798203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.63093495457400599870868237629155641692159289295335166091792377462940615381186
Short name T617
Test name
Test status
Simulation time 106843317633 ps
CPU time 1885.76 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:33:57 PM PST 23
Peak memory 376388 kb
Host smart-9c7f1103-e2ce-45fa-a98a-689c0dfcf939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=63093495457400599870868237629155641692159289295335166091792377462940615381186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_256.63093495457400599870868237629155641692159289295335166091792377462940615381186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.87978708556151572561194001544423642519263899584637756202545339567381865983111
Short name T519
Test name
Test status
Simulation time 83520343504 ps
CPU time 1547.3 seconds
Started Nov 22 02:02:24 PM PST 23
Finished Nov 22 02:28:17 PM PST 23
Peak memory 338456 kb
Host smart-46373427-fbe5-4be3-b982-730777ea5b4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=87978708556151572561194001544423642519263899584637756202545339567381865983111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_384.87978708556151572561194001544423642519263899584637756202545339567381865983111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.46884302102753818162474814518617546842020994752662102539977500970152353548933
Short name T549
Test name
Test status
Simulation time 57499426673 ps
CPU time 1212.57 seconds
Started Nov 22 02:02:05 PM PST 23
Finished Nov 22 02:22:37 PM PST 23
Peak memory 297608 kb
Host smart-e36322ed-7f59-4cb5-998b-b058e14f7196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=46884302102753818162474814518617546842020994752662102539977500970152353548933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_512.46884302102753818162474814518617546842020994752662102539977500970152353548933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.28631407782278815920486251203818917362340849519457904057371886268120429935465
Short name T170
Test name
Test status
Simulation time 320694338954 ps
CPU time 5350.91 seconds
Started Nov 22 02:02:23 PM PST 23
Finished Nov 22 03:31:40 PM PST 23
Peak memory 674184 kb
Host smart-5a020960-9475-4169-bc84-4fc9478b7501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=28631407782278815920486251203818917362340849519457904057371886268120429935465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_test_vectors_shake_128.28631407782278815920486251203818917362340849519457904057371886268120429935465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_alert_test.34999241626412197440174643084693637126443051585356428055541849090656933521582
Short name T457
Test name
Test status
Simulation time 21118646 ps
CPU time 0.82 seconds
Started Nov 22 02:01:58 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 219004 kb
Host smart-8b022f65-7ae5-448a-984c-43962f15da62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34999241626412197440174643084693637126443051585356428055541849090656933521582 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.kmac_alert_test.34999241626412197440174643084693637126443051585356428055541849090656933521582 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.16964821418887929785279522989982929397457846611748783588433686334466448310170
Short name T776
Test name
Test status
Simulation time 6076748772 ps
CPU time 101.79 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:03:15 PM PST 23
Peak memory 236256 kb
Host smart-ea37f96e-79a9-423b-ae6d-fc11ecd88a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16964821418887929785279522989982929397457846611748783588433686334466448310170 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_app.16964821418887929785279522989982929397457846611748783588433686334466448310170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.66358537652388119279815788610777615461220692810881195173250615756676227376583
Short name T1052
Test name
Test status
Simulation time 7277596308 ps
CPU time 117.07 seconds
Started Nov 22 02:01:36 PM PST 23
Finished Nov 22 02:03:34 PM PST 23
Peak memory 243924 kb
Host smart-f9edeebb-f1b9-44a9-9279-850b640df1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66358537652388119279815788610777615461220692810881195173250615756676227376583 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_app_with_partial_data.66358537652388119279815788610777615461220692810881195173250615756676227376583 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.15253690446197497444816477758460329010891247724130477861751663755468115120043
Short name T411
Test name
Test status
Simulation time 14830000174 ps
CPU time 406.98 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:08:08 PM PST 23
Peak memory 243248 kb
Host smart-10ab9dcc-6401-4f6e-9fa3-193a5cddba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15253690446197497444816477758460329010891247724130477861751663755468115120043 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.kmac_burst_write.15253690446197497444816477758460329010891247724130477861751663755468115120043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2167132951035183005980683487828247692296941708034187858727655687107970736366
Short name T888
Test name
Test status
Simulation time 62261174 ps
CPU time 1.29 seconds
Started Nov 22 02:01:38 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 219064 kb
Host smart-eb057619-e3b0-441a-ad72-b26057cca0c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2167132951035183005980683487828247692296941708034187858727655687107970736366 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.kmac_edn_timeout_error.2167132951035183005980683487828247692296941708034187858727655687107970736366 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.8096426045582459224570096886178246825056585141706287653292017345598391074892
Short name T1053
Test name
Test status
Simulation time 64850439 ps
CPU time 1.25 seconds
Started Nov 22 02:01:55 PM PST 23
Finished Nov 22 02:01:57 PM PST 23
Peak memory 219040 kb
Host smart-4a0050d4-5225-4103-9b5d-195db09f522b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=8096426045582459224570096886178246825056585141706287653292017345598391074892 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.kmac_entropy_mode_error.8096426045582459224570096886178246825056585141706287653292017345598391074892 +enable_masking=1
+sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.99671064162885151185594746090643597966304932406656674695221827586269398793433
Short name T583
Test name
Test status
Simulation time 3179093382 ps
CPU time 22.62 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:58 PM PST 23
Peak memory 219300 kb
Host smart-2d8df30d-3ce8-4c96-98c5-37ceea7a8aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99671064162885151185594746090643597966304932406656674695221827586269398793433 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.kmac_entropy_ready_error.99671064162885151185594746090643597966304932406656674695221827586269398793433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.9429654456331819846775404505102264498911359232756676200440342805353965955943
Short name T683
Test name
Test status
Simulation time 7238810904 ps
CPU time 105.85 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 02:03:17 PM PST 23
Peak memory 243880 kb
Host smart-acaee2cf-a963-45c2-8171-b00d8a027461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9429654456331819846775404505102264498911359232756676200440342805353965955943 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.kmac_entropy_refresh.9429654456331819846775404505102264498911359232756676200440342805353965955943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.86852120312934926691104734802157768579207070378082700047434045183750247156341
Short name T31
Test name
Test status
Simulation time 8137821569 ps
CPU time 151.62 seconds
Started Nov 22 02:01:51 PM PST 23
Finished Nov 22 02:04:23 PM PST 23
Peak memory 252760 kb
Host smart-7ecb3ae0-c464-4830-b07d-cd491b842958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86852120312934926691104734802157768579207070378082700047434045183750247156341 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.kmac_error.86852120312934926691104734802157768579207070378082700047434045183750247156341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2891199278260716911985571117766241458572927900191800298970978804811536128707
Short name T937
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.73 seconds
Started Nov 22 02:02:28 PM PST 23
Finished Nov 22 02:02:42 PM PST 23
Peak memory 219264 kb
Host smart-dd8ff06c-e2a3-4144-9129-e3e26c2a6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891199278260716911985571117766241458572927900191800298970978804811536128707 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.kmac_key_error.2891199278260716911985571117766241458572927900191800298970978804811536128707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.49957311200795859441777091042326349284920841739079952754288113394955258050908
Short name T530
Test name
Test status
Simulation time 72761090 ps
CPU time 1.47 seconds
Started Nov 22 02:02:09 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 220408 kb
Host smart-b4a47fd4-f4ea-40ef-8c89-7108acc0f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49957311200795859441777091042326349284920841739079952754288113394955258050908 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.kmac_lc_escalation.49957311200795859441777091042326349284920841739079952754288113394955258050908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.94787804200113283185695226943400059276196476661414482122174736970483265888020
Short name T699
Test name
Test status
Simulation time 50513696845 ps
CPU time 955.17 seconds
Started Nov 22 02:01:13 PM PST 23
Finished Nov 22 02:17:09 PM PST 23
Peak memory 306260 kb
Host smart-3d8111d0-1bd3-46bb-88df-c54eeb206211
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94787804200113283185695226943400059276196476661414482122174736970483265888020 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.9478780420011328318569522694340005927619647666141448212217473697048326
5888020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.115499995842510512244366461580758135500853416589350191997307911867385315976273
Short name T531
Test name
Test status
Simulation time 7712378544 ps
CPU time 136.96 seconds
Started Nov 22 02:01:33 PM PST 23
Finished Nov 22 02:03:51 PM PST 23
Peak memory 244076 kb
Host smart-03036398-6e67-455b-96fa-b4395a90bdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115499995842510512244366461580758135500853416589350191997307911867385315976273 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.kmac_mubi.115499995842510512244366461580758135500853416589350191997307911867385315976273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.73978979823948824902452045436225417528215700418541189761010633238990935592439
Short name T495
Test name
Test status
Simulation time 7628111361 ps
CPU time 134.55 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:03:50 PM PST 23
Peak memory 236384 kb
Host smart-9b379010-5a12-4852-9270-88fe29f19cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73978979823948824902452045436225417528215700418541189761010633238990935592439 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.kmac_sideload.73978979823948824902452045436225417528215700418541189761010633238990935592439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.99061871302847262047864248923863682817697323383539928686799222058563036754677
Short name T482
Test name
Test status
Simulation time 1925406983 ps
CPU time 27.72 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:01:50 PM PST 23
Peak memory 225384 kb
Host smart-589a5790-41ec-427e-9267-4157d6ad26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99061871302847262047864248923863682817697323383539928686799222058563036754677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.kmac_smoke.99061871302847262047864248923863682817697323383539928686799222058563036754677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.72543311781163906974783395280656040242623949106021944221496185262676801291092
Short name T329
Test name
Test status
Simulation time 322955517 ps
CPU time 6.08 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:01:41 PM PST 23
Peak memory 219228 kb
Host smart-edd113de-d9fc-4c61-beff-d4062ae0850c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72543311781163906974783395280656040242623949106021944
221496185262676801291092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac.725433117811639069747833952806560402426
23949106021944221496185262676801291092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3737917977148714968090995327653221033754921290981080942003310795309122356939
Short name T970
Test name
Test status
Simulation time 309259198 ps
CPU time 6.02 seconds
Started Nov 22 02:01:35 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 219232 kb
Host smart-7f267925-f766-41e2-8ba8-59ab3683818e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379179771487149680909953276532210337549212909810809
42003310795309122356939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.37379179771487149680909953276532
21033754921290981080942003310795309122356939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.65472757910021620375888966111903162029556958857931268523393804036262983225827
Short name T773
Test name
Test status
Simulation time 117329894454 ps
CPU time 2113.85 seconds
Started Nov 22 02:01:18 PM PST 23
Finished Nov 22 02:36:33 PM PST 23
Peak memory 400812 kb
Host smart-f29cc70a-2a4e-45a5-8756-e82f74ce4e3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65472757910021620375888966111903162029556958857931268523393804036262983225827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
kmac_test_vectors_sha3_224.65472757910021620375888966111903162029556958857931268523393804036262983225827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.47904732942298189612746943053735169995294864859290922857569215555397117165804
Short name T926
Test name
Test status
Simulation time 106843317633 ps
CPU time 1941.58 seconds
Started Nov 22 02:01:34 PM PST 23
Finished Nov 22 02:33:57 PM PST 23
Peak memory 376368 kb
Host smart-f299e462-6eb5-4d40-b3af-e4c8051f5a19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47904732942298189612746943053735169995294864859290922857569215555397117165804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
kmac_test_vectors_sha3_256.47904732942298189612746943053735169995294864859290922857569215555397117165804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.114800144165631687426799656129598345931785460488770843465479416463133675582208
Short name T399
Test name
Test status
Simulation time 83520343504 ps
CPU time 1552.23 seconds
Started Nov 22 02:01:32 PM PST 23
Finished Nov 22 02:27:25 PM PST 23
Peak memory 338264 kb
Host smart-e25ae207-3785-462b-8e76-f8f6896cd0f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114800144165631687426799656129598345931785460488770843465479416463133675582208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.kmac_test_vectors_sha3_384.114800144165631687426799656129598345931785460488770843465479416463133675582208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.16674365109696362425820025650341365755771482854805598310163733150868271141457
Short name T330
Test name
Test status
Simulation time 57499426673 ps
CPU time 1114.23 seconds
Started Nov 22 02:01:21 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 297804 kb
Host smart-97e54f0e-ded7-47a4-a864-36892eabe180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16674365109696362425820025650341365755771482854805598310163733150868271141457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
kmac_test_vectors_sha3_512.16674365109696362425820025650341365755771482854805598310163733150868271141457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.65607366877526544859074714495902550520526538699033902623160518580534943050368
Short name T584
Test name
Test status
Simulation time 320694338954 ps
CPU time 5506.49 seconds
Started Nov 22 02:01:31 PM PST 23
Finished Nov 22 03:33:19 PM PST 23
Peak memory 674264 kb
Host smart-58cd0a6d-bbd1-465e-ba52-28b86c4ae7c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=65607366877526544859074714495902550520526538699033902623160518580534943050368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_test_vectors_shake_128.65607366877526544859074714495902550520526538699033902623160518580534943050368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.38032521894377984123254452757343965133858378483674408996834333768444429495254
Short name T994
Test name
Test status
Simulation time 270085708112 ps
CPU time 4537.33 seconds
Started Nov 22 02:01:52 PM PST 23
Finished Nov 22 03:17:31 PM PST 23
Peak memory 577176 kb
Host smart-b0504c0e-d677-4e19-a160-c1015c886008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=38032521894377984123254452757343965133858378483674408996834333768444429495254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_test_vectors_shake_256.38032521894377984123254452757343965133858378483674408996834333768444429495254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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