Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102812690	1			T2	5		T3	8		T50	1
all_values[1]	102812690	1			T2	5		T3	8		T50	1
all_values[2]	102812690	1			T2	5		T3	8		T50	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660167

1

T2

5

T3

13

T50

3

auto[1]

307777903

1

T2

10

T3

11

T51

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306876870

1

T2

9

T3

24

T50

3

auto[1]

1561200

1

T2

6

T51

15

T64

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	230723	1			T3	7		T50	1		T51	2
all_values[0]	auto[0]	auto[1]	2369	1			T51	1		T64	2		T141	2
all_values[0]	auto[1]	auto[0]	102061567	1			T2	3		T3	1		T51	1
all_values[0]	auto[1]	auto[1]	518031	1			T2	2		T51	4		T64	3
all_values[1]	auto[0]	auto[0]	212020	1			T3	5		T50	1		T51	2
all_values[1]	auto[0]	auto[1]	1825	1			T2	1		T51	3		T64	2
all_values[1]	auto[1]	auto[0]	102080270	1			T2	3		T3	3		T51	1
all_values[1]	auto[1]	auto[1]	518575	1			T2	1		T51	2		T64	3
all_values[2]	auto[0]	auto[0]	211315	1			T2	3		T3	1		T50	1
all_values[2]	auto[0]	auto[1]	1915	1			T2	1		T51	3		T64	4
all_values[2]	auto[1]	auto[0]	102080975	1			T3	7		T51	1		T64	3
all_values[2]	auto[1]	auto[1]	518485	1			T2	1		T51	2		T64	1