Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
403574 |
1 |
|
|
T4 |
364 |
|
T5 |
272 |
|
T6 |
18 |
auto[1] |
306210 |
1 |
|
|
T5 |
320 |
|
T10 |
104 |
|
T22 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
177578 |
1 |
|
|
T4 |
92 |
|
T5 |
135 |
|
T6 |
7 |
lower_val |
175737 |
1 |
|
|
T4 |
74 |
|
T5 |
146 |
|
T6 |
4 |
zero_val |
1978 |
1 |
|
|
T4 |
1 |
|
T5 |
7 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
277640 |
1 |
|
|
T4 |
168 |
|
T5 |
216 |
|
T6 |
8 |
lower_val |
278188 |
1 |
|
|
T4 |
196 |
|
T5 |
210 |
|
T6 |
10 |
zero_val |
153956 |
1 |
|
|
T5 |
166 |
|
T10 |
62 |
|
T22 |
2360 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
50337 |
1 |
|
|
T4 |
46 |
|
T5 |
30 |
|
T6 |
3 |
higher_val |
higher_val |
auto[1] |
19249 |
1 |
|
|
T5 |
11 |
|
T10 |
4 |
|
T22 |
293 |
higher_val |
lower_val |
auto[0] |
50091 |
1 |
|
|
T4 |
46 |
|
T5 |
35 |
|
T6 |
4 |
higher_val |
lower_val |
auto[1] |
19411 |
1 |
|
|
T5 |
20 |
|
T10 |
3 |
|
T22 |
252 |
higher_val |
zero_val |
auto[0] |
93 |
1 |
|
|
T10 |
1 |
|
T104 |
1 |
|
T70 |
1 |
higher_val |
zero_val |
auto[1] |
38397 |
1 |
|
|
T5 |
39 |
|
T10 |
16 |
|
T22 |
625 |
lower_val |
higher_val |
auto[0] |
49985 |
1 |
|
|
T4 |
40 |
|
T5 |
26 |
|
T6 |
2 |
lower_val |
higher_val |
auto[1] |
18970 |
1 |
|
|
T5 |
27 |
|
T10 |
6 |
|
T22 |
271 |
lower_val |
lower_val |
auto[0] |
49648 |
1 |
|
|
T4 |
34 |
|
T5 |
39 |
|
T6 |
2 |
lower_val |
lower_val |
auto[1] |
18965 |
1 |
|
|
T5 |
9 |
|
T10 |
10 |
|
T22 |
257 |
lower_val |
zero_val |
auto[0] |
95 |
1 |
|
|
T5 |
2 |
|
T10 |
1 |
|
T156 |
1 |
lower_val |
zero_val |
auto[1] |
38074 |
1 |
|
|
T5 |
43 |
|
T10 |
11 |
|
T22 |
571 |
zero_val |
higher_val |
auto[0] |
592 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
zero_val |
higher_val |
auto[1] |
159 |
1 |
|
|
T5 |
1 |
|
T10 |
2 |
|
T22 |
1 |
zero_val |
lower_val |
auto[0] |
614 |
1 |
|
|
T5 |
2 |
|
T10 |
1 |
|
T25 |
1 |
zero_val |
lower_val |
auto[1] |
145 |
1 |
|
|
T157 |
1 |
|
T158 |
1 |
|
T13 |
1 |
zero_val |
zero_val |
auto[0] |
288 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T22 |
1 |
zero_val |
zero_val |
auto[1] |
180 |
1 |
|
|
T5 |
1 |
|
T22 |
1 |
|
T31 |
1 |