Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10353	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9371	1			T5	15		T22	38		T25	24
len_5001_7500	15220	1			T5	58		T22	36		T25	85
len_2501_5000	9455	1			T5	14		T22	36		T25	13
len_1025_2500	5513	1			T5	8		T22	22		T25	10
len_769_1024	6994	1			T4	37		T5	18		T10	3
len_513_768	7348	1			T4	57		T5	23		T10	2
len_257_512	21739	1			T4	33		T5	21		T10	6
len_0_256	261091	1			T4	39		T5	91		T6	9
len_keccak_block_sizes[72]	728	1			T22	3		T28	2		T103	3
len_keccak_block_sizes[104]	629	1			T22	3		T28	2		T103	3
len_keccak_block_sizes[136]	515	1			T22	3		T28	2		T103	3
len_keccak_block_sizes[144]	424	1			T4	2		T22	3		T43	1
len_keccak_block_sizes[168]	324	1			T22	3		T23	1		T103	3
len_1	752	1			T22	3		T28	2		T46	1
len_0	1303	1			T5	3		T10	1		T22	3