Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102812690	1			T2	5		T3	8		T50	1
all_pins[1]	102812690	1			T2	5		T3	8		T50	1
all_pins[2]	102812690	1			T2	5		T3	8		T50	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	256130384	1			T2	10		T3	17		T50	3
values[0x1]	52307686	1			T2	5		T3	7		T51	5
transitions[0x0=>0x1]	51858618	1			T2	4		T3	5		T51	4
transitions[0x1=>0x0]	51858639	1			T2	4		T3	6		T51	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102294659	1			T2	3		T3	8		T50	1
all_pins[0]	values[0x1]	518031	1			T2	2		T51	4		T64	3
all_pins[0]	transitions[0x0=>0x1]	217758	1			T2	2		T51	4		T64	1
all_pins[0]	transitions[0x1=>0x0]	51116152	1			T2	2		T3	1		T64	3
all_pins[1]	values[0x0]	51396265	1			T2	3		T3	7		T50	1
all_pins[1]	values[0x1]	51416425	1			T2	2		T3	1		T64	5
all_pins[1]	transitions[0x0=>0x1]	51269870	1			T2	2		T64	3		T141	1
all_pins[1]	transitions[0x1=>0x0]	226675	1			T2	1		T3	5		T51	1
all_pins[2]	values[0x0]	102439460	1			T2	4		T3	2		T50	1
all_pins[2]	values[0x1]	373230	1			T2	1		T3	6		T51	1
all_pins[2]	transitions[0x0=>0x1]	370990	1			T3	5		T64	1		T141	2
all_pins[2]	transitions[0x1=>0x0]	515812	1			T2	1		T51	3		T64	2