Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	764	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6180	1			T4	15		T5	38		T10	1
len_601_800	14065	1			T4	58		T5	61		T10	2
len_401_600	9345	1			T4	35		T5	46		T10	5
len_201_400	16959	1			T4	15		T5	16		T10	2
len_65_200	74976	1			T4	5		T5	23		T10	11
len_min_for_xof_require_squeeze	1020	1			T22	10		T103	9		T31	10
len_keccak_block_sizes[72]	758	1			T22	5		T103	9		T31	5
len_keccak_block_sizes[104]	765	1			T22	5		T103	9		T31	5
len_keccak_block_sizes[136]	768	1			T5	2		T22	5		T103	9
len_keccak_block_sizes[144]	291	1			T22	5		T31	5		T159	5
len_keccak_block_sizes[168]	290	1			T22	5		T31	5		T160	2
len_datapath_width	14409	1			T4	1		T5	18		T6	3
len_2_63	216267	1			T4	7		T5	93		T6	6
len_1	70	1			T25	1		T156	1		T160	1