Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::state_read_mask_cg

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
share	2	0	2	100.00	100	1	1	2
state_read_mask	4	0	4	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_mask_share_cross	8	0	8	100.00	100	1	1	0

Summary for Variable share

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for share

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11552992

1

T4

27711

T5

33451

T6

96

auto[1]

11552682

1

T4

27711

T5

33451

T6

96

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Summary for Variable state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for state_read_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	22858799	1			T4	55192		T5	66590		T6	192
triple_byte_access	81900	1			T4	72		T5	104		T10	18
halfword_access	82914	1			T4	76		T5	106		T10	14
byte_access	82061	1			T4	82		T5	102		T10	10

---

Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for state_mask_share_cross

Bins

share	state_read_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	11429553	1			T4	27596		T5	33295		T6	96
auto[0]	triple_byte_access	40951	1			T4	36		T5	52		T10	9
auto[0]	halfword_access	41457	1			T4	38		T5	53		T10	7
auto[0]	byte_access	41031	1			T4	41		T5	51		T10	5
auto[1]	word_access	11429246	1			T4	27596		T5	33295		T6	96
auto[1]	triple_byte_access	40949	1			T4	36		T5	52		T10	9
auto[1]	halfword_access	41457	1			T4	38		T5	53		T10	7
auto[1]	byte_access	41030	1			T4	41		T5	51		T10	5