Unified Coverage Report :: Tests

Tests

dashboard | hierarchy | modlist | groups | tests | asserts

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.15	99.93	95.45	96.04	98.89	98.31

Total test records in report: 1266

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/36.kmac_intr_test.2449684250			Dec 24 12:30:34 PM PST 23	Dec 24 12:31:02 PM PST 23	102437909 ps
T1252	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.233633169			Dec 24 12:29:36 PM PST 23	Dec 24 12:29:53 PM PST 23	67375579 ps
T1253	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1021896852			Dec 24 12:30:42 PM PST 23	Dec 24 12:31:10 PM PST 23	139905763 ps
T1254	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1567132827			Dec 24 12:30:33 PM PST 23	Dec 24 12:31:03 PM PST 23	441744499 ps
T1255	/workspace/coverage/cover_reg_top/48.kmac_intr_test.4051801909			Dec 24 12:31:15 PM PST 23	Dec 24 12:31:38 PM PST 23	38492127 ps
T1256	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3823812009			Dec 24 12:30:02 PM PST 23	Dec 24 12:30:29 PM PST 23	41436628 ps
T1257	/workspace/coverage/cover_reg_top/7.kmac_intr_test.3855728774			Dec 24 12:29:31 PM PST 23	Dec 24 12:29:44 PM PST 23	14823931 ps
T1258	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3793135242			Dec 24 12:31:29 PM PST 23	Dec 24 12:31:56 PM PST 23	779184173 ps
T1259	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.585924754			Dec 24 12:29:47 PM PST 23	Dec 24 12:30:11 PM PST 23	38877402 ps
T1260	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.690997339			Dec 24 12:29:25 PM PST 23	Dec 24 12:29:42 PM PST 23	618659015 ps
T1261	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3681416915			Dec 24 12:29:23 PM PST 23	Dec 24 12:29:35 PM PST 23	49412157 ps
T1262	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2550342324			Dec 24 12:29:45 PM PST 23	Dec 24 12:30:12 PM PST 23	931161118 ps
T1263	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3338508294			Dec 24 12:29:30 PM PST 23	Dec 24 12:29:43 PM PST 23	127146394 ps
T1264	/workspace/coverage/cover_reg_top/17.kmac_intr_test.4284910250			Dec 24 12:31:14 PM PST 23	Dec 24 12:31:37 PM PST 23	16869207 ps
T1265	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2989777198			Dec 24 12:29:41 PM PST 23	Dec 24 12:30:03 PM PST 23	25117140 ps
T1266	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2065762677			Dec 24 12:29:22 PM PST 23	Dec 24 12:29:35 PM PST 23	381819359 ps

Test location	/workspace/coverage/default/9.kmac_stress_all.1631097215
Short name	T5
Test name
Test status
Simulation time	227694094172 ps
CPU time	1312.53 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:41:08 PM PST 23
Peak memory	336636 kb
Host	smart-3f3948b8-2578-478c-8a6a-2ffccf18b5e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1631097215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1631097215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2453047450
Short name	T1
Test name
Test status
Simulation time	458830026 ps
CPU time	10.85 seconds
Started	Dec 24 12:31:10 PM PST 23
Finished	Dec 24 12:31:41 PM PST 23
Peak memory	217268 kb
Host	smart-06ad1388-38c0-4843-8a5b-769a9405c5b5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453047450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2453047 450 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3967933676
Short name	T48
Test name
Test status
Simulation time	521625932 ps
CPU time	3.26 seconds
Started	Dec 24 12:30:32 PM PST 23
Finished	Dec 24 12:31:02 PM PST 23
Peak memory	217636 kb
Host	smart-84d06a08-5818-455e-bd1c-35cc510e698d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967933676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3967 933676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3959255640
Short name	T64
Test name
Test status
Simulation time	26262255 ps
CPU time	0.8 seconds
Started	Dec 24 12:30:50 PM PST 23
Finished	Dec 24 12:31:15 PM PST 23
Peak memory	216664 kb
Host	smart-acf472a6-3091-41a3-8749-3484ac5aa938
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959255640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3959255640 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/default/35.kmac_stress_all_with_rand_reset.3143786468
Short name	T10
Test name
Test status
Simulation time	72876589112 ps
CPU time	312.9 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:25:30 PM PST 23
Peak memory	260000 kb
Host	smart-83e8eda1-a86d-4715-b54d-8c509b2757e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3143786468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.3143786468 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.3569302037
Short name	T8
Test name
Test status
Simulation time	25187932222 ps
CPU time	106.82 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:20:30 PM PST 23
Peak memory	289744 kb
Host	smart-f3ec9c28-3f34-40d9-b01d-3f1338f2a3db
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569302037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3569302037 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/default/7.kmac_error.854840848
Short name	T4
Test name
Test status
Simulation time	16985466027 ps
CPU time	454.92 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 01:26:33 PM PST 23
Peak memory	268172 kb
Host	smart-682dd0a2-4b2a-4259-adb9-98ce256afaf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854840848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.854840848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2357745143
Short name	T80
Test name
Test status
Simulation time	165465610 ps
CPU time	1.32 seconds
Started	Dec 24 12:29:33 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	225324 kb
Host	smart-846d10b1-bc18-4729-b447-59a51ef3fec4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357745143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2357745143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.206514344
Short name	T50
Test name
Test status
Simulation time	147473971 ps
CPU time	2.56 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	217680 kb
Host	smart-1b99491c-c507-4071-991a-318878ea5d3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206514344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.206514344 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1508511800
Short name	T115
Test name
Test status
Simulation time	39204337 ps
CPU time	1.5 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:53 PM PST 23
Peak memory	217476 kb
Host	smart-28f3bf2c-dc1f-4bea-a374-d3098aa7f102
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508511800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1508511800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.624273930
Short name	T31
Test name
Test status
Simulation time	893279066219 ps
CPU time	5116.68 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 02:44:19 PM PST 23
Peak memory	585408 kb
Host	smart-cd0e2093-530b-467a-b016-66e2421beb24
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=624273930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.624273930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/0.kmac_key_error.3425996229
Short name	T35
Test name
Test status
Simulation time	1172345125 ps
CPU time	1.94 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:18:10 PM PST 23
Peak memory	218584 kb
Host	smart-bd78cf38-91e0-47e8-baab-6f4913d109bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425996229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3425996229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3613718108
Short name	T86
Test name
Test status
Simulation time	39525686 ps
CPU time	1.29 seconds
Started	Dec 24 12:30:15 PM PST 23
Finished	Dec 24 12:30:39 PM PST 23
Peak memory	217988 kb
Host	smart-674188e8-7f38-4fd6-9623-f94e9b8f17ee
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613718108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3613718108 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.1281296776
Short name	T642
Test name
Test status
Simulation time	27145410478 ps
CPU time	65.62 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	222020 kb
Host	smart-5172e99b-2b99-4256-9447-09e740c6ff8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281296776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1281296776 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/21.kmac_stress_all_with_rand_reset.4066267701
Short name	T15
Test name
Test status
Simulation time	88746370003 ps
CPU time	1978.72 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:52:21 PM PST 23
Peak memory	326568 kb
Host	smart-81a7f871-a212-4850-8ad2-76efb77fc930
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4066267701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.4066267701 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.894473740
Short name	T108
Test name
Test status
Simulation time	97651226 ps
CPU time	4.28 seconds
Started	Dec 24 12:29:39 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	217584 kb
Host	smart-fd8af6f4-7be1-4b40-ac1e-ea726d399a66
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894473740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.89447 3740 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.950788643
Short name	T161
Test name
Test status
Simulation time	55157963 ps
CPU time	0.82 seconds
Started	Dec 24 12:30:23 PM PST 23
Finished	Dec 24 12:30:47 PM PST 23
Peak memory	216544 kb
Host	smart-2da9a183-ce8a-45ce-a46a-e5f066b00f25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950788643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.950788643 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.2509533923
Short name	T440
Test name
Test status
Simulation time	45923319 ps
CPU time	1.2 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:18:00 PM PST 23
Peak memory	218764 kb
Host	smart-15718178-4372-4c49-930b-9820c7aaa5bd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2509533923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2509533923 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_error.2045517395
Short name	T30
Test name
Test status
Simulation time	4551354796 ps
CPU time	366.94 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:25:08 PM PST 23
Peak memory	268064 kb
Host	smart-9ff51500-0f34-47c3-aba0-ec7721f3ead7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045517395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2045517395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2310014787
Short name	T87
Test name
Test status
Simulation time	24374250 ps
CPU time	1.07 seconds
Started	Dec 24 12:31:08 PM PST 23
Finished	Dec 24 12:31:28 PM PST 23
Peak memory	222020 kb
Host	smart-8ba440fd-d503-4d3e-8a03-40e7e383015b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310014787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.2310014787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3774135800
Short name	T147
Test name
Test status
Simulation time	1023465344 ps
CPU time	5.71 seconds
Started	Dec 24 12:30:20 PM PST 23
Finished	Dec 24 12:30:48 PM PST 23
Peak memory	217536 kb
Host	smart-1937bf4f-5ed0-4cf7-aa86-bc21c1af283a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774135800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3774 135800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.2883689178
Short name	T683
Test name
Test status
Simulation time	149504526 ps
CPU time	1.16 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:18:00 PM PST 23
Peak memory	218808 kb
Host	smart-c5f7b8ae-fecf-40a1-b659-b209cbb14522
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2883689178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2883689178 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2116009057
Short name	T52
Test name
Test status
Simulation time	105451373 ps
CPU time	2.52 seconds
Started	Dec 24 12:29:40 PM PST 23
Finished	Dec 24 12:30:04 PM PST 23
Peak memory	216668 kb
Host	smart-b3d0f8fe-85c2-4852-a627-198f34cc024f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116009057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2116009057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/default/25.kmac_stress_all_with_rand_reset.673227992
Short name	T19
Test name
Test status
Simulation time	164596937237 ps
CPU time	1528.47 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:45:09 PM PST 23
Peak memory	320280 kb
Host	smart-0d71be72-f98b-4a82-973c-1acb462d6da9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=673227992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.673227992 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3521323127
Short name	T151
Test name
Test status
Simulation time	589323972 ps
CPU time	6.14 seconds
Started	Dec 24 12:30:45 PM PST 23
Finished	Dec 24 12:31:17 PM PST 23
Peak memory	216032 kb
Host	smart-90d546c4-b759-45d7-bbfa-cc259379dc58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521323127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.35213 23127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.1963756397
Short name	T32
Test name
Test status
Simulation time	23788000364 ps
CPU time	296.82 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:24:55 PM PST 23
Peak memory	248084 kb
Host	smart-48482b7f-2e77-4b37-9122-af5fcf6b4598
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963756397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1963756397 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.3880142833
Short name	T237
Test name
Test status
Simulation time	188520969 ps
CPU time	0.83 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	218628 kb
Host	smart-a507c935-6e77-4442-816f-53a88b3cf5b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880142833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3880142833 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.313887775
Short name	T265
Test name
Test status
Simulation time	984982983 ps
CPU time	26.34 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:19:48 PM PST 23
Peak memory	236856 kb
Host	smart-9461c1c3-3805-4849-b528-0c88dce11210
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313887775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.313887775 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.690997339
Short name	T1260
Test name
Test status
Simulation time	618659015 ps
CPU time	8.5 seconds
Started	Dec 24 12:29:25 PM PST 23
Finished	Dec 24 12:29:42 PM PST 23
Peak memory	216972 kb
Host	smart-d6868364-20e2-43d4-b126-ecbc8e86a4b6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690997339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.69099733 9 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.980034256
Short name	T1157
Test name
Test status
Simulation time	21596648 ps
CPU time	1.03 seconds
Started	Dec 24 12:30:03 PM PST 23
Finished	Dec 24 12:30:30 PM PST 23
Peak memory	217284 kb
Host	smart-061ae8b4-8a63-43a9-8c80-f737880a48d0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980034256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.98003425 6 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4231579296
Short name	T1213
Test name
Test status
Simulation time	23450597 ps
CPU time	1.43 seconds
Started	Dec 24 12:30:20 PM PST 23
Finished	Dec 24 12:30:44 PM PST 23
Peak memory	221184 kb
Host	smart-cb67be14-6848-4379-be24-c3ef47ecede4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231579296 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4231579296 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.505865744
Short name	T173
Test name
Test status
Simulation time	86615578 ps
CPU time	1.12 seconds
Started	Dec 24 12:29:45 PM PST 23
Finished	Dec 24 12:30:08 PM PST 23
Peak memory	217520 kb
Host	smart-f0f3bc41-e977-4be7-ade1-2e8267d9a488
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505865744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.505865744 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.4011173538
Short name	T1245
Test name
Test status
Simulation time	40624760 ps
CPU time	0.76 seconds
Started	Dec 24 12:29:44 PM PST 23
Finished	Dec 24 12:30:07 PM PST 23
Peak memory	216660 kb
Host	smart-688f9468-98ea-418a-b412-1d761185f0fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011173538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.4011173538 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2087544551
Short name	T122
Test name
Test status
Simulation time	64930942 ps
CPU time	1.3 seconds
Started	Dec 24 12:31:44 PM PST 23
Finished	Dec 24 12:32:13 PM PST 23
Peak memory	217496 kb
Host	smart-c5feb506-1815-4218-83ed-906259ec3888
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087544551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.2087544551 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.1141959742
Short name	T1186
Test name
Test status
Simulation time	12055457 ps
CPU time	0.77 seconds
Started	Dec 24 12:30:06 PM PST 23
Finished	Dec 24 12:30:32 PM PST 23
Peak memory	216448 kb
Host	smart-dadfde87-766a-4140-a52f-cb1e13721315
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141959742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1141959742 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.4121076249
Short name	T1178
Test name
Test status
Simulation time	58194233 ps
CPU time	1.6 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	216672 kb
Host	smart-de361105-ccfd-403a-9b0d-046ebe60b6f6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121076249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.4121076249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2368328147
Short name	T85
Test name
Test status
Simulation time	222743555 ps
CPU time	1.91 seconds
Started	Dec 24 12:30:10 PM PST 23
Finished	Dec 24 12:30:36 PM PST 23
Peak memory	221632 kb
Host	smart-9aa42038-d9f6-481e-806e-721fcf415df2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368328147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.2368328147 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.4184359267
Short name	T119
Test name
Test status
Simulation time	303747347 ps
CPU time	2.87 seconds
Started	Dec 24 12:31:24 PM PST 23
Finished	Dec 24 12:31:52 PM PST 23
Peak memory	216940 kb
Host	smart-4b2ccf72-0e20-4e0f-ad8a-49702d2320d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184359267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.4184359267 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1942620195
Short name	T1228
Test name
Test status
Simulation time	330825520 ps
CPU time	4.87 seconds
Started	Dec 24 12:31:07 PM PST 23
Finished	Dec 24 12:31:30 PM PST 23
Peak memory	217396 kb
Host	smart-ff462604-712e-40cf-aa0f-8f5ca441ac2a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942620195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1942620 195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3497103505
Short name	T1171
Test name
Test status
Simulation time	163332902 ps
CPU time	8.27 seconds
Started	Dec 24 12:31:39 PM PST 23
Finished	Dec 24 12:32:14 PM PST 23
Peak memory	217568 kb
Host	smart-1bf737d6-7ece-4c60-a318-31490157d1e9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497103505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3497103 505 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3193512467
Short name	T164
Test name
Test status
Simulation time	188963985 ps
CPU time	0.98 seconds
Started	Dec 24 12:31:27 PM PST 23
Finished	Dec 24 12:31:53 PM PST 23
Peak memory	217268 kb
Host	smart-bd7ca223-7082-4559-8bd1-3749802a35d1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193512467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3193512 467 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4200563464
Short name	T1202
Test name
Test status
Simulation time	86465407 ps
CPU time	2.29 seconds
Started	Dec 24 12:30:03 PM PST 23
Finished	Dec 24 12:30:31 PM PST 23
Peak memory	224564 kb
Host	smart-1497efa0-6924-4c1a-979d-a020b6bc493f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200563464 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.4200563464 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.3701554321
Short name	T172
Test name
Test status
Simulation time	24290544 ps
CPU time	0.98 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	216744 kb
Host	smart-ae88d516-d5d8-4b7c-91ad-90db071fc1f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701554321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3701554321 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2062605509
Short name	T163
Test name
Test status
Simulation time	16660158 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:21 PM PST 23
Finished	Dec 24 12:29:33 PM PST 23
Peak memory	217460 kb
Host	smart-37fc5573-b825-4622-b8bb-06d70ea66982
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062605509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2062605509 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2795236797
Short name	T66
Test name
Test status
Simulation time	102830282 ps
CPU time	1.27 seconds
Started	Dec 24 12:30:09 PM PST 23
Finished	Dec 24 12:30:35 PM PST 23
Peak memory	217532 kb
Host	smart-648cf8d7-9c82-4c00-bb26-97ccad41d527
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795236797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2795236797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.3217716033
Short name	T1206
Test name
Test status
Simulation time	23796580 ps
CPU time	0.74 seconds
Started	Dec 24 12:30:02 PM PST 23
Finished	Dec 24 12:30:28 PM PST 23
Peak memory	217328 kb
Host	smart-98a40b7c-9743-4a4a-8592-983dcc608ec4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217716033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3217716033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4120681571
Short name	T1192
Test name
Test status
Simulation time	105132500 ps
CPU time	2.32 seconds
Started	Dec 24 12:30:04 PM PST 23
Finished	Dec 24 12:30:32 PM PST 23
Peak memory	216672 kb
Host	smart-76768ba3-37b2-4eb5-bd11-1316e86722cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120681571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.4120681571 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.282648171
Short name	T1164
Test name
Test status
Simulation time	53118339 ps
CPU time	1.34 seconds
Started	Dec 24 12:29:34 PM PST 23
Finished	Dec 24 12:29:49 PM PST 23
Peak memory	218960 kb
Host	smart-c008753b-3385-43a9-a537-44724bc62d31
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282648171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e rrors.282648171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1385729530
Short name	T90
Test name
Test status
Simulation time	527827569 ps
CPU time	3.19 seconds
Started	Dec 24 12:31:36 PM PST 23
Finished	Dec 24 12:32:05 PM PST 23
Peak memory	221568 kb
Host	smart-60c73a6e-984c-4c4e-a460-2950ec8bf43c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385729530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.1385729530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3681416915
Short name	T1261
Test name
Test status
Simulation time	49412157 ps
CPU time	3.07 seconds
Started	Dec 24 12:29:23 PM PST 23
Finished	Dec 24 12:29:35 PM PST 23
Peak memory	217860 kb
Host	smart-491fe57a-aa29-4cd1-b0a1-af281fb1f507
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681416915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3681416915 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.920076699
Short name	T149
Test name
Test status
Simulation time	87897500 ps
CPU time	2.47 seconds
Started	Dec 24 12:30:13 PM PST 23
Finished	Dec 24 12:30:39 PM PST 23
Peak memory	217620 kb
Host	smart-8818bd85-d38b-411b-880d-2e401b408304
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920076699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.920076 699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3823812009
Short name	T1256
Test name
Test status
Simulation time	41436628 ps
CPU time	1.99 seconds
Started	Dec 24 12:30:02 PM PST 23
Finished	Dec 24 12:30:29 PM PST 23
Peak memory	219028 kb
Host	smart-a54a927a-c991-465e-b91b-1e3f2cece2cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823812009 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3823812009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.2591653699
Short name	T49
Test name
Test status
Simulation time	186278576 ps
CPU time	1.16 seconds
Started	Dec 24 12:29:33 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	217628 kb
Host	smart-c582311e-eb8d-46fe-a91c-88c5572088f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591653699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2591653699 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.434676728
Short name	T1154
Test name
Test status
Simulation time	23695065 ps
CPU time	0.76 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:49 PM PST 23
Peak memory	217472 kb
Host	smart-dd8782cc-23a3-4388-92fb-1f7720637795
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434676728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.434676728 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.14124652
Short name	T1170
Test name
Test status
Simulation time	484286974 ps
CPU time	2.67 seconds
Started	Dec 24 12:31:41 PM PST 23
Finished	Dec 24 12:32:11 PM PST 23
Peak memory	216728 kb
Host	smart-a4519c74-2d51-4d5a-a41b-bf83612c4372
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14124652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_ outstanding.14124652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.526946296
Short name	T1174
Test name
Test status
Simulation time	32856491 ps
CPU time	1.22 seconds
Started	Dec 24 12:30:04 PM PST 23
Finished	Dec 24 12:30:31 PM PST 23
Peak memory	218288 kb
Host	smart-955e1185-f7c0-44c2-9b2a-947fcde14322
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526946296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_ errors.526946296 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2269853756
Short name	T1232
Test name
Test status
Simulation time	72544050 ps
CPU time	1.82 seconds
Started	Dec 24 12:29:40 PM PST 23
Finished	Dec 24 12:30:02 PM PST 23
Peak memory	217688 kb
Host	smart-6d9b0468-30d2-4298-8eb6-15435aeca86d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269853756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.2269853756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2769783581
Short name	T1146
Test name
Test status
Simulation time	692421406 ps
CPU time	3.17 seconds
Started	Dec 24 12:29:35 PM PST 23
Finished	Dec 24 12:29:53 PM PST 23
Peak memory	217708 kb
Host	smart-443fc613-65d9-4e02-9a2c-286d5f26b760
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769783581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2769783581 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.832747369
Short name	T109
Test name
Test status
Simulation time	791900887 ps
CPU time	5.01 seconds
Started	Dec 24 12:29:42 PM PST 23
Finished	Dec 24 12:30:07 PM PST 23
Peak memory	217056 kb
Host	smart-28d24249-89ad-49ea-b010-8497d0b8535e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832747369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.83274 7369 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3849720191
Short name	T1214
Test name
Test status
Simulation time	66591839 ps
CPU time	1.51 seconds
Started	Dec 24 12:29:46 PM PST 23
Finished	Dec 24 12:30:09 PM PST 23
Peak memory	219016 kb
Host	smart-580b804f-a627-40f4-8137-ee08b07bfdfc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849720191 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3849720191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2364277145
Short name	T1225
Test name
Test status
Simulation time	28273545 ps
CPU time	1.09 seconds
Started	Dec 24 12:30:11 PM PST 23
Finished	Dec 24 12:30:37 PM PST 23
Peak memory	216760 kb
Host	smart-8ed934b4-5142-43ef-b2e2-10f08b86df28
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364277145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2364277145 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.1060271307
Short name	T3
Test name
Test status
Simulation time	13604980 ps
CPU time	0.78 seconds
Started	Dec 24 12:31:46 PM PST 23
Finished	Dec 24 12:32:19 PM PST 23
Peak memory	216548 kb
Host	smart-857dd1cc-4386-43bb-acf5-54799627b0c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060271307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1060271307 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.73177379
Short name	T130
Test name
Test status
Simulation time	235006727 ps
CPU time	2.71 seconds
Started	Dec 24 12:29:40 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	217524 kb
Host	smart-a507f36d-6b28-4163-ba77-b64b60cec519
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73177379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_ outstanding.73177379 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.616882433
Short name	T92
Test name
Test status
Simulation time	43514828 ps
CPU time	1.23 seconds
Started	Dec 24 12:29:57 PM PST 23
Finished	Dec 24 12:30:29 PM PST 23
Peak memory	225088 kb
Host	smart-2d30970c-4180-4d1b-852a-9aa7564f74a4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616882433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_ errors.616882433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.702149662
Short name	T82
Test name
Test status
Simulation time	122959037 ps
CPU time	3.05 seconds
Started	Dec 24 12:30:17 PM PST 23
Finished	Dec 24 12:30:42 PM PST 23
Peak memory	220864 kb
Host	smart-5b939386-6a79-4e3a-8d59-db4d6ce21516
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702149662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac _shadow_reg_errors_with_csr_rw.702149662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2912300412
Short name	T121
Test name
Test status
Simulation time	100580126 ps
CPU time	2.68 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:46 PM PST 23
Peak memory	216984 kb
Host	smart-be62ce8d-ad17-4c7c-afd0-344286a3488c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912300412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2912300412 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.826051896
Short name	T67
Test name
Test status
Simulation time	59780522 ps
CPU time	1.69 seconds
Started	Dec 24 12:30:31 PM PST 23
Finished	Dec 24 12:30:59 PM PST 23
Peak memory	220200 kb
Host	smart-c7f21b84-6b54-4358-b6e0-8231d3dd0cbb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826051896 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.826051896 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.853326366
Short name	T1166
Test name
Test status
Simulation time	22529341 ps
CPU time	0.97 seconds
Started	Dec 24 12:30:18 PM PST 23
Finished	Dec 24 12:30:41 PM PST 23
Peak memory	217352 kb
Host	smart-f5e8c77e-bd8a-41c8-a972-d1c6d4f4d0dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853326366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.853326366 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.118629431
Short name	T1185
Test name
Test status
Simulation time	69363928 ps
CPU time	0.79 seconds
Started	Dec 24 12:30:17 PM PST 23
Finished	Dec 24 12:30:40 PM PST 23
Peak memory	217324 kb
Host	smart-e61aa80a-68e1-40c0-bb0b-28eb071fcf7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118629431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.118629431 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3793135242
Short name	T1258
Test name
Test status
Simulation time	779184173 ps
CPU time	2.77 seconds
Started	Dec 24 12:31:29 PM PST 23
Finished	Dec 24 12:31:56 PM PST 23
Peak memory	217532 kb
Host	smart-f62f77a2-49e2-4036-99be-058b693407d0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793135242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.3793135242 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3109521449
Short name	T53
Test name
Test status
Simulation time	82226291 ps
CPU time	1.09 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	218148 kb
Host	smart-1e8f0b78-756b-44f5-bd49-04aa808f794d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109521449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.3109521449 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1670447693
Short name	T81
Test name
Test status
Simulation time	69967061 ps
CPU time	1.97 seconds
Started	Dec 24 12:30:39 PM PST 23
Finished	Dec 24 12:31:09 PM PST 23
Peak memory	221048 kb
Host	smart-c7c413ed-0068-4a34-a642-d42f78b3ac8e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670447693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.1670447693 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2593568868
Short name	T1175
Test name
Test status
Simulation time	31882866 ps
CPU time	2.04 seconds
Started	Dec 24 12:30:39 PM PST 23
Finished	Dec 24 12:31:08 PM PST 23
Peak memory	216004 kb
Host	smart-151b2346-e9a8-447c-bd25-4d6d5f4f3b5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593568868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2593568868 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3349238278
Short name	T63
Test name
Test status
Simulation time	92315587 ps
CPU time	1.41 seconds
Started	Dec 24 12:30:22 PM PST 23
Finished	Dec 24 12:30:46 PM PST 23
Peak memory	218584 kb
Host	smart-73097f48-0f1c-41af-b075-2f40d3479e0d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349238278 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3349238278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.1007179783
Short name	T112
Test name
Test status
Simulation time	14926600 ps
CPU time	0.94 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	217380 kb
Host	smart-e09808a8-d125-4677-9166-70e4c582f7de
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007179783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1007179783 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.3320305960
Short name	T142
Test name
Test status
Simulation time	13300322 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:12 PM PST 23
Finished	Dec 24 12:31:33 PM PST 23
Peak memory	217108 kb
Host	smart-e64205b4-cbd7-4ef7-90d7-d8908c3a0444
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320305960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3320305960 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2681545717
Short name	T114
Test name
Test status
Simulation time	92600140 ps
CPU time	2.57 seconds
Started	Dec 24 12:30:24 PM PST 23
Finished	Dec 24 12:30:51 PM PST 23
Peak memory	217592 kb
Host	smart-7ac1cabe-29ed-4067-8c33-54fe4b19a4a9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681545717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2681545717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1021896852
Short name	T1253
Test name
Test status
Simulation time	139905763 ps
CPU time	1.29 seconds
Started	Dec 24 12:30:42 PM PST 23
Finished	Dec 24 12:31:10 PM PST 23
Peak memory	218168 kb
Host	smart-700b7d26-9fa8-4e3d-bbac-77d3e0d00667
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021896852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.1021896852 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2503378276
Short name	T1203
Test name
Test status
Simulation time	507281226 ps
CPU time	3.01 seconds
Started	Dec 24 12:30:16 PM PST 23
Finished	Dec 24 12:30:42 PM PST 23
Peak memory	221420 kb
Host	smart-981df463-6fea-4929-926f-fb69986d0334
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503378276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.2503378276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.445423205
Short name	T1226
Test name
Test status
Simulation time	49946366 ps
CPU time	1.81 seconds
Started	Dec 24 12:29:41 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	216720 kb
Host	smart-aa5e4835-a245-4a71-895f-6ede8d9b8a5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445423205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.445423205 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3998319861
Short name	T65
Test name
Test status
Simulation time	1055131963 ps
CPU time	5.01 seconds
Started	Dec 24 12:31:35 PM PST 23
Finished	Dec 24 12:32:05 PM PST 23
Peak memory	217476 kb
Host	smart-7520e560-498d-4fab-bf7f-5c685e192eeb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998319861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3998 319861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4065764991
Short name	T58
Test name
Test status
Simulation time	78411166 ps
CPU time	1.54 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	224728 kb
Host	smart-93a96280-c476-4c3a-b383-ef1766f72568
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065764991 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.4065764991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1354621640
Short name	T1184
Test name
Test status
Simulation time	232161606 ps
CPU time	1.05 seconds
Started	Dec 24 12:30:23 PM PST 23
Finished	Dec 24 12:30:46 PM PST 23
Peak memory	217552 kb
Host	smart-c98a5b9d-4d1b-4941-886a-3ff070e9dd1c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354621640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1354621640 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1930676391
Short name	T1211
Test name
Test status
Simulation time	24491926 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:57 PM PST 23
Finished	Dec 24 12:30:24 PM PST 23
Peak memory	217440 kb
Host	smart-b16a603d-76eb-4aa1-8d52-9d090aa9139b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930676391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1930676391 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3152680981
Short name	T1149
Test name
Test status
Simulation time	47008175 ps
CPU time	1.68 seconds
Started	Dec 24 12:29:54 PM PST 23
Finished	Dec 24 12:30:21 PM PST 23
Peak memory	217512 kb
Host	smart-a7ebb926-368f-4171-a725-d9d0bc0cb717
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152680981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.3152680981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3814748772
Short name	T83
Test name
Test status
Simulation time	105331382 ps
CPU time	1.36 seconds
Started	Dec 24 12:31:40 PM PST 23
Finished	Dec 24 12:32:09 PM PST 23
Peak memory	218912 kb
Host	smart-9fb1a1ca-6ed8-411c-b9e3-0d82cd856141
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814748772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.3814748772 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4153622940
Short name	T1201
Test name
Test status
Simulation time	162722388 ps
CPU time	2.57 seconds
Started	Dec 24 12:29:38 PM PST 23
Finished	Dec 24 12:29:59 PM PST 23
Peak memory	220516 kb
Host	smart-2d5fd423-efbf-409b-9257-a345f8b105fc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153622940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.4153622940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.3911728033
Short name	T1190
Test name
Test status
Simulation time	72110992 ps
CPU time	2.07 seconds
Started	Dec 24 12:30:33 PM PST 23
Finished	Dec 24 12:31:01 PM PST 23
Peak memory	217772 kb
Host	smart-d27b7b3b-e0cd-4f55-9261-354243802542
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911728033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3911728033 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1610865969
Short name	T1193
Test name
Test status
Simulation time	195163757 ps
CPU time	2.95 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	216860 kb
Host	smart-bc27140e-a321-4bff-acd3-43416e823b5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610865969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1610 865969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1128322065
Short name	T1231
Test name
Test status
Simulation time	63592087 ps
CPU time	1.5 seconds
Started	Dec 24 12:29:43 PM PST 23
Finished	Dec 24 12:30:04 PM PST 23
Peak memory	218592 kb
Host	smart-75643350-5caf-476d-9fc7-f2cc70d2dcc6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128322065 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1128322065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1997465602
Short name	T127
Test name
Test status
Simulation time	27851749 ps
CPU time	1.11 seconds
Started	Dec 24 12:29:40 PM PST 23
Finished	Dec 24 12:30:01 PM PST 23
Peak memory	217652 kb
Host	smart-778d78b0-7520-4951-b3e8-8f95bab440df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997465602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1997465602 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.3993661456
Short name	T1179
Test name
Test status
Simulation time	59944885 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:41 PM PST 23
Finished	Dec 24 12:30:02 PM PST 23
Peak memory	216536 kb
Host	smart-563134d2-20b3-412c-9e0b-32528978f974
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993661456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3993661456 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2124165383
Short name	T118
Test name
Test status
Simulation time	39595966 ps
CPU time	1.48 seconds
Started	Dec 24 12:29:53 PM PST 23
Finished	Dec 24 12:30:20 PM PST 23
Peak memory	216832 kb
Host	smart-b0101a98-63ef-4204-a13e-da1f6f47ed06
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124165383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2124165383 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1396206774
Short name	T1177
Test name
Test status
Simulation time	57856154 ps
CPU time	1 seconds
Started	Dec 24 12:30:09 PM PST 23
Finished	Dec 24 12:30:35 PM PST 23
Peak memory	224800 kb
Host	smart-68cfcb31-91e2-44d9-8af2-14c7267e9574
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396206774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.1396206774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.966890044
Short name	T1237
Test name
Test status
Simulation time	105288667 ps
CPU time	2.69 seconds
Started	Dec 24 12:29:50 PM PST 23
Finished	Dec 24 12:30:17 PM PST 23
Peak memory	220248 kb
Host	smart-823b7ab0-0194-4c0f-840b-196e9cd63ae6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966890044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac _shadow_reg_errors_with_csr_rw.966890044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2675415059
Short name	T1148
Test name
Test status
Simulation time	1011196034 ps
CPU time	2.22 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	217764 kb
Host	smart-6197c377-7967-41dd-8de9-5da7285ea20a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675415059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2675415059 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1062843170
Short name	T154
Test name
Test status
Simulation time	102100565 ps
CPU time	2.91 seconds
Started	Dec 24 12:30:05 PM PST 23
Finished	Dec 24 12:30:33 PM PST 23
Peak memory	217672 kb
Host	smart-fe1ded1e-7ceb-4625-bd8b-88aabbd98e04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062843170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1062 843170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.223923482
Short name	T60
Test name
Test status
Simulation time	36163723 ps
CPU time	1.46 seconds
Started	Dec 24 12:29:35 PM PST 23
Finished	Dec 24 12:29:50 PM PST 23
Peak memory	222004 kb
Host	smart-fa9d6930-2c4a-419b-9f25-5e4e4d10690a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223923482 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.223923482 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.585924754
Short name	T1259
Test name
Test status
Simulation time	38877402 ps
CPU time	0.99 seconds
Started	Dec 24 12:29:47 PM PST 23
Finished	Dec 24 12:30:11 PM PST 23
Peak memory	217552 kb
Host	smart-a3f828ce-c819-4d7d-8852-c9beb80d208d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585924754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.585924754 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3346534659
Short name	T2
Test name
Test status
Simulation time	43553459 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:38 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	217432 kb
Host	smart-80403a6f-4266-4102-a5f0-b699df2a1e86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346534659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3346534659 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2989121663
Short name	T1172
Test name
Test status
Simulation time	81263989 ps
CPU time	1.52 seconds
Started	Dec 24 12:30:17 PM PST 23
Finished	Dec 24 12:30:41 PM PST 23
Peak memory	217560 kb
Host	smart-4f7983bc-2165-4327-848c-40b90228cbe4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989121663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.2989121663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1530236471
Short name	T1208
Test name
Test status
Simulation time	93219456 ps
CPU time	0.81 seconds
Started	Dec 24 12:30:05 PM PST 23
Finished	Dec 24 12:30:31 PM PST 23
Peak memory	219796 kb
Host	smart-455ca23a-23cc-4910-b3b3-f9316b5feab3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530236471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.1530236471 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1207545622
Short name	T62
Test name
Test status
Simulation time	490735078 ps
CPU time	2.7 seconds
Started	Dec 24 12:29:53 PM PST 23
Finished	Dec 24 12:30:22 PM PST 23
Peak memory	220344 kb
Host	smart-c09983e7-0145-4a11-bb05-196d855b843f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207545622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1207545622 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2903953501
Short name	T1182
Test name
Test status
Simulation time	47321145 ps
CPU time	1.82 seconds
Started	Dec 24 12:29:35 PM PST 23
Finished	Dec 24 12:29:50 PM PST 23
Peak memory	216916 kb
Host	smart-40d03052-aaad-42dd-8ae5-e6d2feeb2dd8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903953501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2903953501 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2767031212
Short name	T1246
Test name
Test status
Simulation time	29564745 ps
CPU time	1.7 seconds
Started	Dec 24 12:29:54 PM PST 23
Finished	Dec 24 12:30:21 PM PST 23
Peak memory	218548 kb
Host	smart-d21bfcb1-d9f2-4407-953e-7e5bb9408bf9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767031212 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2767031212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1771023565
Short name	T1207
Test name
Test status
Simulation time	23583555 ps
CPU time	1.06 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:52 PM PST 23
Peak memory	217248 kb
Host	smart-eea5fa3a-f15e-4d0e-b38b-6c970a50e80c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771023565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1771023565 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.4284910250
Short name	T1264
Test name
Test status
Simulation time	16869207 ps
CPU time	0.78 seconds
Started	Dec 24 12:31:14 PM PST 23
Finished	Dec 24 12:31:37 PM PST 23
Peak memory	217344 kb
Host	smart-ecdc988f-6415-4a9f-a70b-1c1059392331
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284910250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.4284910250 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4018609802
Short name	T174
Test name
Test status
Simulation time	79336947 ps
CPU time	2.47 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:58 PM PST 23
Peak memory	217572 kb
Host	smart-4e2e2b99-1746-4d90-8f54-3ef59b99ca08
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018609802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.4018609802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.986868128
Short name	T1200
Test name
Test status
Simulation time	562780835 ps
CPU time	1.38 seconds
Started	Dec 24 12:30:34 PM PST 23
Finished	Dec 24 12:31:02 PM PST 23
Peak memory	216752 kb
Host	smart-7151b3cd-2ba3-434d-94a4-6575e62c91a0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986868128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_ errors.986868128 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.62500170
Short name	T1155
Test name
Test status
Simulation time	518560818 ps
CPU time	2.51 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:54 PM PST 23
Peak memory	225008 kb
Host	smart-ef8996eb-fdeb-4f20-a83b-26ce109237ef
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62500170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_ shadow_reg_errors_with_csr_rw.62500170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3968313673
Short name	T1156
Test name
Test status
Simulation time	38747224 ps
CPU time	2.65 seconds
Started	Dec 24 12:30:25 PM PST 23
Finished	Dec 24 12:30:52 PM PST 23
Peak memory	217768 kb
Host	smart-c5a17ca5-da3b-465f-834d-68b952094568
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968313673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3968313673 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4000587277
Short name	T1224
Test name
Test status
Simulation time	287039783 ps
CPU time	5.18 seconds
Started	Dec 24 12:29:44 PM PST 23
Finished	Dec 24 12:30:11 PM PST 23
Peak memory	217616 kb
Host	smart-55d90b22-c174-4f75-9dec-6b3fe1e5aca5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000587277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4000 587277 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4274833511
Short name	T1163
Test name
Test status
Simulation time	109871370 ps
CPU time	1.75 seconds
Started	Dec 24 12:30:57 PM PST 23
Finished	Dec 24 12:31:20 PM PST 23
Peak memory	222388 kb
Host	smart-031c92b9-bd56-4fab-a7d6-4a2c99cdf856
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274833511 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.4274833511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.2189525477
Short name	T1188
Test name
Test status
Simulation time	33649452 ps
CPU time	1.22 seconds
Started	Dec 24 12:31:30 PM PST 23
Finished	Dec 24 12:31:56 PM PST 23
Peak memory	217532 kb
Host	smart-dd302deb-cf30-43f0-98db-8c174b21a9d4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189525477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2189525477 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3169707286
Short name	T1240
Test name
Test status
Simulation time	44842630 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:15 PM PST 23
Finished	Dec 24 12:31:38 PM PST 23
Peak memory	217348 kb
Host	smart-4b6f5a03-9053-44cd-83f0-552b6ee4a455
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169707286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3169707286 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1642636650
Short name	T1238
Test name
Test status
Simulation time	104253388 ps
CPU time	1.37 seconds
Started	Dec 24 12:30:21 PM PST 23
Finished	Dec 24 12:30:44 PM PST 23
Peak memory	217492 kb
Host	smart-1dba6a3a-5124-4987-b6a5-4b339e6228cc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642636650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.1642636650 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1130093095
Short name	T1244
Test name
Test status
Simulation time	35656747 ps
CPU time	1 seconds
Started	Dec 24 12:29:56 PM PST 23
Finished	Dec 24 12:30:23 PM PST 23
Peak memory	224736 kb
Host	smart-de495d6b-7fd8-436e-ae70-c4150a5814f1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130093095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1130093095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3053115335
Short name	T1222
Test name
Test status
Simulation time	237481487 ps
CPU time	3.18 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	221216 kb
Host	smart-bbbd33b1-1889-4331-a163-298165c2622a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053115335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.3053115335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1566889962
Short name	T1160
Test name
Test status
Simulation time	942842026 ps
CPU time	3.34 seconds
Started	Dec 24 12:31:11 PM PST 23
Finished	Dec 24 12:31:35 PM PST 23
Peak memory	217972 kb
Host	smart-aacc0806-5abc-4f97-9336-5019b7569a72
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566889962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1566889962 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3234839441
Short name	T148
Test name
Test status
Simulation time	103995474 ps
CPU time	4.28 seconds
Started	Dec 24 12:30:19 PM PST 23
Finished	Dec 24 12:30:45 PM PST 23
Peak memory	216816 kb
Host	smart-da1b1680-cb9a-49ab-9199-17cc6b9cbbee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234839441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3234 839441 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3844456682
Short name	T54
Test name
Test status
Simulation time	73305602 ps
CPU time	1.57 seconds
Started	Dec 24 12:30:24 PM PST 23
Finished	Dec 24 12:30:49 PM PST 23
Peak memory	218684 kb
Host	smart-5b5793ef-69c4-484e-95de-c7b6f55b19b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844456682 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3844456682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2904988436
Short name	T1145
Test name
Test status
Simulation time	51886972 ps
CPU time	1.2 seconds
Started	Dec 24 12:30:26 PM PST 23
Finished	Dec 24 12:30:51 PM PST 23
Peak memory	217592 kb
Host	smart-342a1842-5591-4b1a-877e-3c09fb8d4428
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904988436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2904988436 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.1236162936
Short name	T1212
Test name
Test status
Simulation time	14432940 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:15 PM PST 23
Finished	Dec 24 12:31:39 PM PST 23
Peak memory	217272 kb
Host	smart-4ee86bd5-02ef-46f8-b146-e4b30d2270b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236162936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1236162936 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.233633169
Short name	T1252
Test name
Test status
Simulation time	67375579 ps
CPU time	2.15 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:53 PM PST 23
Peak memory	216660 kb
Host	smart-3d65683e-df0a-42e8-998b-40c777da28bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233633169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.233633169 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1691536492
Short name	T89
Test name
Test status
Simulation time	157275077 ps
CPU time	2.43 seconds
Started	Dec 24 12:30:08 PM PST 23
Finished	Dec 24 12:30:35 PM PST 23
Peak memory	225140 kb
Host	smart-280aa44a-a9aa-48f5-bcff-db128d520f50
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691536492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.1691536492 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3737034914
Short name	T1194
Test name
Test status
Simulation time	132234654 ps
CPU time	2.52 seconds
Started	Dec 24 12:31:13 PM PST 23
Finished	Dec 24 12:31:37 PM PST 23
Peak memory	216896 kb
Host	smart-780d07e6-021d-42fa-b0cb-19944588d4c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737034914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3737034914 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4205416838
Short name	T47
Test name
Test status
Simulation time	894737163 ps
CPU time	3.08 seconds
Started	Dec 24 12:31:04 PM PST 23
Finished	Dec 24 12:31:26 PM PST 23
Peak memory	217564 kb
Host	smart-1cd40e76-a7a5-4603-b01f-4e50e499c3eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205416838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4205 416838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.4113193129
Short name	T1236
Test name
Test status
Simulation time	80794820 ps
CPU time	4.92 seconds
Started	Dec 24 12:30:04 PM PST 23
Finished	Dec 24 12:30:34 PM PST 23
Peak memory	217520 kb
Host	smart-2db0014e-6cd9-4ea7-a4f1-2bf8ee94cc18
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113193129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.4113193 129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3879099196
Short name	T1152
Test name
Test status
Simulation time	806066188 ps
CPU time	8.97 seconds
Started	Dec 24 12:30:23 PM PST 23
Finished	Dec 24 12:30:55 PM PST 23
Peak memory	217584 kb
Host	smart-70426fcc-c781-4429-ab15-cfa999816f29
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879099196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3879099 196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4150231281
Short name	T1249
Test name
Test status
Simulation time	42171432 ps
CPU time	1.02 seconds
Started	Dec 24 12:30:43 PM PST 23
Finished	Dec 24 12:31:10 PM PST 23
Peak memory	217392 kb
Host	smart-6346e968-cdd8-4153-83ec-7ccaaf406dec
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150231281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4150231 281 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.202121746
Short name	T1223
Test name
Test status
Simulation time	44471700 ps
CPU time	1.45 seconds
Started	Dec 24 12:30:51 PM PST 23
Finished	Dec 24 12:31:16 PM PST 23
Peak memory	220680 kb
Host	smart-b0d691a0-203c-461c-a6b7-b2e7683fe067
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202121746 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.202121746 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2747396258
Short name	T126
Test name
Test status
Simulation time	28648168 ps
CPU time	1.17 seconds
Started	Dec 24 12:30:27 PM PST 23
Finished	Dec 24 12:30:53 PM PST 23
Peak memory	217584 kb
Host	smart-04913f72-208e-49e4-83dd-7dcf12a6d959
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747396258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2747396258 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3048884137
Short name	T120
Test name
Test status
Simulation time	21533072 ps
CPU time	0.82 seconds
Started	Dec 24 12:30:34 PM PST 23
Finished	Dec 24 12:31:01 PM PST 23
Peak memory	216616 kb
Host	smart-10dbad66-c4a8-4811-9eb5-1baa421efe45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048884137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3048884137 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.4052114353
Short name	T123
Test name
Test status
Simulation time	89737232 ps
CPU time	1.19 seconds
Started	Dec 24 12:30:55 PM PST 23
Finished	Dec 24 12:31:18 PM PST 23
Peak memory	217532 kb
Host	smart-29ce3b89-026d-4ad8-b3d0-b7232e3a8b2d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052114353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.4052114353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.865636087
Short name	T55
Test name
Test status
Simulation time	33975255 ps
CPU time	0.72 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:45 PM PST 23
Peak memory	217248 kb
Host	smart-9b433408-46fa-4ad7-ba41-bf96f7ea3175
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865636087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.865636087 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3057561112
Short name	T1168
Test name
Test status
Simulation time	723439524 ps
CPU time	1.58 seconds
Started	Dec 24 12:30:22 PM PST 23
Finished	Dec 24 12:30:47 PM PST 23
Peak memory	218484 kb
Host	smart-c10edcdb-d621-432f-a362-180a66737932
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057561112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.3057561112 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1082380292
Short name	T57
Test name
Test status
Simulation time	40096697 ps
CPU time	2.32 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	216828 kb
Host	smart-6cde4335-3c6b-410b-8947-dbbff3b166b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082380292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1082380292 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1904038349
Short name	T153
Test name
Test status
Simulation time	402017180 ps
CPU time	5.08 seconds
Started	Dec 24 12:30:42 PM PST 23
Finished	Dec 24 12:31:13 PM PST 23
Peak memory	216896 kb
Host	smart-974be853-d86c-4316-9542-69a03c1a0f44
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904038349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.19040 38349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3149272100
Short name	T1189
Test name
Test status
Simulation time	126755946 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:44 PM PST 23
Finished	Dec 24 12:30:07 PM PST 23
Peak memory	217428 kb
Host	smart-287d031f-cc77-4f01-a402-659a85d23f98
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149272100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3149272100 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.246741805
Short name	T1247
Test name
Test status
Simulation time	23634343 ps
CPU time	0.76 seconds
Started	Dec 24 12:31:12 PM PST 23
Finished	Dec 24 12:31:34 PM PST 23
Peak memory	217484 kb
Host	smart-64e771bf-2198-4cd1-9070-6c41aae2f6fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246741805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.246741805 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.3826031814
Short name	T145
Test name
Test status
Simulation time	46390838 ps
CPU time	0.85 seconds
Started	Dec 24 12:31:06 PM PST 23
Finished	Dec 24 12:31:25 PM PST 23
Peak memory	217432 kb
Host	smart-5c13cdd0-c3b1-4988-bb25-ea14e7f62449
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826031814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3826031814 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.693203197
Short name	T1221
Test name
Test status
Simulation time	15421121 ps
CPU time	0.79 seconds
Started	Dec 24 12:30:20 PM PST 23
Finished	Dec 24 12:30:43 PM PST 23
Peak memory	216620 kb
Host	smart-eab53b92-1163-4122-8148-ca83eafa4b6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693203197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.693203197 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.3385202471
Short name	T170
Test name
Test status
Simulation time	18321538 ps
CPU time	0.79 seconds
Started	Dec 24 12:30:46 PM PST 23
Finished	Dec 24 12:31:12 PM PST 23
Peak memory	217344 kb
Host	smart-11acf427-fa58-4a2f-bab8-17e0e53ed33a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385202471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3385202471 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.2644636232
Short name	T1169
Test name
Test status
Simulation time	50929064 ps
CPU time	0.8 seconds
Started	Dec 24 12:30:22 PM PST 23
Finished	Dec 24 12:30:45 PM PST 23
Peak memory	217424 kb
Host	smart-2650233a-6737-4b42-bacf-b1a8490d6838
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644636232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2644636232 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.2033372014
Short name	T1235
Test name
Test status
Simulation time	93555827 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:11 PM PST 23
Finished	Dec 24 12:31:32 PM PST 23
Peak memory	217364 kb
Host	smart-bac6b455-0a86-436a-9f45-6390b7151647
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033372014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2033372014 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.4178220526
Short name	T1234
Test name
Test status
Simulation time	79171673 ps
CPU time	0.82 seconds
Started	Dec 24 12:31:15 PM PST 23
Finished	Dec 24 12:31:38 PM PST 23
Peak memory	217440 kb
Host	smart-fd03843c-02ec-4b91-aa8d-d2ccf617867c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178220526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.4178220526 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.1634298749
Short name	T166
Test name
Test status
Simulation time	13571683 ps
CPU time	0.78 seconds
Started	Dec 24 12:30:04 PM PST 23
Finished	Dec 24 12:30:30 PM PST 23
Peak memory	217388 kb
Host	smart-81b42bae-bb93-46b2-b2fb-8b3573a57160
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634298749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1634298749 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1765266868
Short name	T1158
Test name
Test status
Simulation time	240741521 ps
CPU time	5.59 seconds
Started	Dec 24 12:30:52 PM PST 23
Finished	Dec 24 12:31:20 PM PST 23
Peak memory	217604 kb
Host	smart-148a4a1a-4884-4797-81fd-79bc97ce96fc
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765266868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1765266 868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2532550168
Short name	T131
Test name
Test status
Simulation time	775949471 ps
CPU time	11.49 seconds
Started	Dec 24 12:31:01 PM PST 23
Finished	Dec 24 12:31:32 PM PST 23
Peak memory	217552 kb
Host	smart-581008a5-a856-4957-bce6-86bad01d0f06
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532550168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2532550 168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4211552987
Short name	T1150
Test name
Test status
Simulation time	16942821 ps
CPU time	1.02 seconds
Started	Dec 24 12:31:01 PM PST 23
Finished	Dec 24 12:31:22 PM PST 23
Peak memory	216472 kb
Host	smart-f2ac0294-cd98-4551-a0e7-6ef17ee26008
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211552987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4211552 987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3947441932
Short name	T1183
Test name
Test status
Simulation time	169054374 ps
CPU time	1.7 seconds
Started	Dec 24 12:31:30 PM PST 23
Finished	Dec 24 12:31:56 PM PST 23
Peak memory	221896 kb
Host	smart-00befb7c-d20c-4b65-9e4c-e3f398d205e8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947441932 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3947441932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1869343709
Short name	T1161
Test name
Test status
Simulation time	38567440 ps
CPU time	1 seconds
Started	Dec 24 12:29:53 PM PST 23
Finished	Dec 24 12:30:19 PM PST 23
Peak memory	217448 kb
Host	smart-7a3251d3-9b68-4b02-9044-0d7da14aa773
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869343709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1869343709 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.3253577475
Short name	T144
Test name
Test status
Simulation time	80483077 ps
CPU time	0.81 seconds
Started	Dec 24 12:30:25 PM PST 23
Finished	Dec 24 12:30:50 PM PST 23
Peak memory	217340 kb
Host	smart-ff3a34b7-fd89-434f-9350-b41aaae199cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253577475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3253577475 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3709874948
Short name	T1218
Test name
Test status
Simulation time	15131858 ps
CPU time	0.75 seconds
Started	Dec 24 12:31:08 PM PST 23
Finished	Dec 24 12:31:27 PM PST 23
Peak memory	217240 kb
Host	smart-abf99ed7-316b-4f88-b97d-02b1e9586411
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709874948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3709874948 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2869072493
Short name	T167
Test name
Test status
Simulation time	452972708 ps
CPU time	1.87 seconds
Started	Dec 24 12:30:46 PM PST 23
Finished	Dec 24 12:31:13 PM PST 23
Peak memory	217444 kb
Host	smart-d17de4dd-9205-458c-8594-cb9000b4ce80
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869072493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.2869072493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2026267769
Short name	T1197
Test name
Test status
Simulation time	82995853 ps
CPU time	1.15 seconds
Started	Dec 24 12:31:11 PM PST 23
Finished	Dec 24 12:31:31 PM PST 23
Peak memory	217572 kb
Host	smart-46a72e15-ac71-4fc2-b025-99da45237ad8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026267769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.2026267769 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4037597293
Short name	T1215
Test name
Test status
Simulation time	208928985 ps
CPU time	2.45 seconds
Started	Dec 24 12:29:54 PM PST 23
Finished	Dec 24 12:30:22 PM PST 23
Peak memory	220384 kb
Host	smart-9d68866b-baf8-46a9-9269-27efd5dad1b8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037597293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.4037597293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2241223626
Short name	T61
Test name
Test status
Simulation time	36833132 ps
CPU time	2.2 seconds
Started	Dec 24 12:31:02 PM PST 23
Finished	Dec 24 12:31:24 PM PST 23
Peak memory	217788 kb
Host	smart-c1375ce2-2e7f-4ddf-a52f-ed25334e1d03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241223626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2241223626 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3407216729
Short name	T150
Test name
Test status
Simulation time	244801641 ps
CPU time	5.32 seconds
Started	Dec 24 12:29:39 PM PST 23
Finished	Dec 24 12:30:04 PM PST 23
Peak memory	217216 kb
Host	smart-34e1b21d-99d2-45d0-bea7-91d77260089c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407216729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.34072 16729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.3541602984
Short name	T169
Test name
Test status
Simulation time	15169623 ps
CPU time	0.81 seconds
Started	Dec 24 12:31:18 PM PST 23
Finished	Dec 24 12:31:42 PM PST 23
Peak memory	217340 kb
Host	smart-9bf2ec7d-60ed-439c-813c-b2a764d18dad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541602984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3541602984 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2707145992
Short name	T1241
Test name
Test status
Simulation time	41818881 ps
CPU time	0.87 seconds
Started	Dec 24 12:31:16 PM PST 23
Finished	Dec 24 12:31:40 PM PST 23
Peak memory	217272 kb
Host	smart-41e90f5a-cbad-43b2-9f48-94e5368ed603
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707145992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2707145992 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.1500803308
Short name	T165
Test name
Test status
Simulation time	34342004 ps
CPU time	0.81 seconds
Started	Dec 24 12:31:04 PM PST 23
Finished	Dec 24 12:31:24 PM PST 23
Peak memory	216664 kb
Host	smart-260d786e-2c6e-4f0f-bf63-d459d261e677
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500803308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1500803308 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2165248503
Short name	T1180
Test name
Test status
Simulation time	18341320 ps
CPU time	0.78 seconds
Started	Dec 24 12:33:08 PM PST 23
Finished	Dec 24 12:33:50 PM PST 23
Peak memory	216804 kb
Host	smart-08e3124d-4305-45bd-906b-feee00dfb05d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165248503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2165248503 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3685762381
Short name	T162
Test name
Test status
Simulation time	28074486 ps
CPU time	0.78 seconds
Started	Dec 24 12:30:24 PM PST 23
Finished	Dec 24 12:30:48 PM PST 23
Peak memory	216576 kb
Host	smart-2751fc2f-f00d-4d0f-baac-9711dd83f84c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685762381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3685762381 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.2449684250
Short name	T1251
Test name
Test status
Simulation time	102437909 ps
CPU time	0.82 seconds
Started	Dec 24 12:30:34 PM PST 23
Finished	Dec 24 12:31:02 PM PST 23
Peak memory	215300 kb
Host	smart-033a4170-6ff4-4d6f-bb92-733c28104909
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449684250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2449684250 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.4048630038
Short name	T1153
Test name
Test status
Simulation time	32133481 ps
CPU time	0.76 seconds
Started	Dec 24 12:33:39 PM PST 23
Finished	Dec 24 12:34:16 PM PST 23
Peak memory	217212 kb
Host	smart-f3995fc4-4442-4704-979b-e315af7690fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048630038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.4048630038 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1698531339
Short name	T1227
Test name
Test status
Simulation time	54911570 ps
CPU time	0.82 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:56 PM PST 23
Peak memory	216536 kb
Host	smart-956c8c0a-7cae-48ca-8dba-180ff677201d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698531339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1698531339 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.3695384187
Short name	T1147
Test name
Test status
Simulation time	38789014 ps
CPU time	0.76 seconds
Started	Dec 24 12:31:18 PM PST 23
Finished	Dec 24 12:31:42 PM PST 23
Peak memory	217340 kb
Host	smart-62f2afd0-b96f-455c-b885-45c8ed6c12b3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695384187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3695384187 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3391962597
Short name	T111
Test name
Test status
Simulation time	313325744 ps
CPU time	8.87 seconds
Started	Dec 24 12:29:44 PM PST 23
Finished	Dec 24 12:30:15 PM PST 23
Peak memory	216764 kb
Host	smart-77cab3df-86bb-4de7-b554-23b11ef489ac
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391962597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3391962 597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1224916402
Short name	T1204
Test name
Test status
Simulation time	6194208932 ps
CPU time	23.76 seconds
Started	Dec 24 12:29:29 PM PST 23
Finished	Dec 24 12:30:04 PM PST 23
Peak memory	217628 kb
Host	smart-c8b7af51-c736-4213-8858-a0de246a50ca
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224916402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1224916 402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3052751480
Short name	T113
Test name
Test status
Simulation time	24383757 ps
CPU time	1.13 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:51 PM PST 23
Peak memory	217464 kb
Host	smart-5b2a7b1d-284b-4e48-bc17-5f68bc85dbc0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052751480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3052751 480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1158684712
Short name	T1167
Test name
Test status
Simulation time	31149226 ps
CPU time	2.33 seconds
Started	Dec 24 12:29:25 PM PST 23
Finished	Dec 24 12:29:36 PM PST 23
Peak memory	222828 kb
Host	smart-df11a4a9-1142-404e-b7b7-6104d728f9ef
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158684712 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1158684712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.611002225
Short name	T117
Test name
Test status
Simulation time	343105987 ps
CPU time	1.15 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	216992 kb
Host	smart-7964a3d7-a6a2-45aa-9caa-ac45794b285e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611002225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.611002225 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.1891174526
Short name	T124
Test name
Test status
Simulation time	14468486 ps
CPU time	0.81 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	216548 kb
Host	smart-11ca8a5b-87b2-45c6-bbe6-027f04620e66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891174526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1891174526 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1797458847
Short name	T1173
Test name
Test status
Simulation time	47414400 ps
CPU time	1.18 seconds
Started	Dec 24 12:29:27 PM PST 23
Finished	Dec 24 12:29:38 PM PST 23
Peak memory	217500 kb
Host	smart-89b5156e-80ac-4fdb-91f3-65670e1e30b1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797458847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.1797458847 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1776089445
Short name	T1248
Test name
Test status
Simulation time	44697732 ps
CPU time	0.72 seconds
Started	Dec 24 12:29:27 PM PST 23
Finished	Dec 24 12:29:40 PM PST 23
Peak memory	217144 kb
Host	smart-bc68bec5-8383-465f-b57f-73970e196855
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776089445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1776089445 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2027388013
Short name	T1195
Test name
Test status
Simulation time	283288949 ps
CPU time	1.88 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	217656 kb
Host	smart-8bd02dce-5058-48cb-8c6d-694424517baa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027388013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2027388013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2701885722
Short name	T84
Test name
Test status
Simulation time	27293229 ps
CPU time	1.22 seconds
Started	Dec 24 12:33:47 PM PST 23
Finished	Dec 24 12:34:24 PM PST 23
Peak memory	218028 kb
Host	smart-94187ce5-5c83-4d64-bc2b-6d289ee800a3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701885722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2701885722 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4173019869
Short name	T168
Test name
Test status
Simulation time	106842510 ps
CPU time	1.59 seconds
Started	Dec 24 12:32:04 PM PST 23
Finished	Dec 24 12:32:32 PM PST 23
Peak memory	217940 kb
Host	smart-34007be8-eaeb-4682-bac5-7d8e12ee0fa8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173019869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.4173019869 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.429228086
Short name	T1159
Test name
Test status
Simulation time	246086216 ps
CPU time	2.37 seconds
Started	Dec 24 12:29:55 PM PST 23
Finished	Dec 24 12:30:24 PM PST 23
Peak memory	217636 kb
Host	smart-838a378e-d430-4c4c-819d-2e940732b1be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429228086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.429228086 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2803007511
Short name	T146
Test name
Test status
Simulation time	227983853 ps
CPU time	2.44 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:53 PM PST 23
Peak memory	216692 kb
Host	smart-02a34160-946c-4a5f-be6d-c16d54fb4556
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803007511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.28030 07511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.50885208
Short name	T141
Test name
Test status
Simulation time	48213551 ps
CPU time	0.81 seconds
Started	Dec 24 12:29:46 PM PST 23
Finished	Dec 24 12:30:09 PM PST 23
Peak memory	217304 kb
Host	smart-44f6d17e-a599-41b1-aa15-66fb9b2dd5d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50885208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.50885208 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.3482520363
Short name	T1250
Test name
Test status
Simulation time	16630641 ps
CPU time	0.84 seconds
Started	Dec 24 12:31:21 PM PST 23
Finished	Dec 24 12:31:47 PM PST 23
Peak memory	217424 kb
Host	smart-4ebf2cab-1378-42b9-a007-7fbf5b63f720
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482520363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3482520363 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.4122617372
Short name	T1196
Test name
Test status
Simulation time	23057464 ps
CPU time	0.86 seconds
Started	Dec 24 12:33:08 PM PST 23
Finished	Dec 24 12:33:50 PM PST 23
Peak memory	216492 kb
Host	smart-81bed561-8728-4e6f-984f-4c9838e34005
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122617372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.4122617372 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.3860942354
Short name	T1216
Test name
Test status
Simulation time	26636686 ps
CPU time	0.76 seconds
Started	Dec 24 12:29:55 PM PST 23
Finished	Dec 24 12:30:22 PM PST 23
Peak memory	217320 kb
Host	smart-8a53be7a-6370-4ead-bc2c-53ef12ba9e3f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860942354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3860942354 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2191656561
Short name	T116
Test name
Test status
Simulation time	23112296 ps
CPU time	0.83 seconds
Started	Dec 24 12:29:36 PM PST 23
Finished	Dec 24 12:29:52 PM PST 23
Peak memory	217364 kb
Host	smart-53a5415c-191f-4a11-9631-db7df448e4cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191656561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2191656561 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.551376906
Short name	T1230
Test name
Test status
Simulation time	23140407 ps
CPU time	0.83 seconds
Started	Dec 24 12:30:06 PM PST 23
Finished	Dec 24 12:30:32 PM PST 23
Peak memory	217352 kb
Host	smart-51aee3fb-fa16-4c11-a4bf-e1a24417c709
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551376906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.551376906 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.3759949252
Short name	T133
Test name
Test status
Simulation time	17087337 ps
CPU time	0.78 seconds
Started	Dec 24 12:30:24 PM PST 23
Finished	Dec 24 12:30:48 PM PST 23
Peak memory	217344 kb
Host	smart-bb4fff00-41f9-4553-8cf9-9fb544f13b84
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759949252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3759949252 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.1429525579
Short name	T1205
Test name
Test status
Simulation time	13196775 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:26 PM PST 23
Finished	Dec 24 12:31:53 PM PST 23
Peak memory	217344 kb
Host	smart-3a2df62c-1b6a-41ba-aa42-2400ec4568e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429525579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1429525579 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.4051801909
Short name	T1255
Test name
Test status
Simulation time	38492127 ps
CPU time	0.74 seconds
Started	Dec 24 12:31:15 PM PST 23
Finished	Dec 24 12:31:38 PM PST 23
Peak memory	216428 kb
Host	smart-3f0f0304-5f5c-487a-971c-a47cdb5629fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051801909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.4051801909 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.3846133111
Short name	T132
Test name
Test status
Simulation time	51560083 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:54 PM PST 23
Peak memory	217436 kb
Host	smart-e9cd9996-2a34-4cf6-af62-a86121ee08ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846133111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3846133111 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.199454816
Short name	T1198
Test name
Test status
Simulation time	96716693 ps
CPU time	1.85 seconds
Started	Dec 24 12:30:08 PM PST 23
Finished	Dec 24 12:30:35 PM PST 23
Peak memory	223132 kb
Host	smart-c3d6f9cf-1d8f-46a4-b826-c95103732ed8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199454816 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.199454816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3185571255
Short name	T1165
Test name
Test status
Simulation time	90780311 ps
CPU time	1.2 seconds
Started	Dec 24 12:29:43 PM PST 23
Finished	Dec 24 12:30:04 PM PST 23
Peak memory	217660 kb
Host	smart-7f7bd124-50e4-42c7-8c7a-8b51c6ff6ad6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185571255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3185571255 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1720689165
Short name	T51
Test name
Test status
Simulation time	11823527 ps
CPU time	0.79 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	216612 kb
Host	smart-f676d437-9b7a-403f-af78-46329bfaa3f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720689165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1720689165 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1263349933
Short name	T128
Test name
Test status
Simulation time	216184041 ps
CPU time	2.77 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:45 PM PST 23
Peak memory	217660 kb
Host	smart-5e6b381c-2fc1-458c-8a11-a35a42bcb6af
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263349933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.1263349933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2065762677
Short name	T1266
Test name
Test status
Simulation time	381819359 ps
CPU time	2.78 seconds
Started	Dec 24 12:29:22 PM PST 23
Finished	Dec 24 12:29:35 PM PST 23
Peak memory	220716 kb
Host	smart-eeb6706f-767c-466d-882c-acc9f90f5e9e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065762677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.2065762677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.2559912958
Short name	T56
Test name
Test status
Simulation time	133453100 ps
CPU time	2.55 seconds
Started	Dec 24 12:29:32 PM PST 23
Finished	Dec 24 12:29:49 PM PST 23
Peak memory	217788 kb
Host	smart-3d90ee45-4b78-4754-bb96-4e02efd96be2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559912958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2559912958 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2844799844
Short name	T155
Test name
Test status
Simulation time	143054634 ps
CPU time	3.39 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:45 PM PST 23
Peak memory	217556 kb
Host	smart-30f92abf-8c50-480c-90ba-79e940e4d4cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844799844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.28447 99844 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.819467142
Short name	T171
Test name
Test status
Simulation time	21707790 ps
CPU time	1.55 seconds
Started	Dec 24 12:30:13 PM PST 23
Finished	Dec 24 12:30:38 PM PST 23
Peak memory	218416 kb
Host	smart-18e1a89a-b3f9-4fa2-a9c6-d3c85ffbee78
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819467142 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.819467142 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.4252310996
Short name	T1220
Test name
Test status
Simulation time	17342434 ps
CPU time	0.94 seconds
Started	Dec 24 12:29:33 PM PST 23
Finished	Dec 24 12:29:47 PM PST 23
Peak memory	217376 kb
Host	smart-e51aab25-373b-49d0-a263-a761fbbd928c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252310996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.4252310996 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2648198018
Short name	T125
Test name
Test status
Simulation time	42154308 ps
CPU time	0.77 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	217340 kb
Host	smart-cf90becd-fb55-46e1-98dd-71e28fd36e14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648198018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2648198018 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2107365374
Short name	T1191
Test name
Test status
Simulation time	140957476 ps
CPU time	2.2 seconds
Started	Dec 24 12:29:37 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	216828 kb
Host	smart-5d83fe2b-36b7-4eb7-8010-d842af5be616
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107365374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2107365374 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3478890854
Short name	T1233
Test name
Test status
Simulation time	147313125 ps
CPU time	1.25 seconds
Started	Dec 24 12:30:03 PM PST 23
Finished	Dec 24 12:30:29 PM PST 23
Peak memory	217944 kb
Host	smart-eb3a5058-921f-495c-8fe2-f16341574c1d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478890854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.3478890854 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.232824539
Short name	T91
Test name
Test status
Simulation time	353306309 ps
CPU time	2.91 seconds
Started	Dec 24 12:30:02 PM PST 23
Finished	Dec 24 12:30:31 PM PST 23
Peak memory	221908 kb
Host	smart-73e0c841-0c07-4daa-bfc9-0c90eaa90f0d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232824539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_ shadow_reg_errors_with_csr_rw.232824539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3338508294
Short name	T1263
Test name
Test status
Simulation time	127146394 ps
CPU time	2.12 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:43 PM PST 23
Peak memory	216844 kb
Host	smart-46e50f29-68e1-4a7c-9d67-a75fe9897b62
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338508294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3338508294 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2550342324
Short name	T1262
Test name
Test status
Simulation time	931161118 ps
CPU time	5.06 seconds
Started	Dec 24 12:29:45 PM PST 23
Finished	Dec 24 12:30:12 PM PST 23
Peak memory	217676 kb
Host	smart-f1279962-2bb1-483b-b8e7-07438d9822c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550342324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.25503 42324 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3774284311
Short name	T1199
Test name
Test status
Simulation time	103027754 ps
CPU time	1.29 seconds
Started	Dec 24 12:29:34 PM PST 23
Finished	Dec 24 12:29:48 PM PST 23
Peak memory	218616 kb
Host	smart-2f42d269-d66d-487c-9768-70f64385a00e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774284311 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3774284311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2839506683
Short name	T1176
Test name
Test status
Simulation time	31898291 ps
CPU time	1.19 seconds
Started	Dec 24 12:29:54 PM PST 23
Finished	Dec 24 12:30:21 PM PST 23
Peak memory	217696 kb
Host	smart-4eb9727d-3dd9-492a-b4c3-1302d429ba03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839506683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2839506683 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.3855728774
Short name	T1257
Test name
Test status
Simulation time	14823931 ps
CPU time	0.8 seconds
Started	Dec 24 12:29:31 PM PST 23
Finished	Dec 24 12:29:44 PM PST 23
Peak memory	217296 kb
Host	smart-2603e1e6-97b3-4ba3-8277-0ab931bf40bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855728774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3855728774 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.181229963
Short name	T110
Test name
Test status
Simulation time	78932443 ps
CPU time	2.34 seconds
Started	Dec 24 12:29:27 PM PST 23
Finished	Dec 24 12:29:39 PM PST 23
Peak memory	217604 kb
Host	smart-7a1ac37a-6e50-466f-a962-613de69e892b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181229963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_ outstanding.181229963 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3897308920
Short name	T88
Test name
Test status
Simulation time	44140575 ps
CPU time	1.29 seconds
Started	Dec 24 12:29:09 PM PST 23
Finished	Dec 24 12:29:13 PM PST 23
Peak memory	225052 kb
Host	smart-5d749de9-17cc-45f2-b23c-53ed124c1532
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897308920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.3897308920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2582582230
Short name	T1229
Test name
Test status
Simulation time	900823028 ps
CPU time	1.71 seconds
Started	Dec 24 12:29:52 PM PST 23
Finished	Dec 24 12:30:19 PM PST 23
Peak memory	217660 kb
Host	smart-42392ca8-e42d-443e-a65f-2e1856f2c930
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582582230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.2582582230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3527910398
Short name	T1219
Test name
Test status
Simulation time	214224289 ps
CPU time	2.64 seconds
Started	Dec 24 12:29:19 PM PST 23
Finished	Dec 24 12:29:30 PM PST 23
Peak memory	217580 kb
Host	smart-c23dc9cc-5065-4fec-a9e3-e1cd5a09e93f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527910398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3527910398 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2473600123
Short name	T1151
Test name
Test status
Simulation time	58713940 ps
CPU time	2.49 seconds
Started	Dec 24 12:30:06 PM PST 23
Finished	Dec 24 12:30:33 PM PST 23
Peak memory	216732 kb
Host	smart-2c24b580-ffbf-47f6-98ba-72023b1c00c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473600123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.24736 00123 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1759845820
Short name	T1209
Test name
Test status
Simulation time	36756285 ps
CPU time	1.77 seconds
Started	Dec 24 12:30:19 PM PST 23
Finished	Dec 24 12:30:43 PM PST 23
Peak memory	222380 kb
Host	smart-9fae9647-88bf-4ee2-b961-1d96370f121b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759845820 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1759845820 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1573446312
Short name	T1210
Test name
Test status
Simulation time	46754171 ps
CPU time	1.1 seconds
Started	Dec 24 12:29:38 PM PST 23
Finished	Dec 24 12:29:57 PM PST 23
Peak memory	216920 kb
Host	smart-93ccc0cd-83ee-4dcd-9261-dbaaacdab40d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573446312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1573446312 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.3958283422
Short name	T1187
Test name
Test status
Simulation time	16929810 ps
CPU time	0.79 seconds
Started	Dec 24 12:31:14 PM PST 23
Finished	Dec 24 12:31:37 PM PST 23
Peak memory	217080 kb
Host	smart-cb71d2fc-41e1-40eb-b72d-c9017f43135f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958283422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3958283422 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4212083995
Short name	T1162
Test name
Test status
Simulation time	131098075 ps
CPU time	2.47 seconds
Started	Dec 24 12:29:27 PM PST 23
Finished	Dec 24 12:29:39 PM PST 23
Peak memory	216776 kb
Host	smart-fa34f1b1-1e8a-4659-b1dc-489121eae84c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212083995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.4212083995 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1989047979
Short name	T1217
Test name
Test status
Simulation time	80505226 ps
CPU time	1.25 seconds
Started	Dec 24 12:29:29 PM PST 23
Finished	Dec 24 12:29:41 PM PST 23
Peak memory	218556 kb
Host	smart-6d52623c-5b0c-4ab4-bc45-2a66a2850a43
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989047979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.1989047979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2864411228
Short name	T129
Test name
Test status
Simulation time	36441292 ps
CPU time	1.68 seconds
Started	Dec 24 12:29:26 PM PST 23
Finished	Dec 24 12:29:36 PM PST 23
Peak memory	220804 kb
Host	smart-24fcd82f-d665-4fdd-92a9-a55ae6590b27
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864411228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2864411228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2834030910
Short name	T1181
Test name
Test status
Simulation time	192950061 ps
CPU time	4.27 seconds
Started	Dec 24 12:29:38 PM PST 23
Finished	Dec 24 12:30:01 PM PST 23
Peak memory	217672 kb
Host	smart-f2df99c4-3b66-4b8b-8390-ed91c8b635a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834030910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.28340 30910 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2989777198
Short name	T1265
Test name
Test status
Simulation time	25117140 ps
CPU time	2.13 seconds
Started	Dec 24 12:29:41 PM PST 23
Finished	Dec 24 12:30:03 PM PST 23
Peak memory	222436 kb
Host	smart-c10663dc-603f-4adb-9c8e-2cbf1063af2e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989777198 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2989777198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3696743481
Short name	T1242
Test name
Test status
Simulation time	41567314 ps
CPU time	1.03 seconds
Started	Dec 24 12:29:49 PM PST 23
Finished	Dec 24 12:30:12 PM PST 23
Peak memory	217340 kb
Host	smart-4f9b89ce-75cc-4f58-b3cf-b0098b17c91a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696743481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3696743481 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1109948661
Short name	T143
Test name
Test status
Simulation time	15018552 ps
CPU time	0.83 seconds
Started	Dec 24 12:30:21 PM PST 23
Finished	Dec 24 12:30:44 PM PST 23
Peak memory	216464 kb
Host	smart-8967a58d-a95d-4d6a-91d4-400692cdb662
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109948661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1109948661 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2510439473
Short name	T1239
Test name
Test status
Simulation time	100515883 ps
CPU time	1.73 seconds
Started	Dec 24 12:30:23 PM PST 23
Finished	Dec 24 12:30:48 PM PST 23
Peak memory	216824 kb
Host	smart-a8948419-5bd1-4899-943a-9f561897c2e5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510439473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.2510439473 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1637769751
Short name	T1243
Test name
Test status
Simulation time	27224237 ps
CPU time	1.01 seconds
Started	Dec 24 12:30:39 PM PST 23
Finished	Dec 24 12:31:11 PM PST 23
Peak memory	217404 kb
Host	smart-05d1840e-274d-4c94-916f-73a673035541
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637769751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.1637769751 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1567132827
Short name	T1254
Test name
Test status
Simulation time	441744499 ps
CPU time	3.19 seconds
Started	Dec 24 12:30:33 PM PST 23
Finished	Dec 24 12:31:03 PM PST 23
Peak memory	221756 kb
Host	smart-7ba1208b-d31e-4ab9-b69c-a8cf4c6296d8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567132827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.1567132827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.4092245000
Short name	T59
Test name
Test status
Simulation time	109324533 ps
CPU time	2.8 seconds
Started	Dec 24 12:30:39 PM PST 23
Finished	Dec 24 12:31:09 PM PST 23
Peak memory	216032 kb
Host	smart-e510b590-a5dc-42a2-ad28-7b2bc206c200
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092245000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.4092245000 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4075103609
Short name	T152
Test name
Test status
Simulation time	399456401 ps
CPU time	2.89 seconds
Started	Dec 24 12:29:30 PM PST 23
Finished	Dec 24 12:29:45 PM PST 23
Peak memory	217708 kb
Host	smart-2816a675-0e4a-4363-a5f9-4d19a8b736e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075103609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.40751 03609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.858605712
Short name	T868
Test name
Test status
Simulation time	19483372 ps
CPU time	0.84 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:18:10 PM PST 23
Peak memory	218532 kb
Host	smart-26a73561-3ba2-49dd-9ee2-2125917de2d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858605712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.858605712 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app.1810298646
Short name	T473
Test name
Test status
Simulation time	1665693025 ps
CPU time	74.61 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	232744 kb
Host	smart-4c9f9e02-6c86-465e-bc51-c613ad503d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810298646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1810298646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.2349895082
Short name	T832
Test name
Test status
Simulation time	24088304433 ps
CPU time	103.38 seconds
Started	Dec 24 01:18:32 PM PST 23
Finished	Dec 24 01:20:33 PM PST 23
Peak memory	236400 kb
Host	smart-0cb96976-0633-48c1-a48c-354880a26cf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349895082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2349895082 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.2794395799
Short name	T403
Test name
Test status
Simulation time	1115378389 ps
CPU time	33.81 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:18:34 PM PST 23
Peak memory	223516 kb
Host	smart-164e1c65-3f40-40bc-8873-33571ea2526d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794395799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2794395799 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.2524636686
Short name	T190
Test name
Test status
Simulation time	2172511659 ps
CPU time	33.56 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	228484 kb
Host	smart-815a77bb-3cb9-4636-b725-30164d84da75
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2524636686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2524636686 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.4058373024
Short name	T1075
Test name
Test status
Simulation time	150089376 ps
CPU time	1.05 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:15 PM PST 23
Peak memory	218796 kb
Host	smart-29de5e05-6bd6-4060-9857-3a4c51666098
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4058373024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.4058373024 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.3317142396
Short name	T363
Test name
Test status
Simulation time	3524293461 ps
CPU time	4.83 seconds
Started	Dec 24 01:17:56 PM PST 23
Finished	Dec 24 01:18:05 PM PST 23
Peak memory	222012 kb
Host	smart-fd3a600c-0d9b-4b17-a079-4030e0da86ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317142396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3317142396 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.2702295235
Short name	T1132
Test name
Test status
Simulation time	5604877425 ps
CPU time	211.09 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:21:40 PM PST 23
Peak memory	244808 kb
Host	smart-ba23f60a-72fe-4475-b0ab-d94c3f6e094d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702295235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2702295235 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_error.336469172
Short name	T43
Test name
Test status
Simulation time	12131414308 ps
CPU time	252.25 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:22:11 PM PST 23
Peak memory	259204 kb
Host	smart-235a5970-c0f5-4b2c-bfcd-e787eb2eff22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336469172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.336469172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.3748990206
Short name	T977
Test name
Test status
Simulation time	79948197 ps
CPU time	1.26 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:15 PM PST 23
Peak memory	220380 kb
Host	smart-e8dac0e8-eb0e-464a-92ba-876b4a39aec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748990206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3748990206 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.3411397575
Short name	T725
Test name
Test status
Simulation time	327809380678 ps
CPU time	2978.36 seconds
Started	Dec 24 01:17:52 PM PST 23
Finished	Dec 24 02:07:36 PM PST 23
Peak memory	452844 kb
Host	smart-fab740c9-9d03-4848-86f4-3af8c53aa953
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411397575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.3411397575 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.3066908289
Short name	T287
Test name
Test status
Simulation time	8626691840 ps
CPU time	267.52 seconds
Started	Dec 24 01:18:15 PM PST 23
Finished	Dec 24 01:22:44 PM PST 23
Peak memory	246708 kb
Host	smart-282431b1-4fe7-48de-be25-b51f49015d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066908289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3066908289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.1389378131
Short name	T9
Test name
Test status
Simulation time	9929705728 ps
CPU time	86.27 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:19:24 PM PST 23
Peak memory	279732 kb
Host	smart-4749eafc-3e02-4910-b7ba-8e3495fe92f2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389378131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1389378131 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.95024562
Short name	T470
Test name
Test status
Simulation time	13681388996 ps
CPU time	124.3 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:20:18 PM PST 23
Peak memory	236208 kb
Host	smart-3e131d0e-9454-4d15-9c48-8214305b9dfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95024562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.95024562 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.4104263869
Short name	T525
Test name
Test status
Simulation time	11850799888 ps
CPU time	87.58 seconds
Started	Dec 24 01:18:14 PM PST 23
Finished	Dec 24 01:19:43 PM PST 23
Peak memory	226944 kb
Host	smart-3424f80c-5839-4f24-838c-660737233202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104263869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.4104263869 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.99113361
Short name	T1051
Test name
Test status
Simulation time	568991973200 ps
CPU time	3762.6 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 02:20:42 PM PST 23
Peak memory	534004 kb
Host	smart-ed572a9c-dd66-4ca2-be2f-3ced172e13a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=99113361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.99113361 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/default/0.kmac_stress_all_with_rand_reset.213658691
Short name	T297
Test name
Test status
Simulation time	38747666329 ps
CPU time	793.07 seconds
Started	Dec 24 01:17:56 PM PST 23
Finished	Dec 24 01:31:13 PM PST 23
Peak memory	289728 kb
Host	smart-0b27ef33-2725-493b-9f6b-addb5be88c8e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=213658691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.213658691 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.3293883927
Short name	T851
Test name
Test status
Simulation time	394323163 ps
CPU time	6.25 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:18:06 PM PST 23
Peak memory	218820 kb
Host	smart-5e8ad640-0dc9-454b-90b3-d6f933f9d6e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293883927 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.kmac_test_vectors_kmac.3293883927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2164291185
Short name	T1095
Test name
Test status
Simulation time	95771744 ps
CPU time	5.8 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:18:15 PM PST 23
Peak memory	220112 kb
Host	smart-4b161c4a-3a37-49ea-b03a-0adadc33fdd5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164291185 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2164291185 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.2535248049
Short name	T818
Test name
Test status
Simulation time	85592632373 ps
CPU time	1945.93 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 01:50:41 PM PST 23
Peak memory	401324 kb
Host	smart-dc69629a-e39f-42a5-9606-6749a2690ae7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2535248049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2535248049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.755014149
Short name	T425
Test name
Test status
Simulation time	141465052167 ps
CPU time	2214.46 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:54:55 PM PST 23
Peak memory	389324 kb
Host	smart-732a0183-2f9f-4df0-b551-dd6075865437
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=755014149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.755014149 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.2457077407
Short name	T1068
Test name
Test status
Simulation time	15469710011 ps
CPU time	1658 seconds
Started	Dec 24 01:18:13 PM PST 23
Finished	Dec 24 01:45:53 PM PST 23
Peak memory	342012 kb
Host	smart-d84cd05e-ac28-452c-81bc-bb6b65919c0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2457077407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2457077407 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.2373059396
Short name	T1053
Test name
Test status
Simulation time	17508440776 ps
CPU time	1214.33 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:38:14 PM PST 23
Peak memory	305188 kb
Host	smart-03c7baad-8b38-48da-aa58-10b39f98fe93
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2373059396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2373059396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.957511700
Short name	T707
Test name
Test status
Simulation time	1075253680516 ps
CPU time	6231.76 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 03:02:07 PM PST 23
Peak memory	654960 kb
Host	smart-309f5355-ce9d-4219-9347-0f883f5518cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=957511700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.957511700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.1830982686
Short name	T1103
Test name
Test status
Simulation time	1462400823690 ps
CPU time	5742.67 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 02:53:44 PM PST 23
Peak memory	575552 kb
Host	smart-87cc568f-827b-4180-ba08-7bb7731c06b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1830982686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1830982686 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.2932805866
Short name	T769
Test name
Test status
Simulation time	21706211 ps
CPU time	0.83 seconds
Started	Dec 24 01:18:09 PM PST 23
Finished	Dec 24 01:18:11 PM PST 23
Peak memory	218456 kb
Host	smart-7b3c79c2-c404-44b3-a989-791d71eef49c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932805866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2932805866 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.4274604161
Short name	T828
Test name
Test status
Simulation time	2629149697 ps
CPU time	27.76 seconds
Started	Dec 24 01:18:14 PM PST 23
Finished	Dec 24 01:18:43 PM PST 23
Peak memory	227148 kb
Host	smart-50b9f969-d887-48b3-8b69-8889b53cea90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274604161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4274604161 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.495547270
Short name	T865
Test name
Test status
Simulation time	2355063430 ps
CPU time	65.48 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	230972 kb
Host	smart-f179c064-b914-4d11-9351-331c753b8fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495547270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.495547270 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.1252211269
Short name	T854
Test name
Test status
Simulation time	22090147042 ps
CPU time	1163.84 seconds
Started	Dec 24 01:17:52 PM PST 23
Finished	Dec 24 01:37:21 PM PST 23
Peak memory	243328 kb
Host	smart-e3fdf43d-91a0-4ae4-8e7e-41be7723926d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252211269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1252211269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.754357328
Short name	T846
Test name
Test status
Simulation time	7807504303 ps
CPU time	349.18 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:23:49 PM PST 23
Peak memory	254500 kb
Host	smart-222796ed-2dd5-4a53-ab40-30f25a9a136c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754357328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.754357328 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.1465437103
Short name	T255
Test name
Test status
Simulation time	1625648900 ps
CPU time	26.64 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:18:26 PM PST 23
Peak memory	242000 kb
Host	smart-c3202c2f-c7a9-42e3-b5a3-33e1068ce240
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465437103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1465437103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.2110609392
Short name	T696
Test name
Test status
Simulation time	809079001 ps
CPU time	4.94 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:18:05 PM PST 23
Peak memory	218680 kb
Host	smart-be11b72d-0dca-4b54-97c5-173ebfd360fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110609392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2110609392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.1220939976
Short name	T637
Test name
Test status
Simulation time	135374287 ps
CPU time	1.38 seconds
Started	Dec 24 01:18:09 PM PST 23
Finished	Dec 24 01:18:11 PM PST 23
Peak memory	219880 kb
Host	smart-16538385-5ebf-4e23-a848-016ab7b5c7f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220939976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1220939976 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.2223994502
Short name	T1120
Test name
Test status
Simulation time	44139739002 ps
CPU time	1934.56 seconds
Started	Dec 24 01:17:57 PM PST 23
Finished	Dec 24 01:50:16 PM PST 23
Peak memory	389408 kb
Host	smart-31d2e954-6694-44bc-8551-7751dbea53a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223994502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.2223994502 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.4264919919
Short name	T628
Test name
Test status
Simulation time	48560597187 ps
CPU time	169.34 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:20:48 PM PST 23
Peak memory	242536 kb
Host	smart-6759ae0c-2480-4ee2-a15e-0a584c0bb499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264919919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4264919919 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.222606785
Short name	T106
Test name
Test status
Simulation time	9290522447 ps
CPU time	105.09 seconds
Started	Dec 24 01:18:09 PM PST 23
Finished	Dec 24 01:19:55 PM PST 23
Peak memory	267508 kb
Host	smart-a37b9be2-9166-4315-b25a-ef33e5525c4a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222606785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.222606785 +enable_masking =1 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/1.kmac_sideload.3422887730
Short name	T562
Test name
Test status
Simulation time	2502584835 ps
CPU time	48.67 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:18:48 PM PST 23
Peak memory	228140 kb
Host	smart-e4f028c7-6af1-47c8-acfd-97b3e7410dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422887730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3422887730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.52334798
Short name	T862
Test name
Test status
Simulation time	5976623234 ps
CPU time	44.68 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	226980 kb
Host	smart-0bf0ccd1-1316-4747-8af1-8ab1df603627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52334798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.52334798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.1175061285
Short name	T804
Test name
Test status
Simulation time	8158962410 ps
CPU time	786.21 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 01:31:19 PM PST 23
Peak memory	322056 kb
Host	smart-3173782b-a016-47cc-8e2d-914cc8d5b172
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1175061285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1175061285 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.2867538387
Short name	T722
Test name
Test status
Simulation time	1381569199 ps
CPU time	6.07 seconds
Started	Dec 24 01:17:50 PM PST 23
Finished	Dec 24 01:18:01 PM PST 23
Peak memory	220340 kb
Host	smart-fed2e489-f123-4057-a160-89f51f75c767
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867538387 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.kmac_test_vectors_kmac.2867538387 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.205772021
Short name	T27
Test name
Test status
Simulation time	212910840 ps
CPU time	6.1 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:18:06 PM PST 23
Peak memory	218908 kb
Host	smart-01bb05fd-04e3-4610-a34a-d33fc651ed35
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205772021 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.kmac_test_vectors_kmac_xof.205772021 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.347588437
Short name	T376
Test name
Test status
Simulation time	86305484002 ps
CPU time	1971.66 seconds
Started	Dec 24 01:18:27 PM PST 23
Finished	Dec 24 01:51:39 PM PST 23
Peak memory	399196 kb
Host	smart-7f4665a2-9b72-42c1-95e6-e8332b7a953e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=347588437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.347588437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.3200747472
Short name	T225
Test name
Test status
Simulation time	351027612205 ps
CPU time	2289.2 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:56:19 PM PST 23
Peak memory	395200 kb
Host	smart-c566014b-3b6e-4468-b6b3-6afec727e932
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3200747472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3200747472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.2662006686
Short name	T792
Test name
Test status
Simulation time	30510759189 ps
CPU time	1571.09 seconds
Started	Dec 24 01:17:56 PM PST 23
Finished	Dec 24 01:44:12 PM PST 23
Peak memory	337132 kb
Host	smart-a3a3bde3-db91-4cfa-87ea-0e8779dd730c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2662006686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2662006686 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.838696913
Short name	T204
Test name
Test status
Simulation time	474787298228 ps
CPU time	1422.42 seconds
Started	Dec 24 01:17:55 PM PST 23
Finished	Dec 24 01:41:43 PM PST 23
Peak memory	301872 kb
Host	smart-bca680ad-d679-4f8d-868d-3c6452c88924
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=838696913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.838696913 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.2456050380
Short name	T1118
Test name
Test status
Simulation time	260239704693 ps
CPU time	4781.52 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 02:37:51 PM PST 23
Peak memory	650776 kb
Host	smart-0c51731c-4701-426c-b8c8-d00c8a9e658d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2456050380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2456050380 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.3113681002
Short name	T654
Test name
Test status
Simulation time	173512536398 ps
CPU time	5129.1 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 02:44:09 PM PST 23
Peak memory	579660 kb
Host	smart-0268f711-699f-4214-bd8f-996e381f838e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3113681002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3113681002 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.1474739409
Short name	T320
Test name
Test status
Simulation time	43396805 ps
CPU time	0.89 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	218448 kb
Host	smart-6ea0fb36-567d-4345-bcf0-63d155454d42
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474739409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1474739409 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_app.1937916547
Short name	T759
Test name
Test status
Simulation time	2617813361 ps
CPU time	149.28 seconds
Started	Dec 24 01:19:04 PM PST 23
Finished	Dec 24 01:21:50 PM PST 23
Peak memory	240152 kb
Host	smart-a69933fb-e6ee-4423-adfc-a3f03280d9e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937916547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1937916547 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.2693669958
Short name	T1092
Test name
Test status
Simulation time	8665844491 ps
CPU time	521.67 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:28:06 PM PST 23
Peak memory	235292 kb
Host	smart-831720d1-a1e3-4f39-90db-fcc8625ace80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693669958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2693669958 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.1245534030
Short name	T380
Test name
Test status
Simulation time	94619526 ps
CPU time	1.38 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:19:00 PM PST 23
Peak memory	218776 kb
Host	smart-2b01958f-1c8f-4541-9209-7ca57741c6e0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1245534030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1245534030 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.3838220564
Short name	T673
Test name
Test status
Simulation time	35184741 ps
CPU time	2.62 seconds
Started	Dec 24 01:19:13 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	219688 kb
Host	smart-f8d816aa-a2bc-4d49-9b42-fe199e4ebc60
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3838220564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3838220564 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.1037776705
Short name	T41
Test name
Test status
Simulation time	28319605027 ps
CPU time	312.16 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:24:31 PM PST 23
Peak memory	250592 kb
Host	smart-5fe7b797-37ff-4333-8586-29e88893f338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037776705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1037776705 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.500693603
Short name	T827
Test name
Test status
Simulation time	6863926022 ps
CPU time	225.69 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:22:45 PM PST 23
Peak memory	259652 kb
Host	smart-8e0fb38a-ab67-45fe-bc3a-c5369bdfc98d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500693603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.500693603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.1286160358
Short name	T723
Test name
Test status
Simulation time	3024972629 ps
CPU time	4.32 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:07 PM PST 23
Peak memory	218716 kb
Host	smart-1b221097-1aaa-4f71-92e2-c1d85e5f7ff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286160358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1286160358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.2189000797
Short name	T906
Test name
Test status
Simulation time	64567334269 ps
CPU time	2282.17 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:57:18 PM PST 23
Peak memory	402476 kb
Host	smart-0cf23b7b-cab9-4057-9cf6-78977c12b9f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189000797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a nd_output.2189000797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.70942513
Short name	T943
Test name
Test status
Simulation time	19194226091 ps
CPU time	511.65 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:27:46 PM PST 23
Peak memory	256576 kb
Host	smart-7872d5a8-ce42-46b7-9e58-5b6283ccaaef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70942513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.70942513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.1733977494
Short name	T435
Test name
Test status
Simulation time	3101617956 ps
CPU time	58.76 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:20:06 PM PST 23
Peak memory	227008 kb
Host	smart-59afd104-06a1-42e2-93f6-0e90ba39a9e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733977494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1733977494 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.200184628
Short name	T944
Test name
Test status
Simulation time	73392896544 ps
CPU time	1011.27 seconds
Started	Dec 24 01:18:27 PM PST 23
Finished	Dec 24 01:35:40 PM PST 23
Peak memory	317120 kb
Host	smart-dc6a75d0-08e8-4f1b-9710-18d2ae889f53
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=200184628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.200184628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.1070067179
Short name	T1021
Test name
Test status
Simulation time	214492356 ps
CPU time	6.7 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	218824 kb
Host	smart-5836c1f1-8227-4e57-8edf-f36c846b41c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070067179 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.1070067179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2174020153
Short name	T1084
Test name
Test status
Simulation time	235824592 ps
CPU time	5.84 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	220216 kb
Host	smart-8b8b2002-6cc5-4c45-b541-b458e28a45ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174020153 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2174020153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.655137035
Short name	T986
Test name
Test status
Simulation time	242314868991 ps
CPU time	2203.7 seconds
Started	Dec 24 01:18:59 PM PST 23
Finished	Dec 24 01:56:03 PM PST 23
Peak memory	399456 kb
Host	smart-57fbf9d3-bc97-4132-b3c9-e51dd488a969
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=655137035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.655137035 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.3748867184
Short name	T1066
Test name
Test status
Simulation time	19638082171 ps
CPU time	1956.99 seconds
Started	Dec 24 01:18:55 PM PST 23
Finished	Dec 24 01:51:55 PM PST 23
Peak memory	387012 kb
Host	smart-ec607bb2-2394-4814-8930-0913f0d604ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3748867184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3748867184 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.2765545280
Short name	T226
Test name
Test status
Simulation time	63837960979 ps
CPU time	1651.06 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:46:46 PM PST 23
Peak memory	347856 kb
Host	smart-9d96da77-5409-41e7-b0ec-d5e586a155c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2765545280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2765545280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.4179802994
Short name	T203
Test name
Test status
Simulation time	140453043734 ps
CPU time	1311.11 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:41:13 PM PST 23
Peak memory	305556 kb
Host	smart-a342efc3-4326-45d9-8fae-da063c05d685
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4179802994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.4179802994 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.3157210328
Short name	T584
Test name
Test status
Simulation time	241481492669 ps
CPU time	4707.78 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 02:37:47 PM PST 23
Peak memory	672932 kb
Host	smart-d4365485-1073-478a-a00d-a9601705896d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3157210328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3157210328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.1889794283
Short name	T453
Test name
Test status
Simulation time	718276166812 ps
CPU time	4735.23 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 02:38:11 PM PST 23
Peak memory	561108 kb
Host	smart-fc62118c-bdd4-4fb0-b0d2-76ba4da1b1f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1889794283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1889794283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_app.3739026921
Short name	T778
Test name
Test status
Simulation time	9043930213 ps
CPU time	117.84 seconds
Started	Dec 24 01:18:33 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	236908 kb
Host	smart-14cad577-7c43-444e-963e-5c19cdd0008a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739026921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3739026921 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.1284592006
Short name	T285
Test name
Test status
Simulation time	59821671386 ps
CPU time	1375.73 seconds
Started	Dec 24 01:18:35 PM PST 23
Finished	Dec 24 01:41:51 PM PST 23
Peak memory	239776 kb
Host	smart-b3ce5407-5b9e-4ec0-825b-7307e11ac9fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284592006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1284592006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.3291051450
Short name	T344
Test name
Test status
Simulation time	553222018 ps
CPU time	9.5 seconds
Started	Dec 24 01:18:34 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	227580 kb
Host	smart-989942e4-318f-4db4-adf6-f4c5b16be091
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3291051450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3291051450 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.4122583433
Short name	T638
Test name
Test status
Simulation time	67221392 ps
CPU time	0.92 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	218528 kb
Host	smart-245e3de2-9784-44ee-8a16-d602f8a1bfd8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4122583433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.4122583433 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.4291152596
Short name	T1102
Test name
Test status
Simulation time	4249553622 ps
CPU time	221.15 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:22:39 PM PST 23
Peak memory	245976 kb
Host	smart-eaab479c-1c7f-4e07-a376-378b24b110de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291152596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4291152596 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.979667029
Short name	T351
Test name
Test status
Simulation time	1815383540 ps
CPU time	147.98 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:21:26 PM PST 23
Peak memory	251552 kb
Host	smart-498840b5-43c1-4c23-8757-e2b45be9c2ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979667029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.979667029 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.2930143006
Short name	T625
Test name
Test status
Simulation time	3380913707 ps
CPU time	6.06 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:11 PM PST 23
Peak memory	218776 kb
Host	smart-02a495d9-fc5b-4189-bc13-bb71376596b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930143006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2930143006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.3074876015
Short name	T1108
Test name
Test status
Simulation time	38823353 ps
CPU time	1.38 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	219804 kb
Host	smart-adcaf910-b352-426f-b43d-77d329aafa72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074876015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3074876015 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.1143555827
Short name	T250
Test name
Test status
Simulation time	58364055726 ps
CPU time	1406.19 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:42:25 PM PST 23
Peak memory	339876 kb
Host	smart-03e03f78-dd3d-4204-a954-e58598ae1e01
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143555827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.1143555827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.2722230457
Short name	T331
Test name
Test status
Simulation time	6046394410 ps
CPU time	417.22 seconds
Started	Dec 24 01:18:36 PM PST 23
Finished	Dec 24 01:25:52 PM PST 23
Peak memory	255036 kb
Host	smart-9d3729cd-c353-4b33-b0a8-794d505e82a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722230457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2722230457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.3955477604
Short name	T894
Test name
Test status
Simulation time	965868327 ps
CPU time	20.57 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:19:21 PM PST 23
Peak memory	224884 kb
Host	smart-890b921b-2d74-428f-9d1d-0f54d82e3980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955477604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3955477604 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.801894306
Short name	T1106
Test name
Test status
Simulation time	4070896320 ps
CPU time	214.09 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:22:44 PM PST 23
Peak memory	269872 kb
Host	smart-67564b8b-b990-4c0f-93e4-997adfb842da
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=801894306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.801894306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_stress_all_with_rand_reset.3423301724
Short name	T21
Test name
Test status
Simulation time	120769945831 ps
CPU time	1216.09 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:39:17 PM PST 23
Peak memory	321836 kb
Host	smart-f328dcca-38fc-41a3-8a9b-430cba1969bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3423301724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all_with_rand_reset.3423301724 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.3213864683
Short name	T634
Test name
Test status
Simulation time	1484344864 ps
CPU time	5.23 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	220012 kb
Host	smart-06d4bbc9-79eb-4f3e-a07e-e859331eb14a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213864683 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.3213864683 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.4285380943
Short name	T905
Test name
Test status
Simulation time	292831534 ps
CPU time	6.62 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:11 PM PST 23
Peak memory	218892 kb
Host	smart-0b029ca5-d34a-4ef4-979f-18f31f3c281a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285380943 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.4285380943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.2142150646
Short name	T825
Test name
Test status
Simulation time	66940123433 ps
CPU time	2374.6 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:58:36 PM PST 23
Peak memory	401832 kb
Host	smart-ce42c46f-75de-4a39-b7b0-23fcfba98a37
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2142150646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2142150646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.50494722
Short name	T924
Test name
Test status
Simulation time	86877714909 ps
CPU time	1921.82 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:51:20 PM PST 23
Peak memory	387956 kb
Host	smart-efdf13eb-c9a3-4981-949e-e3a8726301be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=50494722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.50494722 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.2011358688
Short name	T200
Test name
Test status
Simulation time	19508289453 ps
CPU time	1536.98 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:44:44 PM PST 23
Peak memory	338744 kb
Host	smart-cddfb8ee-6b5e-4182-be89-2c36cb3217a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2011358688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2011358688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.1696572539
Short name	T502
Test name
Test status
Simulation time	49616812852 ps
CPU time	1292.99 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:40:32 PM PST 23
Peak memory	304140 kb
Host	smart-c22dad3d-354e-45f5-9b18-c1eb270dcb4e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1696572539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.1696572539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.408453917
Short name	T699
Test name
Test status
Simulation time	1255230580280 ps
CPU time	5871.85 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 02:57:00 PM PST 23
Peak memory	648308 kb
Host	smart-11f76d75-65a4-45a5-876e-be066218e9c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=408453917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.408453917 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.2566334376
Short name	T393
Test name
Test status
Simulation time	767711092568 ps
CPU time	4995.13 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 02:42:20 PM PST 23
Peak memory	574068 kb
Host	smart-69b1b271-9fd4-4eef-a266-4d2bc924c760
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2566334376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2566334376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.3333894660
Short name	T95
Test name
Test status
Simulation time	23949146 ps
CPU time	0.84 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:04 PM PST 23
Peak memory	219688 kb
Host	smart-75996792-2d34-4aee-bd12-5f4a8241a724
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333894660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3333894660 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.3592167447
Short name	T535
Test name
Test status
Simulation time	2644045530 ps
CPU time	148.07 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:21:26 PM PST 23
Peak memory	239080 kb
Host	smart-83f09f55-4e2c-464a-bb26-6d22e956a93a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592167447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3592167447 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.2806920879
Short name	T274
Test name
Test status
Simulation time	2377293514 ps
CPU time	11.56 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:19:11 PM PST 23
Peak memory	219960 kb
Host	smart-35de542a-9842-46ab-bc50-0703db4078bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806920879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2806920879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.1529728797
Short name	T1001
Test name
Test status
Simulation time	1447585144 ps
CPU time	9.8 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:13 PM PST 23
Peak memory	227232 kb
Host	smart-e1a832f1-325b-4636-bf3a-c7a58aa480b1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1529728797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1529728797 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.4016423764
Short name	T530
Test name
Test status
Simulation time	23039052 ps
CPU time	0.97 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	218488 kb
Host	smart-55ee5835-b424-4df5-b3b5-fbef801dd874
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4016423764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4016423764 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.3444372802
Short name	T644
Test name
Test status
Simulation time	10055589778 ps
CPU time	212.9 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:22:41 PM PST 23
Peak memory	243124 kb
Host	smart-b8bc444f-961c-4983-9e1a-693a06dc9483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444372802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3444372802 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.772208552
Short name	T504
Test name
Test status
Simulation time	3687204137 ps
CPU time	120.61 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:21:03 PM PST 23
Peak memory	251616 kb
Host	smart-2e056335-b13a-4ce1-8475-96a3fb5b53d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772208552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.772208552 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.510225803
Short name	T1123
Test name
Test status
Simulation time	99348124 ps
CPU time	1.35 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	218464 kb
Host	smart-b8c951b8-951e-425c-b766-b13ebb2a363e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510225803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.510225803 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.2594166644
Short name	T490
Test name
Test status
Simulation time	725658611 ps
CPU time	21.35 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:26 PM PST 23
Peak memory	235136 kb
Host	smart-b82aacd2-b81a-4467-8e8a-2f2d36390448
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594166644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2594166644 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.1062515451
Short name	T479
Test name
Test status
Simulation time	26129263254 ps
CPU time	597.33 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 01:28:55 PM PST 23
Peak memory	281088 kb
Host	smart-b5a4828e-2d48-4e2c-b988-357de6c2a239
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062515451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.1062515451 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.1863452637
Short name	T610
Test name
Test status
Simulation time	28957858319 ps
CPU time	482.5 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:27:06 PM PST 23
Peak memory	256484 kb
Host	smart-c3893ad8-24d4-4fee-a148-392ba0672e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863452637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1863452637 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.1086121259
Short name	T301
Test name
Test status
Simulation time	995070196 ps
CPU time	40.44 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 01:19:38 PM PST 23
Peak memory	224084 kb
Host	smart-61a41372-206f-4024-a915-0958d55ee5df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086121259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1086121259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.1612372421
Short name	T597
Test name
Test status
Simulation time	11377143345 ps
CPU time	252.54 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:23:13 PM PST 23
Peak memory	259960 kb
Host	smart-de44794a-30d3-4991-b5a8-1e94022d43e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1612372421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1612372421 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_stress_all_with_rand_reset.4132991656
Short name	T780
Test name
Test status
Simulation time	22976053037 ps
CPU time	964.24 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:35:08 PM PST 23
Peak memory	301908 kb
Host	smart-c7f7994b-32ce-4727-8545-601580c6559c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4132991656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.4132991656 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.2033426363
Short name	T907
Test name
Test status
Simulation time	1781585633 ps
CPU time	6.28 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	220088 kb
Host	smart-53128f5b-40e7-4cf3-9741-69599ea043a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033426363 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.2033426363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2609411614
Short name	T950
Test name
Test status
Simulation time	204044526 ps
CPU time	5.63 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:09 PM PST 23
Peak memory	220172 kb
Host	smart-7eb29e28-47c9-42cf-907a-47bebf95975c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609411614 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2609411614 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.281814432
Short name	T1027
Test name
Test status
Simulation time	399920488653 ps
CPU time	2453.59 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:59:57 PM PST 23
Peak memory	393776 kb
Host	smart-539e080f-ae0c-47f3-9c65-f8733e763b9e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=281814432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.281814432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.2710089278
Short name	T901
Test name
Test status
Simulation time	85016462921 ps
CPU time	1980.84 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:51:59 PM PST 23
Peak memory	392272 kb
Host	smart-ee72dcd9-f3be-428f-9f4d-ad425e5f4091
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2710089278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2710089278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.495238786
Short name	T856
Test name
Test status
Simulation time	19783425868 ps
CPU time	1583.28 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:45:28 PM PST 23
Peak memory	346992 kb
Host	smart-28db2a6a-6af5-42d1-997b-8bec4709ece4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=495238786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.495238786 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.1325599250
Short name	T1018
Test name
Test status
Simulation time	56677056288 ps
CPU time	1340.76 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:41:24 PM PST 23
Peak memory	300904 kb
Host	smart-d9f45c89-2d98-46e6-85ee-86ba1abf6122
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1325599250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1325599250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.2842095429
Short name	T1105
Test name
Test status
Simulation time	1825614103956 ps
CPU time	5791.51 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 02:55:30 PM PST 23
Peak memory	648808 kb
Host	smart-685848b1-4662-452b-a903-c1a923b7f524
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2842095429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.2842095429 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.598059266
Short name	T1020
Test name
Test status
Simulation time	798370636518 ps
CPU time	5211.11 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 02:45:55 PM PST 23
Peak memory	576980 kb
Host	smart-879e4e2c-61f0-440d-8718-1b92ece3004c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=598059266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.598059266 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.2732127567
Short name	T441
Test name
Test status
Simulation time	149059791 ps
CPU time	0.86 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	217756 kb
Host	smart-048b4b96-a625-49f5-846a-5e548293403c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732127567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2732127567 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.3900485934
Short name	T630
Test name
Test status
Simulation time	9209510082 ps
CPU time	284.25 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:23:58 PM PST 23
Peak memory	247956 kb
Host	smart-b8d043f3-4acf-4a62-a5b9-ed7e41ae9369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900485934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3900485934 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.2102896982
Short name	T421
Test name
Test status
Simulation time	44736017673 ps
CPU time	1124.5 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 01:37:42 PM PST 23
Peak memory	238112 kb
Host	smart-148fb6c4-5e18-46b6-b3ee-dda64ea46b09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102896982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2102896982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.2842028790
Short name	T214
Test name
Test status
Simulation time	899302919 ps
CPU time	9.85 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:21 PM PST 23
Peak memory	233484 kb
Host	smart-14d4c81d-533f-4bef-94bb-f5673351a22e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2842028790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2842028790 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.3761632985
Short name	T1039
Test name
Test status
Simulation time	1851892748 ps
CPU time	12.06 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	222144 kb
Host	smart-53138c01-094d-471f-9c5d-1ea99a8065d6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3761632985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3761632985 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.3900905193
Short name	T1038
Test name
Test status
Simulation time	16214463108 ps
CPU time	211.89 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:22:46 PM PST 23
Peak memory	243324 kb
Host	smart-4fbbb885-fc0c-4e97-9690-8c0e19ae7e38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900905193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3900905193 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.3753189243
Short name	T912
Test name
Test status
Simulation time	2358832639 ps
CPU time	91.55 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:20:44 PM PST 23
Peak memory	243008 kb
Host	smart-9b30dbeb-d16d-4785-acb5-2ae76be3b5f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753189243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3753189243 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.851823880
Short name	T1004
Test name
Test status
Simulation time	3146979977 ps
CPU time	4.44 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:20 PM PST 23
Peak memory	218656 kb
Host	smart-d021b1fb-e0ee-43c0-b1c4-e31bc32f3c68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851823880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.851823880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.1900326026
Short name	T1091
Test name
Test status
Simulation time	48557457 ps
CPU time	1.45 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	218900 kb
Host	smart-3d2a0b7b-057a-4f47-ba7c-26b5e444c4ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900326026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1900326026 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.1572922850
Short name	T485
Test name
Test status
Simulation time	11120693950 ps
CPU time	449.39 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:26:33 PM PST 23
Peak memory	265116 kb
Host	smart-3a2a2a8e-1d74-4602-b74b-e551e660e6d1
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572922850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.1572922850 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.3306701695
Short name	T398
Test name
Test status
Simulation time	28372034279 ps
CPU time	236.8 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:22:56 PM PST 23
Peak memory	245680 kb
Host	smart-9c1ee262-cfdc-4564-bb95-c9dd817ab69b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306701695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3306701695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.1581529796
Short name	T280
Test name
Test status
Simulation time	4296513693 ps
CPU time	43.82 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	220028 kb
Host	smart-cd0fd123-9dd2-4e83-a19e-f6c422739805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581529796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1581529796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.3212357289
Short name	T588
Test name
Test status
Simulation time	18489670682 ps
CPU time	408.9 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:25:59 PM PST 23
Peak memory	286596 kb
Host	smart-5b830e4f-b3f5-422f-8d11-135edc434dd9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3212357289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3212357289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.3459720211
Short name	T457
Test name
Test status
Simulation time	256091228 ps
CPU time	6.88 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:13 PM PST 23
Peak memory	220232 kb
Host	smart-86908792-6b92-4693-8a71-f9b03ee98e0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459720211 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.kmac_test_vectors_kmac.3459720211 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1635320521
Short name	T191
Test name
Test status
Simulation time	316338004 ps
CPU time	6.62 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	220172 kb
Host	smart-f6325c76-c37d-4008-8dae-774ee67a2720
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635320521 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1635320521 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.1170120141
Short name	T282
Test name
Test status
Simulation time	22642748780 ps
CPU time	1965.32 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:51:44 PM PST 23
Peak memory	393576 kb
Host	smart-0a999144-2887-481a-be97-22f4c7f5254f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1170120141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1170120141 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.3510723515
Short name	T1019
Test name
Test status
Simulation time	147850710258 ps
CPU time	1952.2 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:51:41 PM PST 23
Peak memory	390200 kb
Host	smart-1f46e79a-f01c-45d0-b627-210386c7eb78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3510723515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3510723515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.2213976689
Short name	T643
Test name
Test status
Simulation time	16346387369 ps
CPU time	1475.42 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:43:49 PM PST 23
Peak memory	341984 kb
Host	smart-f4dfc2dc-e22c-49f6-9173-6c056e12c08e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2213976689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2213976689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.2152635452
Short name	T259
Test name
Test status
Simulation time	70745276127 ps
CPU time	1300.92 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:40:39 PM PST 23
Peak memory	305468 kb
Host	smart-2c4c9f93-84d8-42c0-812e-f79936e4b234
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2152635452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2152635452 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.2764093156
Short name	T765
Test name
Test status
Simulation time	186035065408 ps
CPU time	5776.98 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 02:55:29 PM PST 23
Peak memory	659972 kb
Host	smart-6c2e0b05-cbfb-4853-8258-7ed1b5ded061
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2764093156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2764093156 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.266310689
Short name	T386
Test name
Test status
Simulation time	111770098965 ps
CPU time	4177.55 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 02:28:47 PM PST 23
Peak memory	595556 kb
Host	smart-2eb75289-b253-493f-a6c6-ede19200b612
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=266310689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.266310689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.4256425726
Short name	T941
Test name
Test status
Simulation time	163900284 ps
CPU time	0.83 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:19:19 PM PST 23
Peak memory	219712 kb
Host	smart-b309a5ca-4ec9-4e2e-9562-311a98427406
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256425726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4256425726 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.992925433
Short name	T721
Test name
Test status
Simulation time	81792310361 ps
CPU time	388.28 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:25:47 PM PST 23
Peak memory	252148 kb
Host	smart-0fc76aaf-0845-4217-9b41-37ba1384d309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992925433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.992925433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.4026067580
Short name	T873
Test name
Test status
Simulation time	82526397863 ps
CPU time	1132.15 seconds
Started	Dec 24 01:19:01 PM PST 23
Finished	Dec 24 01:38:12 PM PST 23
Peak memory	239508 kb
Host	smart-90ec7877-ac6d-4042-aebc-1f52d8da6a90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026067580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.4026067580 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.712199961
Short name	T466
Test name
Test status
Simulation time	2608044983 ps
CPU time	17.23 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:22 PM PST 23
Peak memory	234944 kb
Host	smart-3a93525e-b200-441d-9615-d9c8569e90d9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=712199961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.712199961 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.1552495981
Short name	T1119
Test name
Test status
Simulation time	1197543773 ps
CPU time	27.93 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:19:36 PM PST 23
Peak memory	225352 kb
Host	smart-c106a21b-450b-4dfe-bb02-4fc483a5f8ae
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1552495981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1552495981 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.3544148548
Short name	T455
Test name
Test status
Simulation time	27333018764 ps
CPU time	292.05 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:23:58 PM PST 23
Peak memory	247152 kb
Host	smart-ac70b5c2-2385-4e27-bcc1-39347da5b13b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544148548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3544148548 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.2938552281
Short name	T806
Test name
Test status
Simulation time	2335537145 ps
CPU time	62.09 seconds
Started	Dec 24 01:18:59 PM PST 23
Finished	Dec 24 01:20:21 PM PST 23
Peak memory	243180 kb
Host	smart-420ebe95-4f95-4290-b31a-8cc4d4f11d87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938552281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2938552281 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.2968094304
Short name	T1003
Test name
Test status
Simulation time	11153075097 ps
CPU time	8.65 seconds
Started	Dec 24 01:19:03 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	218896 kb
Host	smart-3f820844-f58e-4d1c-8901-f43a83ac2d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968094304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2968094304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.4194829066
Short name	T188
Test name
Test status
Simulation time	56332850 ps
CPU time	1.28 seconds
Started	Dec 24 01:18:59 PM PST 23
Finished	Dec 24 01:19:21 PM PST 23
Peak memory	220048 kb
Host	smart-3495c8e5-8b0c-4d7a-9c44-97ee541158f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194829066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.4194829066 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.164355669
Short name	T412
Test name
Test status
Simulation time	815425376462 ps
CPU time	3331.98 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 02:14:47 PM PST 23
Peak memory	470444 kb
Host	smart-d8f40675-6499-4513-98d5-8233a812c4d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164355669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_an d_output.164355669 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.651290991
Short name	T308
Test name
Test status
Simulation time	6144198464 ps
CPU time	445.84 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:26:45 PM PST 23
Peak memory	254488 kb
Host	smart-018ba7d5-3a17-4e10-a84e-c5b48a5a18ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651290991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.651290991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.4095245572
Short name	T982
Test name
Test status
Simulation time	1014228897 ps
CPU time	24.74 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:40 PM PST 23
Peak memory	224360 kb
Host	smart-90e57125-eaee-4079-81b4-a4ff1a492ca9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095245572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.4095245572 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.4262562103
Short name	T967
Test name
Test status
Simulation time	62393235475 ps
CPU time	984.38 seconds
Started	Dec 24 01:18:59 PM PST 23
Finished	Dec 24 01:35:44 PM PST 23
Peak memory	340624 kb
Host	smart-67084545-1e61-4e05-b5cb-b3fef0b65593
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4262562103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.4262562103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3310067999
Short name	T945
Test name
Test status
Simulation time	133571723214 ps
CPU time	2211.35 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:56:14 PM PST 23
Peak memory	420764 kb
Host	smart-b5e71df4-964d-4c87-a0e8-316e3fb3e59d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3310067999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3310067999 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.4119238225
Short name	T1030
Test name
Test status
Simulation time	721975211 ps
CPU time	6.83 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	218824 kb
Host	smart-6bb65f7a-895f-46af-aef2-4f08f2c37b0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119238225 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.4119238225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1629781318
Short name	T361
Test name
Test status
Simulation time	500757895 ps
CPU time	7.12 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	220248 kb
Host	smart-b36c1a55-2691-4499-8a59-e464312ce766
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629781318 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1629781318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.445164406
Short name	T954
Test name
Test status
Simulation time	653455575287 ps
CPU time	2511.86 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 02:01:07 PM PST 23
Peak memory	397504 kb
Host	smart-c0d42304-3dee-4bff-af87-d4c0436e0833
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=445164406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.445164406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.2556661979
Short name	T689
Test name
Test status
Simulation time	84200114610 ps
CPU time	2156.22 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:55:12 PM PST 23
Peak memory	394152 kb
Host	smart-55501fe0-d1a3-42fe-a511-54618a39904d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2556661979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2556661979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.3790210998
Short name	T583
Test name
Test status
Simulation time	33359454086 ps
CPU time	1542.48 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:44:57 PM PST 23
Peak memory	342632 kb
Host	smart-77bac495-d57b-49a9-8d94-57792cc4a89e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3790210998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3790210998 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.3902256807
Short name	T272
Test name
Test status
Simulation time	34483364255 ps
CPU time	1381.76 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:42:24 PM PST 23
Peak memory	301128 kb
Host	smart-f2245850-e894-449a-8ec4-21a31e197e5f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3902256807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3902256807 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.1513571756
Short name	T381
Test name
Test status
Simulation time	118932916020 ps
CPU time	4775.42 seconds
Started	Dec 24 01:19:04 PM PST 23
Finished	Dec 24 02:38:57 PM PST 23
Peak memory	644584 kb
Host	smart-c2fac0ae-db62-491c-8fc6-c3f963ee0f9c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1513571756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.1513571756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.2082869074
Short name	T671
Test name
Test status
Simulation time	53317525777 ps
CPU time	4159.65 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 02:28:42 PM PST 23
Peak memory	564676 kb
Host	smart-90c2b98f-8886-49c0-a99a-936f9b452868
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2082869074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2082869074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.1743730973
Short name	T540
Test name
Test status
Simulation time	17601468 ps
CPU time	0.86 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	218456 kb
Host	smart-48d7baf7-eb10-4828-8d78-fc6d00023ff2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743730973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1743730973 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.2697739802
Short name	T816
Test name
Test status
Simulation time	1554020532 ps
CPU time	49.62 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:55 PM PST 23
Peak memory	229236 kb
Host	smart-9bf06570-3c94-4733-af8f-2fbfc5d572b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697739802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2697739802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.3393694797
Short name	T25
Test name
Test status
Simulation time	22857419754 ps
CPU time	1340.03 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:41:30 PM PST 23
Peak memory	238688 kb
Host	smart-ed03331a-e7a2-4eeb-9bad-4ff5e4cd996b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393694797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3393694797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.3806482128
Short name	T105
Test name
Test status
Simulation time	3035299882 ps
CPU time	32.94 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:41 PM PST 23
Peak memory	236068 kb
Host	smart-02e0ba2e-d798-49db-9cf2-e40a7d8642d0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3806482128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3806482128 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.4170593467
Short name	T536
Test name
Test status
Simulation time	46328059 ps
CPU time	1.21 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:08 PM PST 23
Peak memory	218836 kb
Host	smart-1cea960f-7b80-47ae-ad80-05b2973b7cba
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4170593467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.4170593467 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_error.3731907153
Short name	T494
Test name
Test status
Simulation time	10212032482 ps
CPU time	74.55 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:20:23 PM PST 23
Peak memory	243180 kb
Host	smart-40f01f28-9c12-497a-8f88-8574246cbc38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3731907153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3731907153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.2311320427
Short name	T377
Test name
Test status
Simulation time	5057797992 ps
CPU time	6.32 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	218812 kb
Host	smart-02b45aed-d105-45b4-b6fd-976c3a5d689d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311320427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2311320427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.1924993890
Short name	T98
Test name
Test status
Simulation time	6432781774 ps
CPU time	62.77 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:20:01 PM PST 23
Peak memory	243496 kb
Host	smart-92aaeb59-0f2f-4aaa-85a5-90a1fcec26dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924993890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1924993890 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.745817990
Short name	T717
Test name
Test status
Simulation time	265660810794 ps
CPU time	1649.12 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:46:27 PM PST 23
Peak memory	349980 kb
Host	smart-dff7401e-80df-40b0-9981-a9fd643c22b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745817990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an d_output.745817990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.457239340
Short name	T495
Test name
Test status
Simulation time	977403063 ps
CPU time	38.3 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:42 PM PST 23
Peak memory	226720 kb
Host	smart-338006e4-5f93-41b8-bd4e-d6a8849c6c16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457239340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.457239340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.999445629
Short name	T586
Test name
Test status
Simulation time	3376079465 ps
CPU time	70.2 seconds
Started	Dec 24 01:19:11 PM PST 23
Finished	Dec 24 01:20:34 PM PST 23
Peak memory	224268 kb
Host	smart-d08c47d8-c505-4685-8428-ef557c0ae82b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999445629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.999445629 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.1761718406
Short name	T33
Test name
Test status
Simulation time	93899855076 ps
CPU time	2383.71 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:58:49 PM PST 23
Peak memory	448384 kb
Host	smart-255f1524-f1d8-456b-9a0b-36c1e94825ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1761718406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1761718406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.3322001750
Short name	T529
Test name
Test status
Simulation time	184281640 ps
CPU time	6.42 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	220380 kb
Host	smart-d8ca9f48-f635-4bf8-b1e6-809bd4536e62
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322001750 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.3322001750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.191371725
Short name	T1121
Test name
Test status
Simulation time	254135107 ps
CPU time	6.64 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	220400 kb
Host	smart-0b273b32-0c38-40ea-857b-1a2c15233c59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191371725 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.kmac_test_vectors_kmac_xof.191371725 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.821526704
Short name	T315
Test name
Test status
Simulation time	81844879907 ps
CPU time	1986.92 seconds
Started	Dec 24 01:18:39 PM PST 23
Finished	Dec 24 01:52:05 PM PST 23
Peak memory	400192 kb
Host	smart-031a7176-e715-4347-aa12-9a3c29874069
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=821526704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.821526704 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.1650089933
Short name	T221
Test name
Test status
Simulation time	194212446937 ps
CPU time	2286.82 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:57:11 PM PST 23
Peak memory	386584 kb
Host	smart-4f7893c5-8177-459a-a6e6-5ca8051b72c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1650089933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1650089933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.1689881974
Short name	T794
Test name
Test status
Simulation time	15497359093 ps
CPU time	1645.12 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:46:28 PM PST 23
Peak memory	342668 kb
Host	smart-4b9a7ea5-5248-4687-885f-f5b955c7a969
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1689881974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1689881974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.736657321
Short name	T295
Test name
Test status
Simulation time	13194197229 ps
CPU time	1114.05 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:37:40 PM PST 23
Peak memory	302152 kb
Host	smart-f7153f56-3870-413b-bf68-a6dab910ff7d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=736657321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.736657321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.3814215586
Short name	T459
Test name
Test status
Simulation time	236189659510 ps
CPU time	5441.79 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 02:49:38 PM PST 23
Peak memory	664072 kb
Host	smart-54203e3a-39b0-435d-831f-aad949c9cde6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3814215586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3814215586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.2955792051
Short name	T1077
Test name
Test status
Simulation time	150700376559 ps
CPU time	4687.17 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 02:37:17 PM PST 23
Peak memory	570192 kb
Host	smart-64872fb6-9d53-4983-aaf4-d68e7e3bd5d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2955792051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2955792051 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.908416486
Short name	T981
Test name
Test status
Simulation time	18201381 ps
CPU time	0.86 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	219756 kb
Host	smart-a4061a34-19b7-4d0e-8a94-b56ebde982a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908416486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.908416486 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.2125871558
Short name	T842
Test name
Test status
Simulation time	8187694046 ps
CPU time	105.54 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	243280 kb
Host	smart-26989628-4c22-4990-aafa-56808d9a9a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125871558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2125871558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.560310173
Short name	T442
Test name
Test status
Simulation time	61772449030 ps
CPU time	1158.32 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:38:27 PM PST 23
Peak memory	238944 kb
Host	smart-0afe4e0d-bf1f-43e4-a67d-4975f268b072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560310173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.560310173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.2260479011
Short name	T882
Test name
Test status
Simulation time	66454746 ps
CPU time	0.95 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:07 PM PST 23
Peak memory	218568 kb
Host	smart-ae748b60-6e43-4d4c-88b4-3b284f19df49
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2260479011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2260479011 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.4277817828
Short name	T1130
Test name
Test status
Simulation time	977239352 ps
CPU time	16.29 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:21 PM PST 23
Peak memory	227760 kb
Host	smart-c2c22032-0c84-40a1-818a-8312f8243ca9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4277817828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4277817828 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.1279317436
Short name	T665
Test name
Test status
Simulation time	287290774 ps
CPU time	5.35 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	219968 kb
Host	smart-0c0f3885-bf02-4f3a-8efe-129ee251c598
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279317436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1279317436 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.1377885146
Short name	T488
Test name
Test status
Simulation time	22224548636 ps
CPU time	195.95 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:22:20 PM PST 23
Peak memory	252736 kb
Host	smart-07922df8-f0fd-4398-81e8-70a1fcd67f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377885146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1377885146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.847080677
Short name	T379
Test name
Test status
Simulation time	1134081660 ps
CPU time	5.08 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	218724 kb
Host	smart-94582fe9-6279-4d44-be35-c7927997cd09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847080677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.847080677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.116854410
Short name	T316
Test name
Test status
Simulation time	416279861 ps
CPU time	1.2 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:19:00 PM PST 23
Peak memory	220208 kb
Host	smart-8c560958-9a44-482a-8377-331a83d76421
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116854410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.116854410 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.1218150442
Short name	T1032
Test name
Test status
Simulation time	153685729024 ps
CPU time	2043.5 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:53:10 PM PST 23
Peak memory	365780 kb
Host	smart-fa340da8-9ab9-4314-80f5-ec4a131ccc54
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218150442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.1218150442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.1928925664
Short name	T791
Test name
Test status
Simulation time	16697608941 ps
CPU time	356.04 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:25:05 PM PST 23
Peak memory	250456 kb
Host	smart-5bdae61a-f992-4bdc-9808-08e3790eb5e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928925664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1928925664 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.850990229
Short name	T396
Test name
Test status
Simulation time	887059642 ps
CPU time	15.89 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:19:14 PM PST 23
Peak memory	224280 kb
Host	smart-e3d93361-5f66-42ba-b56a-e5d40738a9f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850990229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.850990229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.3190849195
Short name	T706
Test name
Test status
Simulation time	8320183847 ps
CPU time	53.35 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:19:54 PM PST 23
Peak memory	239116 kb
Host	smart-ece497c0-c6bc-440e-ae53-8e9ef734647a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3190849195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3190849195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.2351275344
Short name	T329
Test name
Test status
Simulation time	271901927 ps
CPU time	6.44 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	220304 kb
Host	smart-1497cf92-bd88-4458-8bcd-5d7b0ab2ff22
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351275344 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.kmac_test_vectors_kmac.2351275344 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3470039821
Short name	T946
Test name
Test status
Simulation time	741388098 ps
CPU time	6.67 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	219972 kb
Host	smart-097258f5-7fb7-40a6-b8ca-e48743a93518
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470039821 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3470039821 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.2730013646
Short name	T592
Test name
Test status
Simulation time	1233018713014 ps
CPU time	2803.41 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 02:05:47 PM PST 23
Peak memory	405384 kb
Host	smart-281fbc2c-5381-4455-8e74-33fd348c0442
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2730013646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2730013646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.2108022544
Short name	T391
Test name
Test status
Simulation time	91191165312 ps
CPU time	2256.72 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:56:35 PM PST 23
Peak memory	383832 kb
Host	smart-9cf717d0-e78b-48c5-b13f-a9de746867bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2108022544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.2108022544 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.3773636191
Short name	T1035
Test name
Test status
Simulation time	14738824726 ps
CPU time	1524.9 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:44:36 PM PST 23
Peak memory	336860 kb
Host	smart-2199efac-d13e-4eaf-918f-c8c471957112
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3773636191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3773636191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.1104191133
Short name	T548
Test name
Test status
Simulation time	50571458304 ps
CPU time	1309.42 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:40:57 PM PST 23
Peak memory	300508 kb
Host	smart-448ca817-5cd4-4bd0-8347-0296eb8fc0d0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1104191133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1104191133 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.879547343
Short name	T787
Test name
Test status
Simulation time	83802330517 ps
CPU time	4932.29 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 02:41:16 PM PST 23
Peak memory	651416 kb
Host	smart-e7827a3e-2326-47ff-a913-56ebe2741fe0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=879547343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.879547343 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.1751035378
Short name	T614
Test name
Test status
Simulation time	930132134936 ps
CPU time	5552.82 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 02:51:41 PM PST 23
Peak memory	578460 kb
Host	smart-3b4e047f-8f21-42bd-b918-66afe23c866f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1751035378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1751035378 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.4169031970
Short name	T922
Test name
Test status
Simulation time	28358322 ps
CPU time	0.86 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	219728 kb
Host	smart-0b8506fc-d5f1-4988-9f07-e4d0ac74ff4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169031970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4169031970 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.2627521918
Short name	T989
Test name
Test status
Simulation time	7830062581 ps
CPU time	114.4 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:21:03 PM PST 23
Peak memory	236744 kb
Host	smart-43dcfcf4-9cd0-4326-8c05-697200ae519e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627521918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2627521918 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.2902046673
Short name	T937
Test name
Test status
Simulation time	30372807744 ps
CPU time	697.07 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:30:48 PM PST 23
Peak memory	235788 kb
Host	smart-5ac9ebe4-ce71-40d3-a5a0-aa5b92915e56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902046673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2902046673 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.2838183655
Short name	T864
Test name
Test status
Simulation time	12665475265 ps
CPU time	49.62 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:56 PM PST 23
Peak memory	238988 kb
Host	smart-f1ec4e82-f198-484c-b28b-ad4a80d597e6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2838183655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2838183655 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.1040170418
Short name	T895
Test name
Test status
Simulation time	59238288 ps
CPU time	0.94 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	218308 kb
Host	smart-aa10c78a-1f75-46ff-9873-46be0f3e9c53
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1040170418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1040170418 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.3937772146
Short name	T749
Test name
Test status
Simulation time	5699014230 ps
CPU time	147.54 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:21:38 PM PST 23
Peak memory	243280 kb
Host	smart-cf799643-3ef9-434f-bad9-5085b4974d1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937772146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3937772146 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.2643486895
Short name	T829
Test name
Test status
Simulation time	24436820370 ps
CPU time	196 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:22:30 PM PST 23
Peak memory	251472 kb
Host	smart-6d918575-5274-4047-b543-d01cd0e467f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643486895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2643486895 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.2366214474
Short name	T1061
Test name
Test status
Simulation time	766910065 ps
CPU time	1.86 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	218648 kb
Host	smart-dd67fa2f-15dc-4650-bdb6-fea5390e09a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366214474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2366214474 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.1600673226
Short name	T444
Test name
Test status
Simulation time	36849396 ps
CPU time	1.39 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	219884 kb
Host	smart-5a08a63e-696c-4614-b0f8-cd6d71bb0043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600673226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1600673226 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.720776685
Short name	T869
Test name
Test status
Simulation time	45854815191 ps
CPU time	1258.96 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:40:12 PM PST 23
Peak memory	322424 kb
Host	smart-08aac172-d7c0-41ed-b359-d248e3752099
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720776685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an d_output.720776685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.4067542309
Short name	T437
Test name
Test status
Simulation time	3162831695 ps
CPU time	281.75 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:23:49 PM PST 23
Peak memory	245812 kb
Host	smart-58591e0b-48a2-4815-a3f1-16a03b2d325b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067542309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.4067542309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.3188614217
Short name	T415
Test name
Test status
Simulation time	6097972867 ps
CPU time	38.49 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:49 PM PST 23
Peak memory	222940 kb
Host	smart-d83d8e36-7ac9-419a-8a78-9cb4600ceac9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188614217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3188614217 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.3502496558
Short name	T892
Test name
Test status
Simulation time	113448384978 ps
CPU time	1479.1 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:43:54 PM PST 23
Peak memory	358696 kb
Host	smart-f515d85f-f4b6-4311-b845-6ccc93d99caa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3502496558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3502496558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_stress_all_with_rand_reset.784412958
Short name	T354
Test name
Test status
Simulation time	83405104225 ps
CPU time	3006.37 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 02:09:23 PM PST 23
Peak memory	392572 kb
Host	smart-2ab114cd-333d-418d-88a7-7a6a06ac8c91
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=784412958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.784412958 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.2818084043
Short name	T909
Test name
Test status
Simulation time	380387971 ps
CPU time	5.95 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	218848 kb
Host	smart-cd2af99c-604d-492c-b7a6-a7bdb4cbdfc1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818084043 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.2818084043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.3292263892
Short name	T521
Test name
Test status
Simulation time	112861129 ps
CPU time	5.47 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:19:18 PM PST 23
Peak memory	218688 kb
Host	smart-cb421251-18a5-4897-b936-6ec386ea0170
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292263892 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.3292263892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.175056511
Short name	T615
Test name
Test status
Simulation time	20740177616 ps
CPU time	2045.52 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:53:12 PM PST 23
Peak memory	397840 kb
Host	smart-9dc99a33-2b12-47ed-82e7-009c867ec26e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=175056511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.175056511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.3800227945
Short name	T797
Test name
Test status
Simulation time	39046547568 ps
CPU time	1914.57 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:50:59 PM PST 23
Peak memory	387364 kb
Host	smart-1a7d6898-4108-4e04-a922-e9078339d555
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3800227945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3800227945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.2345390946
Short name	T1054
Test name
Test status
Simulation time	23020040474 ps
CPU time	1590.23 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:45:42 PM PST 23
Peak memory	337500 kb
Host	smart-c7dbaf16-7f46-4e21-9b2b-bf79b70106af
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2345390946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2345390946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.913082121
Short name	T288
Test name
Test status
Simulation time	34100267462 ps
CPU time	1273.99 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:40:22 PM PST 23
Peak memory	302284 kb
Host	smart-bad9d5b7-d411-494f-b722-dd265997cb25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=913082121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.913082121 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.2656094530
Short name	T1125
Test name
Test status
Simulation time	182361923161 ps
CPU time	5537.27 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 02:51:32 PM PST 23
Peak memory	647268 kb
Host	smart-60aff7d7-1e8e-4c18-a262-84df114eab2f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2656094530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2656094530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.1013309331
Short name	T478
Test name
Test status
Simulation time	314552860993 ps
CPU time	4757.74 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 02:38:28 PM PST 23
Peak memory	574360 kb
Host	smart-96d3c251-f32e-48b1-b5be-af81f0898f3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1013309331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.1013309331 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.3176231706
Short name	T1034
Test name
Test status
Simulation time	69899343 ps
CPU time	0.83 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:19:24 PM PST 23
Peak memory	218468 kb
Host	smart-6a0aedcf-c864-4565-96e0-ed9b4ea5998b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176231706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3176231706 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.3190538573
Short name	T550
Test name
Test status
Simulation time	55704798210 ps
CPU time	334.73 seconds
Started	Dec 24 01:19:04 PM PST 23
Finished	Dec 24 01:24:56 PM PST 23
Peak memory	250908 kb
Host	smart-3025ad86-c92e-4262-b0d5-aa94f8354a6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190538573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3190538573 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.1050584112
Short name	T692
Test name
Test status
Simulation time	132888345625 ps
CPU time	831.28 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:33:07 PM PST 23
Peak memory	238472 kb
Host	smart-605cdf76-091a-47e0-b076-f229a31a413b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050584112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1050584112 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.768941619
Short name	T72
Test name
Test status
Simulation time	45483517 ps
CPU time	0.99 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:19:20 PM PST 23
Peak memory	218536 kb
Host	smart-580acee5-0416-4384-b348-34a87cdebdd7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=768941619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.768941619 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.3133510599
Short name	T79
Test name
Test status
Simulation time	46064278 ps
CPU time	1.48 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:19:28 PM PST 23
Peak memory	217904 kb
Host	smart-92ac1416-52ba-4d4e-922f-08bafe5e6980
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3133510599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3133510599 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.2281964487
Short name	T276
Test name
Test status
Simulation time	10103510291 ps
CPU time	139.75 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:21:44 PM PST 23
Peak memory	240408 kb
Host	smart-57906def-df1e-4ce9-b1cb-3d1d1446f15f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281964487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2281964487 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_error.1021400963
Short name	T397
Test name
Test status
Simulation time	8758336737 ps
CPU time	148.64 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:21:51 PM PST 23
Peak memory	251604 kb
Host	smart-b6e041f2-7110-49bf-b623-d768a4ec98e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021400963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1021400963 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_key_error.3273315228
Short name	T604
Test name
Test status
Simulation time	328143417 ps
CPU time	2.68 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	218652 kb
Host	smart-71de4a8d-c183-4ffa-bbe3-c6c8b9a1bda7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273315228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3273315228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.3215558967
Short name	T482
Test name
Test status
Simulation time	43961043 ps
CPU time	1.55 seconds
Started	Dec 24 01:19:02 PM PST 23
Finished	Dec 24 01:19:22 PM PST 23
Peak memory	219848 kb
Host	smart-dd1708f7-9f4b-472b-8262-21106ba58313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215558967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3215558967 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.1958082687
Short name	T436
Test name
Test status
Simulation time	121774250384 ps
CPU time	3277.99 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 02:13:52 PM PST 23
Peak memory	499696 kb
Host	smart-ac356a49-9364-474b-b79c-1ca0295eec71
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958082687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.1958082687 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.1241329665
Short name	T964
Test name
Test status
Simulation time	10608113337 ps
CPU time	367.04 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:25:22 PM PST 23
Peak memory	250936 kb
Host	smart-955d0def-56e6-400d-98ef-d73901b8f2e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1241329665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1241329665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.74465983
Short name	T242
Test name
Test status
Simulation time	903316608 ps
CPU time	35.72 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:19:50 PM PST 23
Peak memory	219776 kb
Host	smart-8adadae8-55cf-4989-b8f8-53e583e1a1b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74465983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.74465983 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.4234975796
Short name	T814
Test name
Test status
Simulation time	125182200545 ps
CPU time	676.79 seconds
Started	Dec 24 01:19:03 PM PST 23
Finished	Dec 24 01:30:37 PM PST 23
Peak memory	317412 kb
Host	smart-0b04a9da-9057-4070-90e1-0951499518ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4234975796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.4234975796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.699635063
Short name	T719
Test name
Test status
Simulation time	563550823 ps
CPU time	5.97 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:19:30 PM PST 23
Peak memory	220208 kb
Host	smart-2e6da2a7-3e16-4cc2-872a-8ec2e3ba3788
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699635063 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.kmac_test_vectors_kmac.699635063 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3545651015
Short name	T180
Test name
Test status
Simulation time	349292304 ps
CPU time	5.6 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:19:24 PM PST 23
Peak memory	218844 kb
Host	smart-744f7823-e204-4b7a-b2cc-139f8ccb88f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545651015 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3545651015 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.579463797
Short name	T330
Test name
Test status
Simulation time	84774234745 ps
CPU time	1979.62 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:52:15 PM PST 23
Peak memory	397572 kb
Host	smart-9cedb3f6-040b-490b-b05c-c86c0cd079c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=579463797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.579463797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.1030262574
Short name	T891
Test name
Test status
Simulation time	19900022430 ps
CPU time	1902.29 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:50:58 PM PST 23
Peak memory	385724 kb
Host	smart-8a9d9f9f-e401-486d-a01b-1574a1ebd3ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1030262574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1030262574 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.1124749100
Short name	T264
Test name
Test status
Simulation time	14796895208 ps
CPU time	1514.91 seconds
Started	Dec 24 01:19:04 PM PST 23
Finished	Dec 24 01:44:36 PM PST 23
Peak memory	338280 kb
Host	smart-0daaaf15-fbf3-49ef-aadd-80c96700fcdc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1124749100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1124749100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.2147673207
Short name	T195
Test name
Test status
Simulation time	21048870184 ps
CPU time	1117.86 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:37:57 PM PST 23
Peak memory	301000 kb
Host	smart-0e9a4854-e528-4186-b32c-880c51853374
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2147673207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2147673207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.2160554497
Short name	T199
Test name
Test status
Simulation time	265697080036 ps
CPU time	4930.09 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 02:41:33 PM PST 23
Peak memory	640748 kb
Host	smart-5688d651-f18b-4f6d-8611-0b20baa4121d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2160554497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2160554497 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.2469985966
Short name	T789
Test name
Test status
Simulation time	55528698652 ps
CPU time	4334.6 seconds
Started	Dec 24 01:18:55 PM PST 23
Finished	Dec 24 02:31:33 PM PST 23
Peak memory	577224 kb
Host	smart-04eb5807-71f1-476d-a7c8-464c0ebd7512
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2469985966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2469985966 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.50571912
Short name	T531
Test name
Test status
Simulation time	17701611 ps
CPU time	0.87 seconds
Started	Dec 24 01:18:56 PM PST 23
Finished	Dec 24 01:19:19 PM PST 23
Peak memory	218612 kb
Host	smart-7d6cbf33-d175-4f5e-87ee-348e62cf5fe5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50571912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.50571912 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.3501659893
Short name	T695
Test name
Test status
Simulation time	30733155973 ps
CPU time	227.57 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:22:54 PM PST 23
Peak memory	243732 kb
Host	smart-924b9ba9-a635-428a-afb5-93e26ea892d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501659893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3501659893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.4035369024
Short name	T156
Test name
Test status
Simulation time	50199735398 ps
CPU time	647.25 seconds
Started	Dec 24 01:19:11 PM PST 23
Finished	Dec 24 01:30:11 PM PST 23
Peak memory	235644 kb
Host	smart-f46534d7-5299-42df-a96b-25b3723ade33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035369024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.4035369024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.1989571028
Short name	T623
Test name
Test status
Simulation time	24428302 ps
CPU time	1.03 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:09 PM PST 23
Peak memory	218612 kb
Host	smart-7474a725-4906-4099-9846-588b5522ffaf
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1989571028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1989571028 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.664089869
Short name	T1014
Test name
Test status
Simulation time	108745231 ps
CPU time	0.88 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	218488 kb
Host	smart-ec4316c0-267b-4dd8-b985-ab36ad028d72
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=664089869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.664089869 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.1030977344
Short name	T70
Test name
Test status
Simulation time	9955927504 ps
CPU time	257.01 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:23:31 PM PST 23
Peak memory	246868 kb
Host	smart-ec849fbf-78dc-477d-ae6e-56ac1a773025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030977344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1030977344 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.1844201504
Short name	T908
Test name
Test status
Simulation time	72604831515 ps
CPU time	464.7 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:26:58 PM PST 23
Peak memory	273308 kb
Host	smart-3c878e41-14b6-41dc-be99-cdc6e4faab68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844201504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1844201504 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.358578498
Short name	T833
Test name
Test status
Simulation time	694976419 ps
CPU time	4.63 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	218772 kb
Host	smart-f1afaf1b-11c0-4fe7-9233-87af222f080b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358578498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.358578498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.2730277140
Short name	T819
Test name
Test status
Simulation time	65604778 ps
CPU time	1.24 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	219684 kb
Host	smart-67bbbc80-6db3-44df-a679-617abc417e7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730277140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2730277140 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.243713955
Short name	T307
Test name
Test status
Simulation time	327429504602 ps
CPU time	2912.79 seconds
Started	Dec 24 01:19:09 PM PST 23
Finished	Dec 24 02:07:56 PM PST 23
Peak memory	451204 kb
Host	smart-a366d6f1-dce0-4e7d-9332-dfcfc10e6a70
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243713955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_an d_output.243713955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.528130442
Short name	T840
Test name
Test status
Simulation time	44667114573 ps
CPU time	381.78 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:25:28 PM PST 23
Peak memory	251832 kb
Host	smart-7ca0fd01-1407-44b7-8013-88a2d4445d5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528130442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.528130442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.2976679527
Short name	T345
Test name
Test status
Simulation time	2087723182 ps
CPU time	46.59 seconds
Started	Dec 24 01:19:09 PM PST 23
Finished	Dec 24 01:20:10 PM PST 23
Peak memory	222720 kb
Host	smart-eb1d70bc-fc44-473a-a69e-25809bba97a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976679527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2976679527 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.3014002839
Short name	T1070
Test name
Test status
Simulation time	5508456513 ps
CPU time	39.3 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	239944 kb
Host	smart-a9728f2b-fe09-484c-99ef-5b10d9aae606
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3014002839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3014002839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.3292191909
Short name	T670
Test name
Test status
Simulation time	111736614990 ps
CPU time	1948.2 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:51:42 PM PST 23
Peak memory	319944 kb
Host	smart-a6318176-3fcb-4109-9a55-ec3abba4d106
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3292191909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.3292191909 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.1528711743
Short name	T298
Test name
Test status
Simulation time	343221019 ps
CPU time	6.69 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:13 PM PST 23
Peak memory	218800 kb
Host	smart-2d80eb4d-a098-422a-bee2-a9ec3ef33204
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528711743 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.1528711743 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.4164694212
Short name	T635
Test name
Test status
Simulation time	294974826 ps
CPU time	6.35 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:18 PM PST 23
Peak memory	220180 kb
Host	smart-33236d4d-0a6c-4189-bee5-38571cbe2d0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164694212 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.4164694212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.382670176
Short name	T1023
Test name
Test status
Simulation time	22345250084 ps
CPU time	1908.25 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:50:56 PM PST 23
Peak memory	397140 kb
Host	smart-08d466e3-5fb2-4747-bfd2-bda776d01d05
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=382670176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.382670176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.1795346524
Short name	T1111
Test name
Test status
Simulation time	369048411302 ps
CPU time	2121.89 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:54:26 PM PST 23
Peak memory	393380 kb
Host	smart-f4e07972-2946-4212-83a8-55c4d4609335
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1795346524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1795346524 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.3339561975
Short name	T578
Test name
Test status
Simulation time	60410068682 ps
CPU time	1395.68 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:42:20 PM PST 23
Peak memory	341708 kb
Host	smart-cd63b334-8edf-4b8e-b741-60a6cd4d08be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3339561975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3339561975 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.821443292
Short name	T431
Test name
Test status
Simulation time	66210354021 ps
CPU time	1248.26 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:39:52 PM PST 23
Peak memory	303388 kb
Host	smart-0c1bcb36-8765-4729-887e-d46b05a6d966
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=821443292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.821443292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.463990768
Short name	T157
Test name
Test status
Simulation time	271645370250 ps
CPU time	5837.28 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 02:56:29 PM PST 23
Peak memory	667768 kb
Host	smart-b98338ed-c3cb-44ca-8519-e529f1b74bc7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=463990768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.463990768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.1438588288
Short name	T96
Test name
Test status
Simulation time	52433166 ps
CPU time	0.88 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:19:00 PM PST 23
Peak memory	218680 kb
Host	smart-ec45dd8f-ad89-4593-bad6-37a3da9221d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438588288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1438588288 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.1422179720
Short name	T824
Test name
Test status
Simulation time	18920471626 ps
CPU time	292.16 seconds
Started	Dec 24 01:18:23 PM PST 23
Finished	Dec 24 01:23:35 PM PST 23
Peak memory	248860 kb
Host	smart-b0573ef3-2f54-475b-abe3-21d969cbd3f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422179720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1422179720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.3530726848
Short name	T850
Test name
Test status
Simulation time	5080822343 ps
CPU time	339.94 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:24:23 PM PST 23
Peak memory	250440 kb
Host	smart-f6778382-470c-4213-9bbd-56338f25e9a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530726848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3530726848 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.1607161907
Short name	T843
Test name
Test status
Simulation time	16578899253 ps
CPU time	138.4 seconds
Started	Dec 24 01:17:54 PM PST 23
Finished	Dec 24 01:20:18 PM PST 23
Peak memory	228608 kb
Host	smart-e254993c-9aa4-44fa-9d9a-cf9d8ea1d298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607161907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1607161907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.4197170815
Short name	T293
Test name
Test status
Simulation time	40928766 ps
CPU time	0.88 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 01:18:49 PM PST 23
Peak memory	218496 kb
Host	smart-1cc35d80-314d-4247-b3d2-099a34363db4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4197170815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.4197170815 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.2465698263
Short name	T681
Test name
Test status
Simulation time	67554464 ps
CPU time	1.03 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	218468 kb
Host	smart-01215ec2-de72-47e4-b0f3-a49178f4da95
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2465698263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2465698263 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.2339541151
Short name	T37
Test name
Test status
Simulation time	5252869875 ps
CPU time	19.3 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	226352 kb
Host	smart-27806b09-8623-47a1-93ca-6b0f26058d08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339541151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2339541151 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.642513528
Short name	T538
Test name
Test status
Simulation time	12729533257 ps
CPU time	161.72 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 01:20:54 PM PST 23
Peak memory	239760 kb
Host	smart-44b32bda-5f65-4584-9f03-3f352229227f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642513528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.642513528 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.3111963593
Short name	T134
Test name
Test status
Simulation time	6411641003 ps
CPU time	124.83 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:20:48 PM PST 23
Peak memory	251512 kb
Host	smart-0297d26f-45ab-4386-ac42-3d3ad5d2a4b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111963593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3111963593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.545280977
Short name	T1024
Test name
Test status
Simulation time	1180192171 ps
CPU time	1.29 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:18:45 PM PST 23
Peak memory	218496 kb
Host	smart-63dfad5c-3ea8-4f11-8f00-022302fda704
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545280977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.545280977 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.2836560622
Short name	T893
Test name
Test status
Simulation time	28383625 ps
CPU time	1.4 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:07 PM PST 23
Peak memory	219892 kb
Host	smart-562c07db-b93b-4a99-8efe-cd01835bc028
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836560622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2836560622 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.2120961583
Short name	T346
Test name
Test status
Simulation time	62559902167 ps
CPU time	597.9 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 01:28:10 PM PST 23
Peak memory	269004 kb
Host	smart-a1be02f8-a47b-4dee-ac35-4916d88b0493
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120961583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.2120961583 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.3698188761
Short name	T849
Test name
Test status
Simulation time	3941189491 ps
CPU time	72.87 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 01:19:56 PM PST 23
Peak memory	234260 kb
Host	smart-03ffb399-19dc-4a51-b35b-28bd644f4085
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698188761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3698188761 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.4005249693
Short name	T93
Test name
Test status
Simulation time	17443884765 ps
CPU time	41.69 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:45 PM PST 23
Peak memory	258588 kb
Host	smart-d4740b6e-4b20-4808-a800-a09ea35b5697
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005249693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4005249693 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.353971832
Short name	T703
Test name
Test status
Simulation time	6491458868 ps
CPU time	236.37 seconds
Started	Dec 24 01:18:20 PM PST 23
Finished	Dec 24 01:22:29 PM PST 23
Peak memory	244220 kb
Host	smart-ede550de-47f6-4c1d-87f7-4f9a205ef589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353971832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.353971832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.4202470754
Short name	T838
Test name
Test status
Simulation time	2685511236 ps
CPU time	32.25 seconds
Started	Dec 24 01:18:07 PM PST 23
Finished	Dec 24 01:18:40 PM PST 23
Peak memory	224704 kb
Host	smart-003fdc9e-d3fc-44f8-a30e-1bb62ba04b8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202470754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.4202470754 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.3731235094
Short name	T658
Test name
Test status
Simulation time	48008394692 ps
CPU time	1841.49 seconds
Started	Dec 24 01:18:37 PM PST 23
Finished	Dec 24 01:49:36 PM PST 23
Peak memory	391088 kb
Host	smart-db00f469-3f5d-4882-9a9e-ad18bd1b9950
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3731235094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3731235094 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.3403690619
Short name	T247
Test name
Test status
Simulation time	109338257 ps
CPU time	5.18 seconds
Started	Dec 24 01:18:23 PM PST 23
Finished	Dec 24 01:18:48 PM PST 23
Peak memory	218860 kb
Host	smart-6fc3238c-3c03-4342-bc31-53eb4c3bd0f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403690619 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.3403690619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2163553736
Short name	T235
Test name
Test status
Simulation time	264358679 ps
CPU time	6.67 seconds
Started	Dec 24 01:18:32 PM PST 23
Finished	Dec 24 01:18:57 PM PST 23
Peak memory	220208 kb
Host	smart-6aaa3036-f02b-4ba8-bf9b-8dab388d040a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163553736 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2163553736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.66402553
Short name	T523
Test name
Test status
Simulation time	202808610449 ps
CPU time	2530.56 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 02:00:25 PM PST 23
Peak memory	399068 kb
Host	smart-d369da5b-3d84-4206-9638-20a4818be77e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=66402553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.66402553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.153435642
Short name	T958
Test name
Test status
Simulation time	34966443134 ps
CPU time	1868.37 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:49:22 PM PST 23
Peak memory	388080 kb
Host	smart-f0db3a98-aba2-4ce8-8a6e-a8d2bf137e79
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=153435642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.153435642 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.773253640
Short name	T994
Test name
Test status
Simulation time	74040430703 ps
CPU time	1591.71 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:44:45 PM PST 23
Peak memory	345876 kb
Host	smart-fc86122d-9473-421d-b348-21e3f14cc659
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=773253640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.773253640 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.889674522
Short name	T260
Test name
Test status
Simulation time	196497374227 ps
CPU time	1410.68 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 01:41:45 PM PST 23
Peak memory	301616 kb
Host	smart-aa79e448-3c44-4e33-96c5-542f3fcb2c3b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=889674522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.889674522 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.937978862
Short name	T711
Test name
Test status
Simulation time	924524543667 ps
CPU time	5755.59 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 02:54:54 PM PST 23
Peak memory	643408 kb
Host	smart-fa2b4b13-5874-469f-a3c8-62f1d8730a38
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=937978862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.937978862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.392925330
Short name	T1050
Test name
Test status
Simulation time	170346044469 ps
CPU time	4645.3 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 02:35:39 PM PST 23
Peak memory	561240 kb
Host	smart-288566b1-ae67-4a5d-8aaf-424033c58ea2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=392925330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.392925330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.773924994
Short name	T218
Test name
Test status
Simulation time	27005815 ps
CPU time	0.83 seconds
Started	Dec 24 01:18:55 PM PST 23
Finished	Dec 24 01:19:19 PM PST 23
Peak memory	218508 kb
Host	smart-0c1ad3dd-7ccf-428b-95ba-decb16f96fd4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773924994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.773924994 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.1389167415
Short name	T500
Test name
Test status
Simulation time	5472308325 ps
CPU time	154.75 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:21:54 PM PST 23
Peak memory	240724 kb
Host	smart-bff72820-80e8-4aef-b868-a4a46b746be1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389167415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1389167415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.3139188682
Short name	T299
Test name
Test status
Simulation time	116787780984 ps
CPU time	1131.42 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:37:59 PM PST 23
Peak memory	243192 kb
Host	smart-4f252cd8-eb4c-412b-b3b2-4ad320517673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139188682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3139188682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.3451320523
Short name	T1094
Test name
Test status
Simulation time	9491425998 ps
CPU time	187.73 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:22:27 PM PST 23
Peak memory	239504 kb
Host	smart-d6133dd0-a127-413d-9971-b591b5e87d18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451320523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3451320523 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_error.126747457
Short name	T844
Test name
Test status
Simulation time	5205379825 ps
CPU time	218.56 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:22:42 PM PST 23
Peak memory	259692 kb
Host	smart-69128d37-472e-48fe-b189-fcd0f38172f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126747457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.126747457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/20.kmac_key_error.545450319
Short name	T782
Test name
Test status
Simulation time	1920900526 ps
CPU time	4.77 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:19:13 PM PST 23
Peak memory	218612 kb
Host	smart-b65031a8-0682-4a68-8f93-4e06106394af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545450319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.545450319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.2627756693
Short name	T618
Test name
Test status
Simulation time	35551678 ps
CPU time	1.58 seconds
Started	Dec 24 01:18:55 PM PST 23
Finished	Dec 24 01:19:20 PM PST 23
Peak memory	220164 kb
Host	smart-2b211cca-3451-4e88-8cb0-41e599bb89ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627756693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2627756693 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.272329973
Short name	T983
Test name
Test status
Simulation time	67477100374 ps
CPU time	94.17 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:20:45 PM PST 23
Peak memory	235816 kb
Host	smart-34f9385b-301b-40c3-bb91-b6b279e7164c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272329973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an d_output.272329973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.1250424135
Short name	T177
Test name
Test status
Simulation time	8943252412 ps
CPU time	211.23 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:22:45 PM PST 23
Peak memory	242944 kb
Host	smart-d1423d47-550f-443c-bc4e-c421b9ae711b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250424135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1250424135 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.1945122732
Short name	T294
Test name
Test status
Simulation time	1074001880 ps
CPU time	42.79 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:57 PM PST 23
Peak memory	222768 kb
Host	smart-eaee373c-3b51-47bb-aced-646c134c188a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945122732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1945122732 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.4226234089
Short name	T292
Test name
Test status
Simulation time	1170743915737 ps
CPU time	1974.67 seconds
Started	Dec 24 01:19:02 PM PST 23
Finished	Dec 24 01:52:15 PM PST 23
Peak memory	438108 kb
Host	smart-5274a8d7-0fb1-4b90-bdda-fa925db2a167
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4226234089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.4226234089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.293502124
Short name	T860
Test name
Test status
Simulation time	235863757 ps
CPU time	6.07 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:19:25 PM PST 23
Peak memory	218864 kb
Host	smart-d3505ae9-b0c1-40cc-a1be-3db7546b9dbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293502124 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.kmac_test_vectors_kmac.293502124 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.434731047
Short name	T594
Test name
Test status
Simulation time	268122420 ps
CPU time	7.2 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	220156 kb
Host	smart-589f83be-8211-4ee0-bf6a-200aff224b1b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434731047 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 20.kmac_test_vectors_kmac_xof.434731047 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.1851955031
Short name	T970
Test name
Test status
Simulation time	67118768055 ps
CPU time	2075.28 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 01:53:52 PM PST 23
Peak memory	391508 kb
Host	smart-514928c8-2256-4e41-8882-948dbcaecd06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1851955031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1851955031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.3303510604
Short name	T720
Test name
Test status
Simulation time	20366535933 ps
CPU time	1917.26 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:51:12 PM PST 23
Peak memory	389608 kb
Host	smart-990a3a89-c06b-4a92-a79d-f496930dd922
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3303510604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3303510604 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.119832418
Short name	T657
Test name
Test status
Simulation time	396506450394 ps
CPU time	1773.25 seconds
Started	Dec 24 01:19:01 PM PST 23
Finished	Dec 24 01:48:53 PM PST 23
Peak memory	341544 kb
Host	smart-e7034abd-99a1-43b7-abab-8bf0c4cee094
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=119832418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.119832418 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.3898062053
Short name	T770
Test name
Test status
Simulation time	42342004672 ps
CPU time	1181.94 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:38:57 PM PST 23
Peak memory	306508 kb
Host	smart-1b4f3a52-0c92-4222-a66d-b0b54afc7d3a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3898062053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3898062053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.3399061127
Short name	T881
Test name
Test status
Simulation time	128097068849 ps
CPU time	4774.53 seconds
Started	Dec 24 01:18:53 PM PST 23
Finished	Dec 24 02:38:51 PM PST 23
Peak memory	643776 kb
Host	smart-ba85369d-b58e-495e-b874-91b973884b11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3399061127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3399061127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.2079352102
Short name	T229
Test name
Test status
Simulation time	216923487662 ps
CPU time	4473.46 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 02:33:56 PM PST 23
Peak memory	567352 kb
Host	smart-0ab72e21-7f95-4050-8543-9efb497651fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2079352102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2079352102 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.277614946
Short name	T589
Test name
Test status
Simulation time	85286340 ps
CPU time	0.82 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	219720 kb
Host	smart-584868df-5026-4c8a-b870-8512fdcd5c18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277614946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.277614946 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.3373643603
Short name	T949
Test name
Test status
Simulation time	11134183408 ps
CPU time	306.06 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:24:30 PM PST 23
Peak memory	249904 kb
Host	smart-00ed37ef-83f2-472e-84ed-e95d18119fba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373643603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3373643603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.3106861319
Short name	T581
Test name
Test status
Simulation time	31112656844 ps
CPU time	772.86 seconds
Started	Dec 24 01:19:13 PM PST 23
Finished	Dec 24 01:32:17 PM PST 23
Peak memory	237076 kb
Host	smart-9418729f-f68c-4576-83bc-d26fb6f8dcbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106861319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3106861319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.1638157857
Short name	T358
Test name
Test status
Simulation time	9900028698 ps
CPU time	255.57 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:23:40 PM PST 23
Peak memory	248276 kb
Host	smart-c88f0733-167f-4757-aeb2-ba20ac0c6c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638157857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1638157857 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_error.921605230
Short name	T875
Test name
Test status
Simulation time	12593212497 ps
CPU time	278.31 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:24:04 PM PST 23
Peak memory	255800 kb
Host	smart-65539fc8-e63b-4954-8f18-ff13754d7bff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921605230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.921605230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.1727976961
Short name	T99
Test name
Test status
Simulation time	1073550527 ps
CPU time	4.35 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	218728 kb
Host	smart-04546585-ca35-4cb1-a4a9-a67f38e1c386
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727976961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1727976961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.1539736304
Short name	T423
Test name
Test status
Simulation time	186680261 ps
CPU time	4.08 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	227104 kb
Host	smart-6df7bb6e-3efe-409e-8d96-e56dff48d462
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539736304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1539736304 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.3506465350
Short name	T1015
Test name
Test status
Simulation time	73766625001 ps
CPU time	1938.09 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:51:45 PM PST 23
Peak memory	361740 kb
Host	smart-53830a1c-c539-47ee-8e98-b1cc2460a976
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506465350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.3506465350 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_smoke.2469709814
Short name	T746
Test name
Test status
Simulation time	4758670901 ps
CPU time	89.44 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:20:51 PM PST 23
Peak memory	226900 kb
Host	smart-cd265c0d-aa1c-4eff-a3f8-1bb0f57be7c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469709814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2469709814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.3856319568
Short name	T1062
Test name
Test status
Simulation time	28436406200 ps
CPU time	1017.79 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:36:22 PM PST 23
Peak memory	356968 kb
Host	smart-756af8c7-a5d2-4fe7-bf41-2c5660855d64
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3856319568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3856319568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.3528871042
Short name	T640
Test name
Test status
Simulation time	1273200510 ps
CPU time	6.37 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	220164 kb
Host	smart-ae04bb05-0eb6-4c40-8021-9c90e8162199
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528871042 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.3528871042 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.489895309
Short name	T1017
Test name
Test status
Simulation time	416691817 ps
CPU time	6.52 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	220220 kb
Host	smart-a5fe550d-650c-44b6-88f2-092cef7f1c0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489895309 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 21.kmac_test_vectors_kmac_xof.489895309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.3919281063
Short name	T1100
Test name
Test status
Simulation time	115970473446 ps
CPU time	2052.3 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:53:37 PM PST 23
Peak memory	398624 kb
Host	smart-d2c58db9-0542-4d75-945e-11d8c38efab2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3919281063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3919281063 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.3980725809
Short name	T629
Test name
Test status
Simulation time	214724429917 ps
CPU time	2305.56 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:57:50 PM PST 23
Peak memory	391952 kb
Host	smart-25b97c78-4154-4448-a6a3-326e1b361dd8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3980725809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3980725809 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.2521401658
Short name	T741
Test name
Test status
Simulation time	31584645489 ps
CPU time	1544.84 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:45:11 PM PST 23
Peak memory	343496 kb
Host	smart-6e817435-7b1d-41be-ab3e-cba675d72cc1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2521401658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2521401658 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.2080527682
Short name	T468
Test name
Test status
Simulation time	191671973996 ps
CPU time	1277.14 seconds
Started	Dec 24 01:19:11 PM PST 23
Finished	Dec 24 01:40:41 PM PST 23
Peak memory	297888 kb
Host	smart-37e83da8-c5d3-48a1-89b6-41612181cfe3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2080527682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2080527682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.1329860498
Short name	T418
Test name
Test status
Simulation time	1080068555699 ps
CPU time	6242.38 seconds
Started	Dec 24 01:19:00 PM PST 23
Finished	Dec 24 03:03:23 PM PST 23
Peak memory	660532 kb
Host	smart-24f1c25b-2f42-4b32-9f86-ca67939b9cb7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1329860498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.1329860498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.2771436967
Short name	T471
Test name
Test status
Simulation time	1263167353455 ps
CPU time	4930.1 seconds
Started	Dec 24 01:19:09 PM PST 23
Finished	Dec 24 02:41:34 PM PST 23
Peak memory	553272 kb
Host	smart-bb520dad-2a43-4b44-82d7-25c3a624aaa0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2771436967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2771436967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.1992138398
Short name	T208
Test name
Test status
Simulation time	31494746 ps
CPU time	0.83 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	218476 kb
Host	smart-4548bb17-d570-4259-bbd9-d2b807b3f6a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992138398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1992138398 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.534725594
Short name	T422
Test name
Test status
Simulation time	3211553436 ps
CPU time	151.17 seconds
Started	Dec 24 01:19:09 PM PST 23
Finished	Dec 24 01:21:54 PM PST 23
Peak memory	241320 kb
Host	smart-596a1419-a144-4046-9d69-97a799048deb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534725594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.534725594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.581695323
Short name	T537
Test name
Test status
Simulation time	5085345215 ps
CPU time	469.3 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:27:08 PM PST 23
Peak memory	242128 kb
Host	smart-14416a3f-aaa1-496a-b9eb-2fabd134a371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581695323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.581695323 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.189916355
Short name	T76
Test name
Test status
Simulation time	51113230559 ps
CPU time	367.91 seconds
Started	Dec 24 01:19:11 PM PST 23
Finished	Dec 24 01:25:32 PM PST 23
Peak memory	250380 kb
Host	smart-4e47f32c-0406-4a09-b6fb-fc773a02c5b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189916355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.189916355 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.1993191916
Short name	T46
Test name
Test status
Simulation time	1122486514 ps
CPU time	86.71 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:20:46 PM PST 23
Peak memory	242468 kb
Host	smart-f43f53d8-99b8-48c8-b2c5-7ffe82c4f161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993191916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1993191916 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.832963284
Short name	T40
Test name
Test status
Simulation time	1038588343 ps
CPU time	6.24 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	218664 kb
Host	smart-1785249d-1a74-4c81-b365-8508076e4681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832963284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.832963284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.2530832720
Short name	T341
Test name
Test status
Simulation time	2801331510 ps
CPU time	30.36 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:19:55 PM PST 23
Peak memory	236428 kb
Host	smart-abc2e2b4-0681-4296-a0db-c62fbb8951ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530832720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2530832720 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.365525045
Short name	T848
Test name
Test status
Simulation time	389027776 ps
CPU time	5.41 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:19:32 PM PST 23
Peak memory	226204 kb
Host	smart-c69e8297-41fe-4f2c-98cc-d90d66707ca7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365525045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an d_output.365525045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.2543249054
Short name	T680
Test name
Test status
Simulation time	26648263260 ps
CPU time	110.13 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:21:12 PM PST 23
Peak memory	234996 kb
Host	smart-7b600de0-4777-4f74-9bd7-5657229585aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543249054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2543249054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.2664488319
Short name	T546
Test name
Test status
Simulation time	7467466473 ps
CPU time	62.81 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:20:29 PM PST 23
Peak memory	227016 kb
Host	smart-2482e80b-ef2e-4d11-8838-6891dc920f5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664488319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2664488319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.218794632
Short name	T580
Test name
Test status
Simulation time	8448492487 ps
CPU time	751.21 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:31:56 PM PST 23
Peak memory	299480 kb
Host	smart-3b663849-7ae7-4636-a7ee-58bc51951029
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=218794632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.218794632 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_stress_all_with_rand_reset.3521136211
Short name	T793
Test name
Test status
Simulation time	24624546863 ps
CPU time	1062.04 seconds
Started	Dec 24 01:19:06 PM PST 23
Finished	Dec 24 01:37:04 PM PST 23
Peak memory	333736 kb
Host	smart-6b074206-a329-4122-a810-5299c0cf9026
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3521136211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all_with_rand_reset.3521136211 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.1098233331
Short name	T362
Test name
Test status
Simulation time	1037904006 ps
CPU time	6.85 seconds
Started	Dec 24 01:19:09 PM PST 23
Finished	Dec 24 01:19:30 PM PST 23
Peak memory	218692 kb
Host	smart-4814f2f8-8ff3-4e08-900b-959cc6d69bde
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098233331 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.1098233331 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.688736773
Short name	T887
Test name
Test status
Simulation time	268958221 ps
CPU time	6.35 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:19:29 PM PST 23
Peak memory	220220 kb
Host	smart-e02a5355-d527-4b2a-9ac6-b2b2a9db6475
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688736773 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 22.kmac_test_vectors_kmac_xof.688736773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.3402221238
Short name	T751
Test name
Test status
Simulation time	84770550165 ps
CPU time	1937.76 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:51:40 PM PST 23
Peak memory	394068 kb
Host	smart-fd91ce50-f04c-4481-928d-e16ff32d7ccb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3402221238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3402221238 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.3763857729
Short name	T962
Test name
Test status
Simulation time	19155288587 ps
CPU time	1872.44 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:50:35 PM PST 23
Peak memory	383628 kb
Host	smart-3cddac2c-89cd-4f07-a785-8bae18359e34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3763857729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3763857729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.2274148416
Short name	T560
Test name
Test status
Simulation time	55009859554 ps
CPU time	1646.98 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:46:46 PM PST 23
Peak memory	340164 kb
Host	smart-dd312628-d1ff-4e71-b4fd-bae311bafe01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2274148416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2274148416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.2733136663
Short name	T627
Test name
Test status
Simulation time	45448830593 ps
CPU time	1278.36 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:40:37 PM PST 23
Peak memory	303108 kb
Host	smart-47739c46-787d-453b-a851-271315e6c435
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2733136663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2733136663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.2583306332
Short name	T666
Test name
Test status
Simulation time	792864005258 ps
CPU time	5182.6 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 02:45:45 PM PST 23
Peak memory	634396 kb
Host	smart-cc1b98cb-66b3-49b5-a249-daf96ab52ab3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2583306332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.2583306332 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.3128919803
Short name	T889
Test name
Test status
Simulation time	106933436172 ps
CPU time	4269.9 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 02:30:33 PM PST 23
Peak memory	569592 kb
Host	smart-2cc1b077-edf3-4a7b-a6dd-45ae611ede2b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3128919803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3128919803 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.3910196481
Short name	T317
Test name
Test status
Simulation time	37078066 ps
CPU time	0.84 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:19:25 PM PST 23
Peak memory	218624 kb
Host	smart-b671d001-2e74-443d-b2ed-28010afac910
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910196481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3910196481 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.920431047
Short name	T669
Test name
Test status
Simulation time	3868007842 ps
CPU time	229.58 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:23:08 PM PST 23
Peak memory	247140 kb
Host	smart-1513bde5-0a41-4958-b224-534679f6a912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920431047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.920431047 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.2229831152
Short name	T405
Test name
Test status
Simulation time	35555343906 ps
CPU time	1015.75 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:36:18 PM PST 23
Peak memory	243328 kb
Host	smart-2d77359b-ad43-4481-9ae9-611af2e9002b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229831152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2229831152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.1913556182
Short name	T516
Test name
Test status
Simulation time	35737830949 ps
CPU time	376.52 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:25:39 PM PST 23
Peak memory	252760 kb
Host	smart-32e79fda-914f-4441-9c81-db57782f3c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913556182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1913556182 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.920886452
Short name	T815
Test name
Test status
Simulation time	76828581332 ps
CPU time	498.73 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:27:38 PM PST 23
Peak memory	268020 kb
Host	smart-8e026367-f65a-46a8-a8ac-edfa48d52749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920886452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.920886452 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_key_error.154259621
Short name	T369
Test name
Test status
Simulation time	427790376 ps
CPU time	3.07 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	218560 kb
Host	smart-648bd29c-dbe5-4786-b943-858e1723c53b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154259621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.154259621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.1498719444
Short name	T702
Test name
Test status
Simulation time	94617018 ps
CPU time	1.36 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:19:23 PM PST 23
Peak memory	221612 kb
Host	smart-5ac65e51-7bf5-4bb5-b329-e60a9dd4dcc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498719444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1498719444 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2202288055
Short name	T890
Test name
Test status
Simulation time	28120592550 ps
CPU time	668.06 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:30:32 PM PST 23
Peak memory	273328 kb
Host	smart-5ddd0bc3-8a97-4df0-b25b-5800c3214484
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202288055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2202288055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.4290224790
Short name	T464
Test name
Test status
Simulation time	2615995149 ps
CPU time	187.9 seconds
Started	Dec 24 01:19:08 PM PST 23
Finished	Dec 24 01:22:30 PM PST 23
Peak memory	240944 kb
Host	smart-7b186c10-8885-4313-baee-60d51868b6d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290224790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4290224790 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.1580101438
Short name	T193
Test name
Test status
Simulation time	638008542 ps
CPU time	24.98 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	226960 kb
Host	smart-5f355168-0b71-4ab4-9144-a392911b0653
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580101438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1580101438 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.3787843016
Short name	T1057
Test name
Test status
Simulation time	91702600721 ps
CPU time	2650.78 seconds
Started	Dec 24 01:19:04 PM PST 23
Finished	Dec 24 02:03:32 PM PST 23
Peak memory	421060 kb
Host	smart-fd723909-12f3-4b9c-81c1-df0d3c2080cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3787843016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3787843016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_stress_all_with_rand_reset.4210476309
Short name	T601
Test name
Test status
Simulation time	25492949422 ps
CPU time	819.28 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 01:33:01 PM PST 23
Peak memory	309000 kb
Host	smart-2bc32ed4-953b-423b-8345-b199fe9ef0ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4210476309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.4210476309 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.379179560
Short name	T650
Test name
Test status
Simulation time	961832932 ps
CPU time	6.98 seconds
Started	Dec 24 01:19:03 PM PST 23
Finished	Dec 24 01:19:28 PM PST 23
Peak memory	220288 kb
Host	smart-58c718e9-7c0e-4335-a2e1-62f93e2dbeea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379179560 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.kmac_test_vectors_kmac.379179560 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3085451419
Short name	T268
Test name
Test status
Simulation time	351374020 ps
CPU time	5.7 seconds
Started	Dec 24 01:19:13 PM PST 23
Finished	Dec 24 01:19:30 PM PST 23
Peak memory	220048 kb
Host	smart-e794ad31-a4d2-4c6c-b466-26c509d4c28d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085451419 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3085451419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.603749801
Short name	T852
Test name
Test status
Simulation time	551158053316 ps
CPU time	2370.6 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:58:50 PM PST 23
Peak memory	401752 kb
Host	smart-899db3e6-821a-40d5-a87a-dab2643763b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=603749801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.603749801 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.4067662029
Short name	T384
Test name
Test status
Simulation time	255939471110 ps
CPU time	2155.93 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:55:20 PM PST 23
Peak memory	385808 kb
Host	smart-86b3e673-4240-4611-b701-7745a98bf328
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4067662029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.4067662029 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.973138528
Short name	T1063
Test name
Test status
Simulation time	237549966045 ps
CPU time	1784.07 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:49:03 PM PST 23
Peak memory	344972 kb
Host	smart-074142fb-817b-4f3b-b399-2c2b41652fbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=973138528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.973138528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.2144393589
Short name	T311
Test name
Test status
Simulation time	48193600582 ps
CPU time	1326.58 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:41:26 PM PST 23
Peak memory	298528 kb
Host	smart-18d45a1d-a221-4c20-a5ad-3c108e249471
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2144393589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2144393589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.2678906040
Short name	T646
Test name
Test status
Simulation time	1035739274055 ps
CPU time	5497.5 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 02:51:02 PM PST 23
Peak memory	659300 kb
Host	smart-23e95636-4847-4f79-bd6a-a2d4da4072a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2678906040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2678906040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.3201960835
Short name	T831
Test name
Test status
Simulation time	53246357111 ps
CPU time	4402.7 seconds
Started	Dec 24 01:19:05 PM PST 23
Finished	Dec 24 02:32:45 PM PST 23
Peak memory	569684 kb
Host	smart-ff4cc352-b7ff-47d6-945f-19b56ebc9881
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3201960835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3201960835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.2773373999
Short name	T736
Test name
Test status
Simulation time	22184468 ps
CPU time	0.89 seconds
Started	Dec 24 01:19:15 PM PST 23
Finished	Dec 24 01:19:26 PM PST 23
Peak memory	219792 kb
Host	smart-75c7f177-5b6d-41a5-986e-2a2258d64a3e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773373999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2773373999 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.481398805
Short name	T777
Test name
Test status
Simulation time	28032253945 ps
CPU time	297.42 seconds
Started	Dec 24 01:19:15 PM PST 23
Finished	Dec 24 01:24:23 PM PST 23
Peak memory	249608 kb
Host	smart-25ccf3a0-0b61-48a5-86e0-1ee03329ebec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481398805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.481398805 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.844168322
Short name	T664
Test name
Test status
Simulation time	55534382438 ps
CPU time	1479.28 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:43:58 PM PST 23
Peak memory	238832 kb
Host	smart-ae4d1d6a-114c-4889-a6fc-7cac713ba8ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844168322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.844168322 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.3817438598
Short name	T454
Test name
Test status
Simulation time	14263470711 ps
CPU time	115.65 seconds
Started	Dec 24 01:19:17 PM PST 23
Finished	Dec 24 01:21:22 PM PST 23
Peak memory	243256 kb
Host	smart-208479b1-76d7-49c0-b0ce-6ef4a5e40462
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817438598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3817438598 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.254785564
Short name	T934
Test name
Test status
Simulation time	59659935238 ps
CPU time	386.02 seconds
Started	Dec 24 01:19:17 PM PST 23
Finished	Dec 24 01:25:52 PM PST 23
Peak memory	267940 kb
Host	smart-c79bc2b6-36e7-4ade-acc1-2d13f3b4eaac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=254785564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.254785564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.2030858814
Short name	T100
Test name
Test status
Simulation time	1057656164 ps
CPU time	5.95 seconds
Started	Dec 24 01:19:17 PM PST 23
Finished	Dec 24 01:19:32 PM PST 23
Peak memory	218796 kb
Host	smart-3378955d-b322-46d1-896b-f8c8652c5492
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030858814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2030858814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.1515228372
Short name	T773
Test name
Test status
Simulation time	148554937 ps
CPU time	1.31 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:19:28 PM PST 23
Peak memory	219952 kb
Host	smart-973d4b76-0371-4953-a54c-ed83121576c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515228372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1515228372 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.979558817
Short name	T748
Test name
Test status
Simulation time	88558065643 ps
CPU time	2212.01 seconds
Started	Dec 24 01:19:01 PM PST 23
Finished	Dec 24 01:56:12 PM PST 23
Peak memory	400644 kb
Host	smart-e902ecf9-b60c-45b8-accb-fdaaca3e9e24
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979558817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an d_output.979558817 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.24737043
Short name	T697
Test name
Test status
Simulation time	14827042187 ps
CPU time	212.24 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:22:54 PM PST 23
Peak memory	241528 kb
Host	smart-26a7c9b1-56ec-48a1-8b4d-ffcab6e84477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24737043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.24737043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.3390144936
Short name	T220
Test name
Test status
Simulation time	2592705065 ps
CPU time	60.82 seconds
Started	Dec 24 01:18:57 PM PST 23
Finished	Dec 24 01:20:20 PM PST 23
Peak memory	224120 kb
Host	smart-5c0ea41f-178e-4b4f-a0c8-e9db4f0686cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390144936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3390144936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.2840284777
Short name	T817
Test name
Test status
Simulation time	33834347292 ps
CPU time	1002.97 seconds
Started	Dec 24 01:19:17 PM PST 23
Finished	Dec 24 01:36:09 PM PST 23
Peak memory	334060 kb
Host	smart-cf60382c-0faf-4e37-8426-add79596e0db
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2840284777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2840284777 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_stress_all_with_rand_reset.2696402481
Short name	T771
Test name
Test status
Simulation time	34308807615 ps
CPU time	1065.9 seconds
Started	Dec 24 01:19:20 PM PST 23
Finished	Dec 24 01:37:13 PM PST 23
Peak memory	311460 kb
Host	smart-579773b2-f559-4304-905c-a09b55a4cb59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2696402481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all_with_rand_reset.2696402481 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.1330894808
Short name	T182
Test name
Test status
Simulation time	2913565037 ps
CPU time	6.55 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:19:33 PM PST 23
Peak memory	220332 kb
Host	smart-5a722093-46de-4c2f-85a7-89e36b1f42b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330894808 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.1330894808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.218552905
Short name	T450
Test name
Test status
Simulation time	392207299 ps
CPU time	5.42 seconds
Started	Dec 24 01:19:23 PM PST 23
Finished	Dec 24 01:19:34 PM PST 23
Peak memory	220212 kb
Host	smart-0596354c-0ddf-45e8-9d85-983191722264
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218552905 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 24.kmac_test_vectors_kmac_xof.218552905 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.3200281321
Short name	T528
Test name
Test status
Simulation time	415246817157 ps
CPU time	1978.97 seconds
Started	Dec 24 01:18:58 PM PST 23
Finished	Dec 24 01:52:18 PM PST 23
Peak memory	393080 kb
Host	smart-fa121e2a-dede-42f2-bcb3-f8d391e8fe11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3200281321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.3200281321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.4073118122
Short name	T735
Test name
Test status
Simulation time	1181132926644 ps
CPU time	2634.68 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 02:03:21 PM PST 23
Peak memory	398284 kb
Host	smart-af3f62aa-7268-4522-8cf7-e1d7c0ddd890
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4073118122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.4073118122 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.2874749707
Short name	T845
Test name
Test status
Simulation time	90142875176 ps
CPU time	1698.96 seconds
Started	Dec 24 01:19:12 PM PST 23
Finished	Dec 24 01:47:43 PM PST 23
Peak memory	337248 kb
Host	smart-8c50a7c1-1fb2-4bbf-b1fd-f1f2e1861018
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2874749707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.2874749707 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.443085460
Short name	T870
Test name
Test status
Simulation time	344843004524 ps
CPU time	1323.41 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 01:41:26 PM PST 23
Peak memory	298972 kb
Host	smart-423e638c-821c-4414-afb4-1d3eb8b41d4d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=443085460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.443085460 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.3902093932
Short name	T372
Test name
Test status
Simulation time	61326393932 ps
CPU time	5140.31 seconds
Started	Dec 24 01:19:07 PM PST 23
Finished	Dec 24 02:45:03 PM PST 23
Peak memory	666524 kb
Host	smart-4e7b9195-7307-4552-8bd1-fab90e000e87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3902093932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3902093932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.3613287146
Short name	T248
Test name
Test status
Simulation time	213195877503 ps
CPU time	4376.64 seconds
Started	Dec 24 01:19:15 PM PST 23
Finished	Dec 24 02:32:22 PM PST 23
Peak memory	576476 kb
Host	smart-ea6e229f-c8ed-4097-8125-e674a250aed8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3613287146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.3613287146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.3714621114
Short name	T202
Test name
Test status
Simulation time	50007587 ps
CPU time	0.89 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:19:41 PM PST 23
Peak memory	219640 kb
Host	smart-a5aa0123-89d8-470c-9a32-aaf40495066e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714621114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3714621114 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.267130820
Short name	T1044
Test name
Test status
Simulation time	6400851822 ps
CPU time	183.87 seconds
Started	Dec 24 01:19:23 PM PST 23
Finished	Dec 24 01:22:32 PM PST 23
Peak memory	243372 kb
Host	smart-b3cfae0b-1e4d-47e9-a938-d23f4d9f77b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267130820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.267130820 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.2288716123
Short name	T334
Test name
Test status
Simulation time	40817969844 ps
CPU time	1044.62 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:36:51 PM PST 23
Peak memory	243412 kb
Host	smart-7447891a-204a-4e51-98e0-0f4796641a0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288716123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2288716123 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.2080062230
Short name	T595
Test name
Test status
Simulation time	10627528738 ps
CPU time	176.28 seconds
Started	Dec 24 01:19:27 PM PST 23
Finished	Dec 24 01:22:26 PM PST 23
Peak memory	239748 kb
Host	smart-b9c850cf-5fef-4a0c-9d84-ad4ea8f2257e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080062230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2080062230 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.1108995125
Short name	T135
Test name
Test status
Simulation time	8566813669 ps
CPU time	359.78 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:25:26 PM PST 23
Peak memory	268692 kb
Host	smart-10b7beb8-add0-457b-97f1-15ec82fa73ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108995125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1108995125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.1993601313
Short name	T632
Test name
Test status
Simulation time	80836636 ps
CPU time	1.11 seconds
Started	Dec 24 01:19:32 PM PST 23
Finished	Dec 24 01:19:34 PM PST 23
Peak memory	218520 kb
Host	smart-d52b53df-c3f2-4bc5-ad23-7c5de0f85457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993601313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1993601313 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.2740395413
Short name	T598
Test name
Test status
Simulation time	115240191 ps
CPU time	1.71 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:19:45 PM PST 23
Peak memory	221896 kb
Host	smart-36a67729-b9ed-440b-8162-80f4461359c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740395413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2740395413 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.3260679353
Short name	T498
Test name
Test status
Simulation time	17782933724 ps
CPU time	1808.79 seconds
Started	Dec 24 01:19:16 PM PST 23
Finished	Dec 24 01:49:34 PM PST 23
Peak memory	387796 kb
Host	smart-857e70ba-0c70-4c10-a94c-26cbf7f11101
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260679353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a nd_output.3260679353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.4066816359
Short name	T238
Test name
Test status
Simulation time	15373854295 ps
CPU time	377.24 seconds
Started	Dec 24 01:19:16 PM PST 23
Finished	Dec 24 01:25:43 PM PST 23
Peak memory	251420 kb
Host	smart-a7de5e76-122f-4ebb-8923-bea96a8bc75f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066816359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.4066816359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.2938088635
Short name	T645
Test name
Test status
Simulation time	9342187897 ps
CPU time	74.88 seconds
Started	Dec 24 01:19:20 PM PST 23
Finished	Dec 24 01:20:42 PM PST 23
Peak memory	225324 kb
Host	smart-3790ae30-2ed9-4b1f-a596-3a274792a4ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938088635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.2938088635 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all.2734962440
Short name	T600
Test name
Test status
Simulation time	394218561379 ps
CPU time	2740.64 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 02:05:21 PM PST 23
Peak memory	485336 kb
Host	smart-3d6bab1e-27b0-4954-b5b1-2e911c3e8ff6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2734962440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2734962440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.2256265360
Short name	T300
Test name
Test status
Simulation time	584823782 ps
CPU time	5.9 seconds
Started	Dec 24 01:19:18 PM PST 23
Finished	Dec 24 01:19:32 PM PST 23
Peak memory	220252 kb
Host	smart-8dd9f7bb-151a-45fe-b968-06ab960f9c92
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256265360 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.2256265360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.20979889
Short name	T443
Test name
Test status
Simulation time	406041961 ps
CPU time	5.94 seconds
Started	Dec 24 01:19:20 PM PST 23
Finished	Dec 24 01:19:33 PM PST 23
Peak memory	218780 kb
Host	smart-bf31e72a-d7c3-4171-9e15-47ccdab0c4ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979889 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.kmac_test_vectors_kmac_xof.20979889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.2751085434
Short name	T176
Test name
Test status
Simulation time	68164403495 ps
CPU time	2334.59 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:58:21 PM PST 23
Peak memory	396268 kb
Host	smart-34ab0edf-bd88-4e40-92fc-b6b621bef20b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2751085434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.2751085434 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.4207829545
Short name	T688
Test name
Test status
Simulation time	41084713452 ps
CPU time	1834.86 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:50:01 PM PST 23
Peak memory	400368 kb
Host	smart-d02b5bba-a4bb-4c5f-8550-b0f87058df69
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4207829545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.4207829545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.570978600
Short name	T904
Test name
Test status
Simulation time	16118367319 ps
CPU time	1503.36 seconds
Started	Dec 24 01:19:17 PM PST 23
Finished	Dec 24 01:44:29 PM PST 23
Peak memory	339076 kb
Host	smart-8d043e89-5ac2-4c6c-8fc9-751a676e3947
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=570978600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.570978600 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.3821146137
Short name	T861
Test name
Test status
Simulation time	21984983594 ps
CPU time	1214.73 seconds
Started	Dec 24 01:19:19 PM PST 23
Finished	Dec 24 01:39:41 PM PST 23
Peak memory	306300 kb
Host	smart-a72eb43b-5a80-472e-a299-20a0013560c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3821146137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3821146137 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.1722026190
Short name	T277
Test name
Test status
Simulation time	276357414870 ps
CPU time	5513.59 seconds
Started	Dec 24 01:19:21 PM PST 23
Finished	Dec 24 02:51:22 PM PST 23
Peak memory	664320 kb
Host	smart-53db6fc4-81b6-4400-8478-2df2d8fab80f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1722026190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.1722026190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.4287641369
Short name	T1013
Test name
Test status
Simulation time	213321491464 ps
CPU time	4310.61 seconds
Started	Dec 24 01:19:22 PM PST 23
Finished	Dec 24 02:31:19 PM PST 23
Peak memory	557496 kb
Host	smart-a507f48d-bb76-4d1e-b611-c875da563ebb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4287641369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.4287641369 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.123563622
Short name	T481
Test name
Test status
Simulation time	15918983 ps
CPU time	0.84 seconds
Started	Dec 24 01:19:47 PM PST 23
Finished	Dec 24 01:19:49 PM PST 23
Peak memory	219716 kb
Host	smart-1270db0f-e52c-4176-a41e-57713ed4d23a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123563622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.123563622 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.30871091
Short name	T371
Test name
Test status
Simulation time	6006827979 ps
CPU time	172.28 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:22:33 PM PST 23
Peak memory	241368 kb
Host	smart-e9a39b34-1281-4b3b-b66c-1ef8e9d40962
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30871091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.30871091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.948980644
Short name	T1135
Test name
Test status
Simulation time	15990738892 ps
CPU time	297.65 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:24:40 PM PST 23
Peak memory	232724 kb
Host	smart-bd4bc905-9833-4dc6-8633-c413efde410b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948980644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.948980644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.916595036
Short name	T718
Test name
Test status
Simulation time	16755881379 ps
CPU time	155.07 seconds
Started	Dec 24 01:19:37 PM PST 23
Finished	Dec 24 01:22:14 PM PST 23
Peak memory	243364 kb
Host	smart-cd6d432f-eb5f-4309-a273-692f7a419292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916595036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.916595036 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.2356669406
Short name	T568
Test name
Test status
Simulation time	110499933811 ps
CPU time	347.08 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:25:30 PM PST 23
Peak memory	259632 kb
Host	smart-60697f29-cc9f-4293-bc17-47cda7e8f5e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356669406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2356669406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.3014397841
Short name	T730
Test name
Test status
Simulation time	2983750850 ps
CPU time	5.37 seconds
Started	Dec 24 01:19:32 PM PST 23
Finished	Dec 24 01:19:39 PM PST 23
Peak memory	218820 kb
Host	smart-966308c2-a269-43f9-8e1e-1a8904bd72a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014397841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3014397841 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.716357062
Short name	T660
Test name
Test status
Simulation time	155569226 ps
CPU time	1.68 seconds
Started	Dec 24 01:19:37 PM PST 23
Finished	Dec 24 01:19:41 PM PST 23
Peak memory	220372 kb
Host	smart-faeec707-5ae3-4983-ab60-eaccc0073b1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716357062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.716357062 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.1001868207
Short name	T424
Test name
Test status
Simulation time	110431510492 ps
CPU time	3071.14 seconds
Started	Dec 24 01:19:36 PM PST 23
Finished	Dec 24 02:10:49 PM PST 23
Peak memory	485212 kb
Host	smart-20b20457-7682-4642-8617-af49cb7fba13
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001868207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.1001868207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.3146863077
Short name	T211
Test name
Test status
Simulation time	40334043609 ps
CPU time	331.68 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:25:12 PM PST 23
Peak memory	248900 kb
Host	smart-8cc1a2d2-38fa-46e3-bac3-ab70fbc85e7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146863077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3146863077 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.3150222082
Short name	T596
Test name
Test status
Simulation time	13190034176 ps
CPU time	67.63 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	219288 kb
Host	smart-c7810319-e914-443c-b572-6e6fa31fa22b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150222082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3150222082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.2080498061
Short name	T1129
Test name
Test status
Simulation time	4527432455 ps
CPU time	459.26 seconds
Started	Dec 24 01:19:34 PM PST 23
Finished	Dec 24 01:27:15 PM PST 23
Peak memory	284300 kb
Host	smart-a65075af-6a37-4e2f-8ea7-a0f6f318d08d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2080498061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2080498061 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.2241635494
Short name	T918
Test name
Test status
Simulation time	12309250859 ps
CPU time	992.48 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:36:16 PM PST 23
Peak memory	297652 kb
Host	smart-f931468c-9499-48a6-ab3e-a2f4e368beb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2241635494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.2241635494 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.1439571883
Short name	T871
Test name
Test status
Simulation time	261141814 ps
CPU time	6.52 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	220244 kb
Host	smart-9b8c1179-4dbd-4664-b9b8-15a9156334d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439571883 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.1439571883 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3142926953
Short name	T104
Test name
Test status
Simulation time	272230522 ps
CPU time	6.36 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:19:48 PM PST 23
Peak memory	220060 kb
Host	smart-28389d00-0d90-492b-8777-ebba57ac9939
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142926953 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3142926953 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.4218832160
Short name	T867
Test name
Test status
Simulation time	411931601311 ps
CPU time	2203.55 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:56:25 PM PST 23
Peak memory	400448 kb
Host	smart-dba3a07f-a242-42b1-afc7-46d6306d5a5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4218832160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.4218832160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.3394293039
Short name	T602
Test name
Test status
Simulation time	76245998445 ps
CPU time	1928.55 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:51:50 PM PST 23
Peak memory	386484 kb
Host	smart-b0ac2a86-bf8c-4229-87d6-25bcea891886
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3394293039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3394293039 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.3700595578
Short name	T663
Test name
Test status
Simulation time	241163969224 ps
CPU time	1691.3 seconds
Started	Dec 24 01:19:37 PM PST 23
Finished	Dec 24 01:47:50 PM PST 23
Peak memory	337580 kb
Host	smart-6486e9c6-bcda-40b0-ae10-fee0ece64831
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3700595578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3700595578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.1689213400
Short name	T517
Test name
Test status
Simulation time	369190341577 ps
CPU time	1285.26 seconds
Started	Dec 24 01:19:34 PM PST 23
Finished	Dec 24 01:41:00 PM PST 23
Peak memory	302584 kb
Host	smart-087ead08-75af-4c52-83d9-fcf6b3be1803
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1689213400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1689213400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.2736377227
Short name	T1073
Test name
Test status
Simulation time	432249680614 ps
CPU time	5943.72 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 02:58:46 PM PST 23
Peak memory	657004 kb
Host	smart-052a987f-fd9f-4d8a-8997-717607bfb3fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2736377227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2736377227 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.3292319759
Short name	T159
Test name
Test status
Simulation time	53193308505 ps
CPU time	4515.03 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 02:34:55 PM PST 23
Peak memory	575840 kb
Host	smart-998a221b-7238-4237-87a6-a2b27783447f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3292319759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3292319759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.1840770108
Short name	T374
Test name
Test status
Simulation time	17991429 ps
CPU time	0.82 seconds
Started	Dec 24 01:19:42 PM PST 23
Finished	Dec 24 01:19:45 PM PST 23
Peak memory	218588 kb
Host	smart-ce3fee4a-667c-4211-8d4c-04fdf09f06ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840770108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1840770108 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.1274206757
Short name	T1069
Test name
Test status
Simulation time	25213744445 ps
CPU time	388.84 seconds
Started	Dec 24 01:19:42 PM PST 23
Finished	Dec 24 01:26:13 PM PST 23
Peak memory	253528 kb
Host	smart-5c8fee9b-d0b0-4763-b267-b75b61378867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274206757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1274206757 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.3560390589
Short name	T661
Test name
Test status
Simulation time	20526677283 ps
CPU time	1003 seconds
Started	Dec 24 01:19:37 PM PST 23
Finished	Dec 24 01:36:22 PM PST 23
Peak memory	239764 kb
Host	smart-9f6064f8-154e-4161-9d5f-b2ad42b0c04a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560390589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3560390589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.3631441654
Short name	T897
Test name
Test status
Simulation time	502792864 ps
CPU time	24.9 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:20:07 PM PST 23
Peak memory	227360 kb
Host	smart-c3b09fb8-54fd-40a5-b203-dd30df4dbf41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631441654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3631441654 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.1388662659
Short name	T1141
Test name
Test status
Simulation time	35770107881 ps
CPU time	503.97 seconds
Started	Dec 24 01:19:48 PM PST 23
Finished	Dec 24 01:28:15 PM PST 23
Peak memory	269928 kb
Host	smart-026e8b66-7cd6-462c-b263-951fb2396bd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388662659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1388662659 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.2962952701
Short name	T727
Test name
Test status
Simulation time	1558825779 ps
CPU time	2.84 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:19:46 PM PST 23
Peak memory	218616 kb
Host	smart-71404f3e-f105-4392-8613-054c3df4c64f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962952701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2962952701 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.177968988
Short name	T605
Test name
Test status
Simulation time	42209520 ps
CPU time	1.43 seconds
Started	Dec 24 01:19:47 PM PST 23
Finished	Dec 24 01:19:50 PM PST 23
Peak memory	219832 kb
Host	smart-a12f1732-b20c-4e0d-acc2-e3ebaccc6575
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177968988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.177968988 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.2382286220
Short name	T1098
Test name
Test status
Simulation time	414246314162 ps
CPU time	2903.22 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 02:08:04 PM PST 23
Peak memory	431716 kb
Host	smart-8acd517e-d716-45b8-b8b3-116db8f7823c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382286220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.2382286220 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.1589647759
Short name	T997
Test name
Test status
Simulation time	4098358794 ps
CPU time	301.68 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:24:42 PM PST 23
Peak memory	248768 kb
Host	smart-f49faa84-ce24-4011-b619-17dc05b124b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589647759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1589647759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.1302278309
Short name	T668
Test name
Test status
Simulation time	3543485330 ps
CPU time	44.22 seconds
Started	Dec 24 01:19:33 PM PST 23
Finished	Dec 24 01:20:19 PM PST 23
Peak memory	224548 kb
Host	smart-a1617537-b4a1-4fec-a608-6e47f13eeb35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302278309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1302278309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all_with_rand_reset.321382954
Short name	T375
Test name
Test status
Simulation time	81753796849 ps
CPU time	1287.84 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 01:41:11 PM PST 23
Peak memory	299412 kb
Host	smart-4c90ab23-d76d-4a60-bae5-418bd864d710
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=321382954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.321382954 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.1293140673
Short name	T539
Test name
Test status
Simulation time	352743827 ps
CPU time	5.86 seconds
Started	Dec 24 01:19:37 PM PST 23
Finished	Dec 24 01:19:44 PM PST 23
Peak memory	218848 kb
Host	smart-b67410b1-81a2-4fd1-85e1-a7ccfc9aef7f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293140673 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.1293140673 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.4226227043
Short name	T916
Test name
Test status
Simulation time	263862427 ps
CPU time	6.47 seconds
Started	Dec 24 01:19:43 PM PST 23
Finished	Dec 24 01:19:52 PM PST 23
Peak memory	218908 kb
Host	smart-7c075f1a-41ce-4cd3-80aa-576b9643da10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226227043 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.4226227043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.3389570979
Short name	T408
Test name
Test status
Simulation time	86114701030 ps
CPU time	1986.4 seconds
Started	Dec 24 01:19:33 PM PST 23
Finished	Dec 24 01:52:41 PM PST 23
Peak memory	403888 kb
Host	smart-8370b4ef-55c4-4525-a4cd-13aa42228b32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3389570979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3389570979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.1843753468
Short name	T731
Test name
Test status
Simulation time	92397922528 ps
CPU time	2251.13 seconds
Started	Dec 24 01:19:38 PM PST 23
Finished	Dec 24 01:57:11 PM PST 23
Peak memory	388412 kb
Host	smart-829a3e76-8422-42b7-b37e-a242b427838f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1843753468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1843753468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.1531555309
Short name	T352
Test name
Test status
Simulation time	68979019371 ps
CPU time	1792.29 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 01:49:35 PM PST 23
Peak memory	347948 kb
Host	smart-3a8590fb-c623-402f-b949-560775d10f74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1531555309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1531555309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.3402195553
Short name	T969
Test name
Test status
Simulation time	51313195917 ps
CPU time	1358.83 seconds
Started	Dec 24 01:19:41 PM PST 23
Finished	Dec 24 01:42:23 PM PST 23
Peak memory	303292 kb
Host	smart-bff669fa-eeb8-4f30-97e8-8779e842d9e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3402195553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.3402195553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.1075590153
Short name	T965
Test name
Test status
Simulation time	261533294433 ps
CPU time	6002.29 seconds
Started	Dec 24 01:19:39 PM PST 23
Finished	Dec 24 02:59:44 PM PST 23
Peak memory	650024 kb
Host	smart-a5bd9512-648c-4a44-a7e2-c1d160d8dce1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1075590153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1075590153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.4199866600
Short name	T599
Test name
Test status
Simulation time	225008125700 ps
CPU time	5249.34 seconds
Started	Dec 24 01:19:34 PM PST 23
Finished	Dec 24 02:47:06 PM PST 23
Peak memory	566060 kb
Host	smart-c02abb62-322e-4256-b36c-f9dc61d87854
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4199866600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.4199866600 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.1649078308
Short name	T178
Test name
Test status
Simulation time	24345188 ps
CPU time	0.93 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	218460 kb
Host	smart-c9c031c9-9402-4892-9070-a3b6fccd502e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649078308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1649078308 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.611814401
Short name	T955
Test name
Test status
Simulation time	5110690427 ps
CPU time	155.96 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:22:30 PM PST 23
Peak memory	243236 kb
Host	smart-64f78b2c-10d8-470e-891f-06b863196422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611814401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.611814401 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.1008008010
Short name	T1113
Test name
Test status
Simulation time	11485828441 ps
CPU time	1177.41 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:39:34 PM PST 23
Peak memory	243468 kb
Host	smart-8c8f39e8-3c3d-4fed-9862-3d4ee6315d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008008010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1008008010 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.201609211
Short name	T810
Test name
Test status
Simulation time	5775880580 ps
CPU time	56.44 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	229580 kb
Host	smart-24ac9e28-0bfc-485d-a1da-0f8134f21d5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201609211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.201609211 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_error.768018416
Short name	T1081
Test name
Test status
Simulation time	21110155829 ps
CPU time	454.33 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:27:29 PM PST 23
Peak memory	268228 kb
Host	smart-6208a611-c445-4ba9-83d9-b470248944e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768018416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.768018416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.3946134864
Short name	T971
Test name
Test status
Simulation time	1198428033 ps
CPU time	6.76 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:20:01 PM PST 23
Peak memory	218552 kb
Host	smart-05b106ca-286a-42bc-9c1f-6dd9f74a5155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946134864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3946134864 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.4292728445
Short name	T620
Test name
Test status
Simulation time	53135198 ps
CPU time	1.39 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:19:57 PM PST 23
Peak memory	219924 kb
Host	smart-ae2a48d1-bc34-4069-aeb7-5c5e2961dc42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292728445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4292728445 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.4027921253
Short name	T402
Test name
Test status
Simulation time	262135504563 ps
CPU time	3519.73 seconds
Started	Dec 24 01:19:40 PM PST 23
Finished	Dec 24 02:18:23 PM PST 23
Peak memory	478232 kb
Host	smart-3ee984bc-2205-4c11-a6d6-ccd0cb251e5f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027921253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.4027921253 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.1748058506
Short name	T734
Test name
Test status
Simulation time	7375259236 ps
CPU time	235.06 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:23:48 PM PST 23
Peak memory	243652 kb
Host	smart-9d0f4941-eac7-4d5e-9089-ac058f622d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748058506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1748058506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.944055334
Short name	T475
Test name
Test status
Simulation time	3950545614 ps
CPU time	78.61 seconds
Started	Dec 24 01:19:41 PM PST 23
Finished	Dec 24 01:21:03 PM PST 23
Peak memory	227036 kb
Host	smart-12e2a760-bc63-4d72-b269-fdf2a4e920e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944055334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.944055334 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.3038272841
Short name	T17
Test name
Test status
Simulation time	13590340061 ps
CPU time	308.89 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:25:02 PM PST 23
Peak memory	284576 kb
Host	smart-01b470ee-6de6-441d-9210-d77d9a6dc724
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3038272841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3038272841 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.2542611842
Short name	T6
Test name
Test status
Simulation time	289848499 ps
CPU time	5.55 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:19:59 PM PST 23
Peak memory	220460 kb
Host	smart-4cf1a785-9a69-4bb9-bd29-bcbb1c3a49b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542611842 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.2542611842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3607680913
Short name	T784
Test name
Test status
Simulation time	2874233476 ps
CPU time	7.41 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	220280 kb
Host	smart-3ba33a98-9508-439e-9119-75ff84a7429d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607680913 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3607680913 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.2834248327
Short name	T310
Test name
Test status
Simulation time	21004521189 ps
CPU time	2029.14 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:53:44 PM PST 23
Peak memory	391888 kb
Host	smart-72a76183-43e9-426c-94f9-8b1c22acdb99
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2834248327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2834248327 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.561014698
Short name	T617
Test name
Test status
Simulation time	19974078459 ps
CPU time	1931.82 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:52:11 PM PST 23
Peak memory	386172 kb
Host	smart-98e277c6-f1d9-4202-bab6-9a2d4788b017
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=561014698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.561014698 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.3755851317
Short name	T990
Test name
Test status
Simulation time	32425252051 ps
CPU time	1586.77 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:46:20 PM PST 23
Peak memory	342660 kb
Host	smart-970aadf5-8388-4079-a7f5-a1be14f76808
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3755851317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3755851317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.3892466191
Short name	T809
Test name
Test status
Simulation time	201609925750 ps
CPU time	1259.62 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:40:56 PM PST 23
Peak memory	296596 kb
Host	smart-0ebf9964-8001-478b-bd93-fe88e02be964
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3892466191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3892466191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.3807765279
Short name	T1101
Test name
Test status
Simulation time	1073582788183 ps
CPU time	6386.54 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 03:06:26 PM PST 23
Peak memory	655008 kb
Host	smart-6c299bda-8152-4b12-a1e0-90fb13df5724
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3807765279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3807765279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.1618535419
Short name	T201
Test name
Test status
Simulation time	274327710781 ps
CPU time	4544.23 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 02:35:42 PM PST 23
Peak memory	564148 kb
Host	smart-0fe55f91-8264-488b-b7ee-bb0527d5fc07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1618535419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1618535419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.3977175259
Short name	T760
Test name
Test status
Simulation time	138839163 ps
CPU time	0.89 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:19:57 PM PST 23
Peak memory	218488 kb
Host	smart-081370a6-ea2b-4088-ad45-141cd503610c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977175259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3977175259 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.388168398
Short name	T939
Test name
Test status
Simulation time	16288931703 ps
CPU time	244.45 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:23:57 PM PST 23
Peak memory	247916 kb
Host	smart-7e3d5465-36c5-4635-a0cc-ab568d1f457e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=388168398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.388168398 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.2180465176
Short name	T1059
Test name
Test status
Simulation time	117914830976 ps
CPU time	1463.66 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:44:17 PM PST 23
Peak memory	243328 kb
Host	smart-784ef672-b45e-481e-8c3c-fb6925b3a9b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180465176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2180465176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.2469207187
Short name	T71
Test name
Test status
Simulation time	11455645310 ps
CPU time	47.14 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:20:45 PM PST 23
Peak memory	229424 kb
Host	smart-2ae292e0-46d0-4eea-94b0-52c0ec7b002d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469207187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2469207187 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.3285870552
Short name	T469
Test name
Test status
Simulation time	32896493908 ps
CPU time	240.3 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:23:57 PM PST 23
Peak memory	251892 kb
Host	smart-01ea04ba-660f-4a37-aa43-90d2b13cfbdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285870552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3285870552 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.1115021471
Short name	T407
Test name
Test status
Simulation time	239170595 ps
CPU time	1.06 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:20:00 PM PST 23
Peak memory	218576 kb
Host	smart-bdf48a15-6dc6-4954-a434-62fa395ec8f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115021471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1115021471 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.882272112
Short name	T591
Test name
Test status
Simulation time	169267128 ps
CPU time	1.37 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:19:54 PM PST 23
Peak memory	219724 kb
Host	smart-f06f04a7-6ab0-4078-ae13-396ceda0c9d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882272112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.882272112 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.2982330524
Short name	T197
Test name
Test status
Simulation time	62417920948 ps
CPU time	1759.12 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:49:16 PM PST 23
Peak memory	361848 kb
Host	smart-99bf1da1-6f06-49cc-830b-aebca90a4703
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982330524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.2982330524 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.2191811710
Short name	T993
Test name
Test status
Simulation time	23930540527 ps
CPU time	312.96 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:25:06 PM PST 23
Peak memory	250148 kb
Host	smart-3babfc5f-660c-401f-94aa-482c4f28560b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191811710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2191811710 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.2494807511
Short name	T566
Test name
Test status
Simulation time	1766190882 ps
CPU time	31.95 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:20:31 PM PST 23
Peak memory	226868 kb
Host	smart-7f250112-ce37-4bc0-85ff-2ef95311ea0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494807511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2494807511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.924650875
Short name	T577
Test name
Test status
Simulation time	14578928992 ps
CPU time	1044.78 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:37:20 PM PST 23
Peak memory	341884 kb
Host	smart-58cc3de3-4bf6-41ea-9f58-876366d95ba9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=924650875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.924650875 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.1568993726
Short name	T863
Test name
Test status
Simulation time	47465757992 ps
CPU time	1303.22 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:41:41 PM PST 23
Peak memory	350212 kb
Host	smart-c6147907-e2d2-4333-b44f-cdcf7f1c75b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1568993726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.1568993726 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.3790948204
Short name	T775
Test name
Test status
Simulation time	293731034 ps
CPU time	6.12 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:19:59 PM PST 23
Peak memory	220516 kb
Host	smart-32379c2b-cd2f-41ed-bc24-5a11ce685ba4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790948204 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.3790948204 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2795160116
Short name	T1127
Test name
Test status
Simulation time	441431339 ps
CPU time	6.09 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	218860 kb
Host	smart-743f8208-813a-4163-95cd-b49bf08887bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795160116 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2795160116 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.4006679578
Short name	T383
Test name
Test status
Simulation time	44100683710 ps
CPU time	1988.4 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:53:07 PM PST 23
Peak memory	399200 kb
Host	smart-702e271e-6963-401c-87ad-e5add81f0952
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4006679578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.4006679578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.3094463729
Short name	T266
Test name
Test status
Simulation time	19910339397 ps
CPU time	2099.26 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:54:59 PM PST 23
Peak memory	387376 kb
Host	smart-17bb9e2d-9c10-45f9-bf03-2479c6fa7986
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3094463729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3094463729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.3649103927
Short name	T1008
Test name
Test status
Simulation time	50706358141 ps
CPU time	1552.37 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:45:47 PM PST 23
Peak memory	340300 kb
Host	smart-0f4e66b7-fa73-4bac-ac2d-d9ce7571efc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3649103927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3649103927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.754381294
Short name	T979
Test name
Test status
Simulation time	190113490943 ps
CPU time	1344.8 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:42:22 PM PST 23
Peak memory	298172 kb
Host	smart-577db97f-638a-4381-8944-e4c976333f37
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=754381294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.754381294 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.2766210782
Short name	T935
Test name
Test status
Simulation time	1376241328822 ps
CPU time	5952.18 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 02:59:09 PM PST 23
Peak memory	666664 kb
Host	smart-303e724e-2334-4c13-a3be-595457585393
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2766210782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2766210782 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.2820603209
Short name	T189
Test name
Test status
Simulation time	757881834080 ps
CPU time	4685.58 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 02:38:05 PM PST 23
Peak memory	563028 kb
Host	smart-b63cef27-3936-4f73-a4b7-ff978aa29a94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2820603209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2820603209 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.456988701
Short name	T477
Test name
Test status
Simulation time	62136113 ps
CPU time	0.89 seconds
Started	Dec 24 01:18:32 PM PST 23
Finished	Dec 24 01:18:51 PM PST 23
Peak memory	218524 kb
Host	smart-19b9760a-ae46-4cb7-ba24-aa287642e98a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456988701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.456988701 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.3990011312
Short name	T685
Test name
Test status
Simulation time	16930451113 ps
CPU time	215.51 seconds
Started	Dec 24 01:18:09 PM PST 23
Finished	Dec 24 01:21:46 PM PST 23
Peak memory	243416 kb
Host	smart-8ee1176b-54c7-4a40-9fe0-d47ac396a602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990011312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3990011312 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.1675062109
Short name	T400
Test name
Test status
Simulation time	13093774741 ps
CPU time	44.98 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:56 PM PST 23
Peak memory	229604 kb
Host	smart-d74153c8-8baf-41ff-9eae-6b3b969d935e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675062109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1675062109 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.4239680671
Short name	T847
Test name
Test status
Simulation time	6132331887 ps
CPU time	60.53 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:20:08 PM PST 23
Peak memory	240096 kb
Host	smart-43fffcca-a70f-4669-ac2a-ce26b17c1320
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239680671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4239680671 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.154147505
Short name	T75
Test name
Test status
Simulation time	55175554 ps
CPU time	0.79 seconds
Started	Dec 24 01:18:08 PM PST 23
Finished	Dec 24 01:18:10 PM PST 23
Peak memory	218464 kb
Host	smart-f8adde5a-56ab-485f-b958-01d9df5a1920
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=154147505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.154147505 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.3658113600
Short name	T337
Test name
Test status
Simulation time	2480256462 ps
CPU time	8.2 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:18:57 PM PST 23
Peak memory	226472 kb
Host	smart-a2306a73-1672-40fa-aa22-43eb7361d23f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3658113600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3658113600 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.3148508207
Short name	T872
Test name
Test status
Simulation time	12340190436 ps
CPU time	34.17 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:47 PM PST 23
Peak memory	219792 kb
Host	smart-4bdc3599-7bb9-4ea6-8ce0-0a38e3417ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148508207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3148508207 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.3445273712
Short name	T262
Test name
Test status
Simulation time	11731784462 ps
CPU time	289.49 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:22:48 PM PST 23
Peak memory	249428 kb
Host	smart-7760ccca-d031-4012-9931-bc329edf817f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445273712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3445273712 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.703524414
Short name	T138
Test name
Test status
Simulation time	64684263822 ps
CPU time	262.27 seconds
Started	Dec 24 01:18:26 PM PST 23
Finished	Dec 24 01:23:07 PM PST 23
Peak memory	259796 kb
Host	smart-b49fece0-a330-4dd5-a7d7-7cfc38548924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703524414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.703524414 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.1834665228
Short name	T542
Test name
Test status
Simulation time	328898002 ps
CPU time	2.5 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:16 PM PST 23
Peak memory	218660 kb
Host	smart-98370c7e-93b3-43a5-9039-df22062b7c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834665228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1834665228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.4149286871
Short name	T876
Test name
Test status
Simulation time	73696455 ps
CPU time	1.37 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:18:44 PM PST 23
Peak memory	219908 kb
Host	smart-5e13faa2-d75a-49e3-a669-5eead4beefdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149286871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4149286871 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.3076163919
Short name	T931
Test name
Test status
Simulation time	73886787800 ps
CPU time	2691.39 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 02:03:55 PM PST 23
Peak memory	432204 kb
Host	smart-f6d90a45-71a3-434d-b79d-74708448d397
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076163919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.3076163919 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.2737417703
Short name	T648
Test name
Test status
Simulation time	51550017023 ps
CPU time	405.33 seconds
Started	Dec 24 01:17:53 PM PST 23
Finished	Dec 24 01:24:44 PM PST 23
Peak memory	254284 kb
Host	smart-481942c2-19ef-41c6-a715-831430cdb0fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737417703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2737417703 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.3843903453
Short name	T7
Test name
Test status
Simulation time	6287803380 ps
CPU time	77.51 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:20:01 PM PST 23
Peak memory	273684 kb
Host	smart-fdf739ab-cf39-4499-9700-a15e072d25a8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843903453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3843903453 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.119429127
Short name	T1143
Test name
Test status
Simulation time	500920411 ps
CPU time	16.69 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:24 PM PST 23
Peak memory	226088 kb
Host	smart-69a286a2-46f3-405c-a7ea-af3677d2e128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119429127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.119429127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.3848796982
Short name	T880
Test name
Test status
Simulation time	49348516228 ps
CPU time	96.05 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:20:37 PM PST 23
Peak memory	226908 kb
Host	smart-93bcf3e2-a008-494e-8a81-6fa5809a51e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848796982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3848796982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.549206518
Short name	T768
Test name
Test status
Simulation time	9231552871 ps
CPU time	769.52 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 01:31:33 PM PST 23
Peak memory	319412 kb
Host	smart-d15ce47c-9562-4dbe-a9ea-e0fb78ad1515
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=549206518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.549206518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3624776218
Short name	T593
Test name
Test status
Simulation time	150501975075 ps
CPU time	1052.11 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:36:15 PM PST 23
Peak memory	285152 kb
Host	smart-6da0ce88-c264-47e3-8708-fcb67ddeb61e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3624776218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3624776218 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.278361772
Short name	T175
Test name
Test status
Simulation time	554352782 ps
CPU time	7.01 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	220376 kb
Host	smart-9671f493-bc41-40a6-b334-bbb9f0d643e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278361772 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 3.kmac_test_vectors_kmac.278361772 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.541497684
Short name	T411
Test name
Test status
Simulation time	645299759 ps
CPU time	5.86 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:20 PM PST 23
Peak memory	220076 kb
Host	smart-e1e40e9a-23a0-46a6-83b7-202a8b0c57cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541497684 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.kmac_test_vectors_kmac_xof.541497684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.593594811
Short name	T239
Test name
Test status
Simulation time	261616416153 ps
CPU time	2186.78 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:55:27 PM PST 23
Peak memory	399544 kb
Host	smart-7890da00-1197-485c-8bde-52921ca7a91e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=593594811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.593594811 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.3177271137
Short name	T356
Test name
Test status
Simulation time	20458389523 ps
CPU time	1916.83 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:51:01 PM PST 23
Peak memory	387744 kb
Host	smart-be710074-e40b-4515-8dc0-1bf8ec47bf3b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3177271137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3177271137 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.3465893042
Short name	T305
Test name
Test status
Simulation time	333054982946 ps
CPU time	1879.07 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:50:30 PM PST 23
Peak memory	340096 kb
Host	smart-a0ef5ddc-6ee4-457c-a16d-37263ae9c346
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3465893042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3465893042 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.364079587
Short name	T677
Test name
Test status
Simulation time	41531599722 ps
CPU time	1135.17 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:38:08 PM PST 23
Peak memory	301072 kb
Host	smart-bb56bc6b-46d3-4bea-96f0-d5df227aae2c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=364079587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.364079587 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.634279815
Short name	T179
Test name
Test status
Simulation time	178270303030 ps
CPU time	5615.45 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 02:52:39 PM PST 23
Peak memory	655860 kb
Host	smart-4d201500-6ca6-4be4-ab5d-53d0efaf629a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=634279815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.634279815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.2418232852
Short name	T22
Test name
Test status
Simulation time	152734323474 ps
CPU time	4960 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 02:41:54 PM PST 23
Peak memory	573172 kb
Host	smart-eed62a5c-474f-4f0f-8dde-cbe2813b63e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2418232852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2418232852 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.739470444
Short name	T427
Test name
Test status
Simulation time	24649780 ps
CPU time	0.84 seconds
Started	Dec 24 01:20:09 PM PST 23
Finished	Dec 24 01:20:13 PM PST 23
Peak memory	219632 kb
Host	smart-2d781ff4-7605-40f5-ae1e-b6ed165b77fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739470444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.739470444 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.3141696002
Short name	T206
Test name
Test status
Simulation time	48634094268 ps
CPU time	222.19 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:23:36 PM PST 23
Peak memory	243996 kb
Host	smart-072d84c8-cf28-48b1-95b2-6a53baedbe22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141696002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3141696002 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.750776404
Short name	T456
Test name
Test status
Simulation time	36811136582 ps
CPU time	1029.98 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:37:02 PM PST 23
Peak memory	237916 kb
Host	smart-126dc86b-d403-471f-91ac-4b34aa697644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750776404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.750776404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.30837360
Short name	T139
Test name
Test status
Simulation time	10554065992 ps
CPU time	232.55 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:23:46 PM PST 23
Peak memory	246348 kb
Host	smart-92822859-16e1-414c-bb6d-bbe090924ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30837360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.30837360 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.3694007083
Short name	T1040
Test name
Test status
Simulation time	5117449873 ps
CPU time	79.55 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	243156 kb
Host	smart-8d1fcb66-f50a-49a1-a1d6-6b5f8510ebd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694007083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3694007083 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.778172633
Short name	T606
Test name
Test status
Simulation time	2317744332 ps
CPU time	3.72 seconds
Started	Dec 24 01:19:48 PM PST 23
Finished	Dec 24 01:19:55 PM PST 23
Peak memory	218728 kb
Host	smart-f6f22efe-19e1-403f-8d6f-c617a2cca9bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778172633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.778172633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.2772922986
Short name	T998
Test name
Test status
Simulation time	46730875 ps
CPU time	1.26 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:19:57 PM PST 23
Peak memory	219988 kb
Host	smart-b10c5509-7f52-48e5-ae75-49f29e621664
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772922986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2772922986 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.178019862
Short name	T228
Test name
Test status
Simulation time	123871563481 ps
CPU time	1036.14 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:37:10 PM PST 23
Peak memory	306308 kb
Host	smart-993c05ea-2006-4e04-be3c-892db5803a2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178019862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an d_output.178019862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.1669316608
Short name	T429
Test name
Test status
Simulation time	8914158597 ps
CPU time	141.2 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:22:16 PM PST 23
Peak memory	236452 kb
Host	smart-4b9f0315-7cf9-44f5-bf48-203a09caed60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669316608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1669316608 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.161767118
Short name	T779
Test name
Test status
Simulation time	8594895841 ps
CPU time	42.84 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:20:36 PM PST 23
Peak memory	226844 kb
Host	smart-06d3eadd-ef7a-47a6-9fab-580d8228cf48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161767118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.161767118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.3262299879
Short name	T224
Test name
Test status
Simulation time	1839170055 ps
CPU time	116.25 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:21:55 PM PST 23
Peak memory	243400 kb
Host	smart-38a23a3b-53e5-44c0-ad8a-23e6534277e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3262299879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3262299879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.500528407
Short name	T210
Test name
Test status
Simulation time	1213662721 ps
CPU time	6.65 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:20:03 PM PST 23
Peak memory	220172 kb
Host	smart-cce8b45d-d995-45c3-97d1-f0d3b3ec90a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500528407 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.kmac_test_vectors_kmac.500528407 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3996209375
Short name	T462
Test name
Test status
Simulation time	215167788 ps
CPU time	6.26 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:19:59 PM PST 23
Peak memory	220228 kb
Host	smart-d723ce6e-5415-4110-9c6b-1578aa5785e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996209375 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3996209375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.684587597
Short name	T230
Test name
Test status
Simulation time	44181668727 ps
CPU time	1996.25 seconds
Started	Dec 24 01:19:51 PM PST 23
Finished	Dec 24 01:53:10 PM PST 23
Peak memory	399692 kb
Host	smart-c16d8ef8-1e9e-4505-acc4-142c9e38d736
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=684587597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.684587597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.2683686472
Short name	T830
Test name
Test status
Simulation time	19182634920 ps
CPU time	2082.91 seconds
Started	Dec 24 01:19:50 PM PST 23
Finished	Dec 24 01:54:35 PM PST 23
Peak memory	382876 kb
Host	smart-bcc0d955-6e82-404b-85ea-5031057bb91d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2683686472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2683686472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.3605798774
Short name	T489
Test name
Test status
Simulation time	15548497208 ps
CPU time	1595.63 seconds
Started	Dec 24 01:19:52 PM PST 23
Finished	Dec 24 01:46:31 PM PST 23
Peak memory	343884 kb
Host	smart-39f01228-ddd9-49d9-a7c6-4c6e78ed45a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3605798774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3605798774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.900927265
Short name	T313
Test name
Test status
Simulation time	21488553178 ps
CPU time	1118.72 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:38:37 PM PST 23
Peak memory	299636 kb
Host	smart-9fa22dcd-f476-4757-b234-f6319e00db14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=900927265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.900927265 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.2741924305
Short name	T508
Test name
Test status
Simulation time	928927664858 ps
CPU time	5882.06 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 02:58:00 PM PST 23
Peak memory	644144 kb
Host	smart-6d0004cb-eb82-4dd6-b7c9-84b53508cd64
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2741924305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2741924305 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.1029786244
Short name	T207
Test name
Test status
Simulation time	133466905082 ps
CPU time	4601.84 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 02:36:43 PM PST 23
Peak memory	573816 kb
Host	smart-2d30e755-8348-4d51-865d-2639ba9b7ddb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1029786244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1029786244 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.4146914428
Short name	T899
Test name
Test status
Simulation time	28235798 ps
CPU time	0.84 seconds
Started	Dec 24 01:20:09 PM PST 23
Finished	Dec 24 01:20:13 PM PST 23
Peak memory	218496 kb
Host	smart-ff9a0a5e-14c6-47b3-bc1e-34a6eac8829a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146914428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4146914428 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.3678686696
Short name	T763
Test name
Test status
Simulation time	520753750 ps
CPU time	37.98 seconds
Started	Dec 24 01:19:57 PM PST 23
Finished	Dec 24 01:20:40 PM PST 23
Peak memory	235964 kb
Host	smart-32b402c1-2863-4004-a243-4755cbf03ba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678686696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3678686696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.2134899416
Short name	T367
Test name
Test status
Simulation time	26258912123 ps
CPU time	890.4 seconds
Started	Dec 24 01:19:59 PM PST 23
Finished	Dec 24 01:34:55 PM PST 23
Peak memory	243316 kb
Host	smart-dacdbe74-6b2f-49bb-a989-cf7cfc26082a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134899416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2134899416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_error.3605146815
Short name	T866
Test name
Test status
Simulation time	4634077866 ps
CPU time	361.52 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:26:13 PM PST 23
Peak memory	259536 kb
Host	smart-ba448ca5-2146-4678-ac8a-f2feb8999ba5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605146815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3605146815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.209232399
Short name	T309
Test name
Test status
Simulation time	804395672 ps
CPU time	2.73 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	218632 kb
Host	smart-c334a934-d051-49d2-a062-286459eca9be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209232399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.209232399 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.576417137
Short name	T705
Test name
Test status
Simulation time	67562503 ps
CPU time	1.45 seconds
Started	Dec 24 01:19:57 PM PST 23
Finished	Dec 24 01:20:04 PM PST 23
Peak memory	219920 kb
Host	smart-6f7016cc-fd98-475a-9aa1-1ea296d2b397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576417137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.576417137 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.3226630723
Short name	T275
Test name
Test status
Simulation time	86650278883 ps
CPU time	900.44 seconds
Started	Dec 24 01:19:57 PM PST 23
Finished	Dec 24 01:35:03 PM PST 23
Peak memory	288660 kb
Host	smart-d20168cc-a6f7-42fc-acc9-c30653b74a03
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226630723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.3226630723 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.4024868334
Short name	T729
Test name
Test status
Simulation time	1584324136 ps
CPU time	20.23 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:20:18 PM PST 23
Peak memory	227436 kb
Host	smart-e7c3b475-5fbe-4449-9f14-88010657a9f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024868334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4024868334 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.3458876949
Short name	T281
Test name
Test status
Simulation time	877967947 ps
CPU time	28.69 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:20:34 PM PST 23
Peak memory	226880 kb
Host	smart-78886550-a3df-4dba-81ec-72ba0e1aa63d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458876949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3458876949 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.1870907758
Short name	T799
Test name
Test status
Simulation time	9454284918 ps
CPU time	135.3 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:22:15 PM PST 23
Peak memory	256368 kb
Host	smart-7c705de6-e105-4d98-b58c-054f647d05ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1870907758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1870907758 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_stress_all_with_rand_reset.3902969726
Short name	T1124
Test name
Test status
Simulation time	979809225726 ps
CPU time	1048.13 seconds
Started	Dec 24 01:20:09 PM PST 23
Finished	Dec 24 01:37:40 PM PST 23
Peak memory	292488 kb
Host	smart-88dc9ce3-835f-43d5-9c1c-9ca7131a9a2a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3902969726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all_with_rand_reset.3902969726 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.2810528942
Short name	T544
Test name
Test status
Simulation time	499619710 ps
CPU time	6.16 seconds
Started	Dec 24 01:19:53 PM PST 23
Finished	Dec 24 01:20:04 PM PST 23
Peak memory	220216 kb
Host	smart-e398e074-c211-4ddd-9133-b5e6a3ebce70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810528942 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.2810528942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2987408966
Short name	T953
Test name
Test status
Simulation time	234947618 ps
CPU time	6.2 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:20:17 PM PST 23
Peak memory	218696 kb
Host	smart-3e56cfeb-aa5e-4952-8fe6-57191540f9aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987408966 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2987408966 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.467477208
Short name	T355
Test name
Test status
Simulation time	459845214089 ps
CPU time	2344.95 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:59:06 PM PST 23
Peak memory	392744 kb
Host	smart-0ac1b8be-475b-46cf-8971-966ac6191dcf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=467477208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.467477208 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.1873311384
Short name	T493
Test name
Test status
Simulation time	223610510620 ps
CPU time	2427.63 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 02:00:28 PM PST 23
Peak memory	387400 kb
Host	smart-8f840900-1bdb-4e80-b471-5bf42ccca19b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1873311384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.1873311384 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.1741569014
Short name	T336
Test name
Test status
Simulation time	73713338141 ps
CPU time	1827.21 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:50:26 PM PST 23
Peak memory	343536 kb
Host	smart-52483249-18e2-45e6-99e9-80c69eb56296
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1741569014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.1741569014 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.1759736835
Short name	T327
Test name
Test status
Simulation time	70592344560 ps
CPU time	1257.35 seconds
Started	Dec 24 01:19:54 PM PST 23
Finished	Dec 24 01:40:56 PM PST 23
Peak memory	301096 kb
Host	smart-9b9a9c7d-67c1-4e23-b502-f00c87a08403
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1759736835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1759736835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.2242433723
Short name	T709
Test name
Test status
Simulation time	194160101898 ps
CPU time	5556.09 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 02:52:36 PM PST 23
Peak memory	650060 kb
Host	smart-16bd865c-cc61-4bab-9649-50c9fd7356c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2242433723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2242433723 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.286154213
Short name	T930
Test name
Test status
Simulation time	73727771498 ps
CPU time	4364.14 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 02:32:45 PM PST 23
Peak memory	572284 kb
Host	smart-c34df737-85ba-4776-8da5-5c5592aebb1e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=286154213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.286154213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.3547048895
Short name	T724
Test name
Test status
Simulation time	44029937 ps
CPU time	0.84 seconds
Started	Dec 24 01:19:59 PM PST 23
Finished	Dec 24 01:20:05 PM PST 23
Peak memory	218568 kb
Host	smart-c5d760aa-d1a2-486c-acc8-f0d5fc7c0e66
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547048895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3547048895 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.1764791952
Short name	T988
Test name
Test status
Simulation time	5130233640 ps
CPU time	119.48 seconds
Started	Dec 24 01:20:09 PM PST 23
Finished	Dec 24 01:22:12 PM PST 23
Peak memory	243172 kb
Host	smart-916ee896-bdac-4e76-aca1-d98e014068b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764791952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1764791952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.2704994284
Short name	T514
Test name
Test status
Simulation time	57496487044 ps
CPU time	676.89 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:31:17 PM PST 23
Peak memory	236064 kb
Host	smart-d155837d-1415-463d-84b1-828bb102a66b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704994284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2704994284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.2908704650
Short name	T401
Test name
Test status
Simulation time	25040917883 ps
CPU time	260.61 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 01:24:31 PM PST 23
Peak memory	245696 kb
Host	smart-95aebbfb-f1fb-4d06-820f-39c28ee81a98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908704650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2908704650 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.4096365356
Short name	T803
Test name
Test status
Simulation time	53819012382 ps
CPU time	450.95 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 01:27:42 PM PST 23
Peak memory	265344 kb
Host	smart-9b5d38fb-5032-4e8a-867a-4fdf5fd19a74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096365356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.4096365356 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_key_error.3588583868
Short name	T522
Test name
Test status
Simulation time	650960634 ps
CPU time	4.62 seconds
Started	Dec 24 01:20:09 PM PST 23
Finished	Dec 24 01:20:17 PM PST 23
Peak memory	218548 kb
Host	smart-fd501c7a-3bff-4dc6-8e4d-ab05acfec98a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588583868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3588583868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.1735277922
Short name	T853
Test name
Test status
Simulation time	99346567 ps
CPU time	1.44 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:20:13 PM PST 23
Peak memory	219940 kb
Host	smart-98680d76-f5a8-4894-9dd2-b103fdb5cfb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735277922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1735277922 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.4088901118
Short name	T742
Test name
Test status
Simulation time	248705958797 ps
CPU time	2422.09 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 02:00:26 PM PST 23
Peak memory	420280 kb
Host	smart-7faf7571-c625-440f-a45f-f51411416aef
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088901118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.4088901118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.1268732100
Short name	T822
Test name
Test status
Simulation time	20030953862 ps
CPU time	165.37 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:22:45 PM PST 23
Peak memory	239364 kb
Host	smart-2b262e13-2eac-47e4-b636-09db544b3c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268732100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1268732100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.3878639091
Short name	T501
Test name
Test status
Simulation time	13162270068 ps
CPU time	68.31 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 01:21:11 PM PST 23
Peak memory	224316 kb
Host	smart-237d3297-51da-4e66-b98a-f6ea481d85a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878639091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3878639091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.3409795642
Short name	T972
Test name
Test status
Simulation time	76090054235 ps
CPU time	1872.03 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 01:51:16 PM PST 23
Peak memory	398080 kb
Host	smart-38a6a1a5-214c-42c5-8ce5-d7076dbdcaee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3409795642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3409795642 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_stress_all_with_rand_reset.1504159488
Short name	T14
Test name
Test status
Simulation time	75060952014 ps
CPU time	1599.52 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:46:52 PM PST 23
Peak memory	321284 kb
Host	smart-85e9f46a-0acb-4ec3-b686-0a48b6e79a63
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1504159488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all_with_rand_reset.1504159488 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.2565644071
Short name	T919
Test name
Test status
Simulation time	403765802 ps
CPU time	6.23 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:20:12 PM PST 23
Peak memory	218816 kb
Host	smart-26057140-a5f1-4dba-ab40-f75ac118241b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565644071 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.kmac_test_vectors_kmac.2565644071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.662747728
Short name	T1055
Test name
Test status
Simulation time	205648445 ps
CPU time	6.51 seconds
Started	Dec 24 01:20:10 PM PST 23
Finished	Dec 24 01:20:19 PM PST 23
Peak memory	220104 kb
Host	smart-9453514b-88fc-4f64-a76a-587b676a6ed4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662747728 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 32.kmac_test_vectors_kmac_xof.662747728 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.2945223027
Short name	T273
Test name
Test status
Simulation time	33282827083 ps
CPU time	2134.27 seconds
Started	Dec 24 01:19:59 PM PST 23
Finished	Dec 24 01:55:39 PM PST 23
Peak memory	399432 kb
Host	smart-a73317d4-bb04-466c-b4d5-f7e1a5d01861
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2945223027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.2945223027 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.1243334790
Short name	T756
Test name
Test status
Simulation time	64273667629 ps
CPU time	2296.28 seconds
Started	Dec 24 01:19:57 PM PST 23
Finished	Dec 24 01:58:19 PM PST 23
Peak memory	391248 kb
Host	smart-5c061b83-66f9-4406-91fa-3ba0ad3a7035
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1243334790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1243334790 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.371092666
Short name	T452
Test name
Test status
Simulation time	413138114304 ps
CPU time	1839.21 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:50:51 PM PST 23
Peak memory	341520 kb
Host	smart-628b965b-7072-4415-8985-90a5faa841ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=371092666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.371092666 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.3797547572
Short name	T213
Test name
Test status
Simulation time	166422737830 ps
CPU time	1251.53 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:40:52 PM PST 23
Peak memory	303896 kb
Host	smart-ad534aaf-ad2c-4898-94b6-88f14a15f036
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3797547572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3797547572 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.1612511112
Short name	T187
Test name
Test status
Simulation time	63525606946 ps
CPU time	5024.88 seconds
Started	Dec 24 01:19:59 PM PST 23
Finished	Dec 24 02:43:50 PM PST 23
Peak memory	650600 kb
Host	smart-403941a6-135f-4c23-975d-3dd55246e363
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1612511112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.1612511112 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.3102321224
Short name	T903
Test name
Test status
Simulation time	661713489978 ps
CPU time	4966.55 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 02:42:51 PM PST 23
Peak memory	575372 kb
Host	smart-9d15a891-cb00-4a68-8dac-ea0178c1fa6e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3102321224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3102321224 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.928170835
Short name	T438
Test name
Test status
Simulation time	48504550 ps
CPU time	0.86 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 01:20:04 PM PST 23
Peak memory	218644 kb
Host	smart-fe047bd8-9506-485d-8a2c-2f009b85bc3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928170835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.928170835 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.474364119
Short name	T855
Test name
Test status
Simulation time	7435661021 ps
CPU time	192.07 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:23:13 PM PST 23
Peak memory	242876 kb
Host	smart-47682d20-356b-487b-a022-e8da28802d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474364119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.474364119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.2809996406
Short name	T491
Test name
Test status
Simulation time	28499023138 ps
CPU time	1323.97 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 01:42:15 PM PST 23
Peak memory	243280 kb
Host	smart-aba262c2-0bd0-4873-a66a-76831ba42fcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809996406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2809996406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.1824214085
Short name	T26
Test name
Test status
Simulation time	1144477886 ps
CPU time	30.21 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:20:30 PM PST 23
Peak memory	225464 kb
Host	smart-a27c0729-ee3c-459e-b2c3-89cc0cf5742b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824214085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1824214085 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.4011818461
Short name	T1104
Test name
Test status
Simulation time	5764878844 ps
CPU time	206.92 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:23:32 PM PST 23
Peak memory	251564 kb
Host	smart-fbfe320c-838f-40e8-a1f2-3e2ab6704bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011818461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.4011818461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.3047601213
Short name	T662
Test name
Test status
Simulation time	977438199 ps
CPU time	3.65 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:20:09 PM PST 23
Peak memory	218680 kb
Host	smart-6995ed56-e9a1-4aab-b84a-31c36308a9fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047601213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3047601213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.831557937
Short name	T694
Test name
Test status
Simulation time	135564658 ps
CPU time	1.49 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:20:08 PM PST 23
Peak memory	219828 kb
Host	smart-50b5dd40-fdee-4046-88bc-03f7492cbcc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831557937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.831557937 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.799656466
Short name	T788
Test name
Test status
Simulation time	1055678904585 ps
CPU time	3344.39 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 02:15:57 PM PST 23
Peak memory	499096 kb
Host	smart-30b44a15-0311-485f-bed6-da02e4634f26
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799656466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an d_output.799656466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.3509648838
Short name	T357
Test name
Test status
Simulation time	16117387259 ps
CPU time	501.79 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 01:28:21 PM PST 23
Peak memory	257556 kb
Host	smart-533998bc-e0ce-4f94-94ca-e2922ebe4f32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509648838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3509648838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.647771008
Short name	T1005
Test name
Test status
Simulation time	2600516154 ps
CPU time	53.99 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:20:55 PM PST 23
Peak memory	226968 kb
Host	smart-b089d107-05d2-4d1a-b719-3a8667269f16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647771008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.647771008 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.1925605935
Short name	T984
Test name
Test status
Simulation time	274197870356 ps
CPU time	942.82 seconds
Started	Dec 24 01:19:59 PM PST 23
Finished	Dec 24 01:35:47 PM PST 23
Peak memory	316976 kb
Host	smart-71ff266a-0d6a-4cd0-a437-bbf61c87aee4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1925605935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1925605935 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_stress_all_with_rand_reset.154854045
Short name	T554
Test name
Test status
Simulation time	64569031858 ps
CPU time	316.23 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 01:25:19 PM PST 23
Peak memory	270276 kb
Host	smart-ae520ff0-74f2-46cb-b10e-5f3e051e16dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=154854045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.154854045 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.4180967158
Short name	T510
Test name
Test status
Simulation time	229882724 ps
CPU time	6.14 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:20:06 PM PST 23
Peak memory	220332 kb
Host	smart-0706fc77-7fc9-42c9-a538-6b81256eca19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180967158 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.4180967158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3366043119
Short name	T571
Test name
Test status
Simulation time	106716670 ps
CPU time	5.83 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:20:07 PM PST 23
Peak memory	218832 kb
Host	smart-3b3c48c1-218d-4255-9275-92f2fb958864
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366043119 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3366043119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.2415382825
Short name	T348
Test name
Test status
Simulation time	111034709476 ps
CPU time	2521.59 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 02:02:01 PM PST 23
Peak memory	405160 kb
Host	smart-e808e087-f37b-4ac0-a251-c9d08289199c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2415382825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.2415382825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.3407353531
Short name	T1139
Test name
Test status
Simulation time	19236848354 ps
CPU time	1992.06 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:53:17 PM PST 23
Peak memory	384416 kb
Host	smart-ba64eed3-5483-4c2b-a5db-4c7377812439
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3407353531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3407353531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.1421191384
Short name	T319
Test name
Test status
Simulation time	450432911820 ps
CPU time	1953.81 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 01:52:35 PM PST 23
Peak memory	348884 kb
Host	smart-c38921a4-7234-4552-bf2f-1f04fe9bd841
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1421191384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.1421191384 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.4122862254
Short name	T626
Test name
Test status
Simulation time	33269467061 ps
CPU time	1284.2 seconds
Started	Dec 24 01:19:58 PM PST 23
Finished	Dec 24 01:41:28 PM PST 23
Peak memory	302924 kb
Host	smart-a0b0249f-5c2d-4d6f-bb7e-94adc9e27f35
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4122862254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.4122862254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.1214898337
Short name	T445
Test name
Test status
Simulation time	61393215698 ps
CPU time	4906.63 seconds
Started	Dec 24 01:19:56 PM PST 23
Finished	Dec 24 02:41:48 PM PST 23
Peak memory	671836 kb
Host	smart-209f582f-c6c0-496b-a257-71c736a64d3c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1214898337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1214898337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.3586477548
Short name	T667
Test name
Test status
Simulation time	226857753553 ps
CPU time	4928.27 seconds
Started	Dec 24 01:19:55 PM PST 23
Finished	Dec 24 02:42:08 PM PST 23
Peak memory	573524 kb
Host	smart-ab766d9e-62fc-49f0-bb97-340dc8200853
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3586477548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3586477548 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.2255449658
Short name	T1031
Test name
Test status
Simulation time	64103521 ps
CPU time	0.91 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:20:07 PM PST 23
Peak memory	218500 kb
Host	smart-a08eaa07-28ae-414e-b46c-17c8075f81c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255449658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2255449658 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.2475769400
Short name	T557
Test name
Test status
Simulation time	7570778026 ps
CPU time	183.65 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:23:17 PM PST 23
Peak memory	241544 kb
Host	smart-d65cf5d6-b12b-4884-b8be-4cdf34ca0e11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475769400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2475769400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.985838899
Short name	T674
Test name
Test status
Simulation time	963988562 ps
CPU time	41.94 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:20:51 PM PST 23
Peak memory	239896 kb
Host	smart-febecfb7-7160-40cb-85fd-521ddf5cbc8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985838899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.985838899 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.2948719517
Short name	T1115
Test name
Test status
Simulation time	7341045914 ps
CPU time	410.74 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:27:03 PM PST 23
Peak memory	255600 kb
Host	smart-ff4a7a0c-4ecd-430c-b174-74c52b19f24d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948719517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2948719517 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.4214241564
Short name	T1078
Test name
Test status
Simulation time	65875598054 ps
CPU time	160.19 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:22:54 PM PST 23
Peak memory	243340 kb
Host	smart-b0bc6dcd-5fb1-4e2c-b57f-6755a5bdd0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214241564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4214241564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.3712706411
Short name	T767
Test name
Test status
Simulation time	1861241017 ps
CPU time	5.87 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:20:18 PM PST 23
Peak memory	218584 kb
Host	smart-42e4a357-a717-4709-98fe-6a8c64823ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712706411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3712706411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.640889764
Short name	T387
Test name
Test status
Simulation time	79884721 ps
CPU time	1.22 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 01:20:08 PM PST 23
Peak memory	219872 kb
Host	smart-f5e7223d-a2e4-4c96-98ee-338fb09d2eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640889764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.640889764 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.3260648700
Short name	T682
Test name
Test status
Simulation time	5127867817 ps
CPU time	488.23 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:28:15 PM PST 23
Peak memory	268308 kb
Host	smart-163a82d5-8e84-4629-a861-755e926027b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260648700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a nd_output.3260648700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.4044812726
Short name	T236
Test name
Test status
Simulation time	48600965342 ps
CPU time	301.54 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:25:10 PM PST 23
Peak memory	248528 kb
Host	smart-e575f350-beb2-4963-bc90-157c6590aacb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044812726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.4044812726 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.2859864258
Short name	T559
Test name
Test status
Simulation time	1270563117 ps
CPU time	28.21 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:20:35 PM PST 23
Peak memory	226716 kb
Host	smart-0f615203-f715-415b-a634-edc0e363909d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859864258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2859864258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.3614640884
Short name	T476
Test name
Test status
Simulation time	279460043606 ps
CPU time	2501.23 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 02:01:50 PM PST 23
Peak memory	481484 kb
Host	smart-fcff5e6d-1669-4ad6-b6d0-20eecff1441c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3614640884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3614640884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_stress_all_with_rand_reset.1243762283
Short name	T952
Test name
Test status
Simulation time	194473327109 ps
CPU time	1195.45 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:40:02 PM PST 23
Peak memory	317432 kb
Host	smart-0132bce2-1400-44ec-b932-d4aadc93d0c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1243762283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.1243762283 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.342008427
Short name	T1076
Test name
Test status
Simulation time	265018078 ps
CPU time	7.18 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:20:14 PM PST 23
Peak memory	220308 kb
Host	smart-340f3c8e-ecc5-4d27-83f8-e66ab50a9b94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342008427 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 34.kmac_test_vectors_kmac.342008427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1687957539
Short name	T715
Test name
Test status
Simulation time	1228329856 ps
CPU time	6.91 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:20:19 PM PST 23
Peak memory	220256 kb
Host	smart-7ac80bd4-c798-4872-85b1-706bf213236b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687957539 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1687957539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.2322154402
Short name	T679
Test name
Test status
Simulation time	76485765788 ps
CPU time	2050.42 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 01:54:18 PM PST 23
Peak memory	398668 kb
Host	smart-9bd60785-4c4b-4237-af9f-947e075aa788
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2322154402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2322154402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.2639490851
Short name	T927
Test name
Test status
Simulation time	87999493976 ps
CPU time	1774.94 seconds
Started	Dec 24 01:20:05 PM PST 23
Finished	Dec 24 01:49:45 PM PST 23
Peak memory	376736 kb
Host	smart-ec7bc28d-086b-48d6-b33b-171446557774
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2639490851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2639490851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.3212826179
Short name	T1085
Test name
Test status
Simulation time	15176931248 ps
CPU time	1503.42 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:45:10 PM PST 23
Peak memory	350480 kb
Host	smart-72bdf499-33e9-4494-8506-31156a4ac60a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3212826179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.3212826179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.1668627440
Short name	T304
Test name
Test status
Simulation time	152948154150 ps
CPU time	1421.84 seconds
Started	Dec 24 01:20:05 PM PST 23
Finished	Dec 24 01:43:51 PM PST 23
Peak memory	301280 kb
Host	smart-e8c60c1f-02f3-4525-b8d4-5f0928aa7ed3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1668627440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1668627440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.4259190968
Short name	T350
Test name
Test status
Simulation time	255110462769 ps
CPU time	4893.23 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 02:41:40 PM PST 23
Peak memory	646804 kb
Host	smart-3cc2d194-a306-459a-94a7-9e821ff2a4e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4259190968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.4259190968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.1974579355
Short name	T205
Test name
Test status
Simulation time	564567955626 ps
CPU time	5004.32 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 02:43:32 PM PST 23
Peak memory	577232 kb
Host	smart-93252d23-bc63-49b5-a428-f4a2af93b34e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1974579355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1974579355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.1822827379
Short name	T975
Test name
Test status
Simulation time	44434960 ps
CPU time	0.84 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:20:15 PM PST 23
Peak memory	219628 kb
Host	smart-ddd4e6d4-5cf9-4525-8c1e-dbedaa601814
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822827379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1822827379 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.1395197228
Short name	T1000
Test name
Test status
Simulation time	11844811680 ps
CPU time	388.21 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:26:37 PM PST 23
Peak memory	255088 kb
Host	smart-271de55c-08a8-4041-b521-8ea6c594db5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395197228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1395197228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.905059433
Short name	T194
Test name
Test status
Simulation time	30443043512 ps
CPU time	537.51 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:29:10 PM PST 23
Peak memory	235220 kb
Host	smart-368b7777-a891-4757-831e-23383829a800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905059433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.905059433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.1567284804
Short name	T973
Test name
Test status
Simulation time	64352799882 ps
CPU time	298.06 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:25:05 PM PST 23
Peak memory	248028 kb
Host	smart-6f7a7cda-b4af-4772-aa6c-9b74d00e8817
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567284804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1567284804 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.2446204755
Short name	T776
Test name
Test status
Simulation time	19670476861 ps
CPU time	375.65 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:26:27 PM PST 23
Peak memory	267460 kb
Host	smart-bfeef4ec-3ab3-45ee-8b75-53616a0ef92d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446204755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2446204755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.2653551867
Short name	T820
Test name
Test status
Simulation time	1408291909 ps
CPU time	3.08 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 01:20:10 PM PST 23
Peak memory	218788 kb
Host	smart-e6db5936-c96c-4b6f-8aa6-ef60b5ff973f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653551867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2653551867 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.728877632
Short name	T505
Test name
Test status
Simulation time	2739512469 ps
CPU time	21.56 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 01:20:32 PM PST 23
Peak memory	235824 kb
Host	smart-298e88d6-0b5c-4d99-8660-65f018a6ca34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728877632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.728877632 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.445935321
Short name	T1138
Test name
Test status
Simulation time	182699817060 ps
CPU time	2936.9 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 02:09:06 PM PST 23
Peak memory	448368 kb
Host	smart-b93c1c74-8a84-48ec-b303-bf6213b16f2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445935321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an d_output.445935321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.290799945
Short name	T254
Test name
Test status
Simulation time	895918898 ps
CPU time	72.36 seconds
Started	Dec 24 01:20:08 PM PST 23
Finished	Dec 24 01:21:24 PM PST 23
Peak memory	230088 kb
Host	smart-7d5c4241-2600-4cfb-881c-5b1aa7f9e43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290799945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.290799945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.375129364
Short name	T1097
Test name
Test status
Simulation time	3800570162 ps
CPU time	68.35 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	220120 kb
Host	smart-cd7be5a6-b3c4-472f-ae25-49c0a243983c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375129364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.375129364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.784736871
Short name	T641
Test name
Test status
Simulation time	68313528999 ps
CPU time	1833.19 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:50:39 PM PST 23
Peak memory	375172 kb
Host	smart-610714b3-f17c-4ca1-8eff-d687894450e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=784736871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.784736871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.1439910763
Short name	T991
Test name
Test status
Simulation time	404400372 ps
CPU time	5.74 seconds
Started	Dec 24 01:20:01 PM PST 23
Finished	Dec 24 01:20:12 PM PST 23
Peak memory	220296 kb
Host	smart-5e1745fc-3589-46a2-936f-22079ad362b6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439910763 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.1439910763 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1296746615
Short name	T234
Test name
Test status
Simulation time	756947812 ps
CPU time	5.9 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 01:20:13 PM PST 23
Peak memory	220224 kb
Host	smart-f7f8c59f-08ed-421a-a5d1-2df7ae981f85
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296746615 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1296746615 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.4003894651
Short name	T439
Test name
Test status
Simulation time	87416075992 ps
CPU time	2045.61 seconds
Started	Dec 24 01:20:00 PM PST 23
Finished	Dec 24 01:54:11 PM PST 23
Peak memory	396196 kb
Host	smart-cbe654ad-2aab-4bf3-be6e-aa4ce8b12d2c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4003894651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.4003894651 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.452665783
Short name	T395
Test name
Test status
Simulation time	776599639083 ps
CPU time	2263.56 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:57:53 PM PST 23
Peak memory	390380 kb
Host	smart-4f39a0f6-abff-48ca-a420-805b7d94b626
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=452665783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.452665783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.2802189079
Short name	T1071
Test name
Test status
Simulation time	72844333671 ps
CPU time	1857.66 seconds
Started	Dec 24 01:20:02 PM PST 23
Finished	Dec 24 01:51:05 PM PST 23
Peak memory	341188 kb
Host	smart-0f290359-1248-4dde-a433-8360beaba7fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2802189079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2802189079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.1745946736
Short name	T1137
Test name
Test status
Simulation time	134607503714 ps
CPU time	1335.31 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:42:25 PM PST 23
Peak memory	304760 kb
Host	smart-407eed3e-eeb0-4ffb-926b-fe3878ab5c5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1745946736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1745946736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.4189391508
Short name	T811
Test name
Test status
Simulation time	173145206101 ps
CPU time	5514.53 seconds
Started	Dec 24 01:20:03 PM PST 23
Finished	Dec 24 02:52:03 PM PST 23
Peak memory	637224 kb
Host	smart-532a92c0-38a8-44d9-8d71-88a23a648c0d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4189391508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.4189391508 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.207641471
Short name	T655
Test name
Test status
Simulation time	1362331223770 ps
CPU time	4683.66 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 02:38:14 PM PST 23
Peak memory	574324 kb
Host	smart-c083b78f-1ecb-48dd-978e-2c9c2883eb9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=207641471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.207641471 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.1854766632
Short name	T332
Test name
Test status
Simulation time	26811178 ps
CPU time	0.96 seconds
Started	Dec 24 01:20:18 PM PST 23
Finished	Dec 24 01:20:20 PM PST 23
Peak memory	219788 kb
Host	smart-2ccd78aa-a595-4578-a0ae-4b96f02207e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854766632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1854766632 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.3905663900
Short name	T291
Test name
Test status
Simulation time	1494207137 ps
CPU time	143.26 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:22:37 PM PST 23
Peak memory	228636 kb
Host	smart-a2dadfa6-9826-4f97-987b-e515bccd8652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905663900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3905663900 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.3951022046
Short name	T409
Test name
Test status
Simulation time	7256063578 ps
CPU time	132.92 seconds
Started	Dec 24 01:20:17 PM PST 23
Finished	Dec 24 01:22:31 PM PST 23
Peak memory	243364 kb
Host	smart-73b4ced1-e54c-4dda-855b-a522ff35f74d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951022046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3951022046 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.154733043
Short name	T956
Test name
Test status
Simulation time	2368197366 ps
CPU time	200.35 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:23:38 PM PST 23
Peak memory	251876 kb
Host	smart-db262e21-6e22-45df-ad38-b6abfb5b57b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154733043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.154733043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.3246335832
Short name	T590
Test name
Test status
Simulation time	2303540946 ps
CPU time	3.78 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:20:21 PM PST 23
Peak memory	218084 kb
Host	smart-a40bf9a8-5de5-4922-92dd-7ba456d27053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246335832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3246335832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.3489357024
Short name	T572
Test name
Test status
Simulation time	483494115 ps
CPU time	20.98 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:20:39 PM PST 23
Peak memory	235196 kb
Host	smart-856c69fd-0bb9-4e2d-b8f4-34f81c2120cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489357024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3489357024 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.2497897325
Short name	T417
Test name
Test status
Simulation time	74791501687 ps
CPU time	2875.61 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 02:08:10 PM PST 23
Peak memory	438148 kb
Host	smart-0d80fae9-5c87-485f-9173-7fe0993af0cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497897325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.2497897325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.176024
Short name	T1016
Test name
Test status
Simulation time	6236747831 ps
CPU time	271.04 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:24:45 PM PST 23
Peak memory	245520 kb
Host	smart-f588792a-990a-4109-ae2d-ae27fbb1ead1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.176024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.3431016026
Short name	T527
Test name
Test status
Simulation time	15724537518 ps
CPU time	62.17 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:21:16 PM PST 23
Peak memory	225324 kb
Host	smart-eea8390f-1c12-498c-8241-cceb7d134b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431016026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3431016026 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.1417821873
Short name	T745
Test name
Test status
Simulation time	48920255990 ps
CPU time	1293.91 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:41:43 PM PST 23
Peak memory	357044 kb
Host	smart-1793ada8-eedf-4638-904c-54bb92f44812
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1417821873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1417821873 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.2870109499
Short name	T1022
Test name
Test status
Simulation time	87200073823 ps
CPU time	1792.09 seconds
Started	Dec 24 01:20:04 PM PST 23
Finished	Dec 24 01:50:01 PM PST 23
Peak memory	333940 kb
Host	smart-2ce3e1b3-5969-4c7d-9c9d-4c8883788a41
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2870109499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.2870109499 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.4258849603
Short name	T465
Test name
Test status
Simulation time	379394715 ps
CPU time	5.55 seconds
Started	Dec 24 01:20:17 PM PST 23
Finished	Dec 24 01:20:24 PM PST 23
Peak memory	220204 kb
Host	smart-9ca046ff-981c-4f36-9aea-32d514a17b73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258849603 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.4258849603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.658734328
Short name	T573
Test name
Test status
Simulation time	250110941 ps
CPU time	6.39 seconds
Started	Dec 24 01:20:17 PM PST 23
Finished	Dec 24 01:20:25 PM PST 23
Peak memory	220152 kb
Host	smart-4a23e704-9ec1-4ec1-8355-600f30457655
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658734328 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 36.kmac_test_vectors_kmac_xof.658734328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.1752099836
Short name	T716
Test name
Test status
Simulation time	171613838155 ps
CPU time	2323.28 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 01:58:58 PM PST 23
Peak memory	395696 kb
Host	smart-4e830465-d68c-4e41-a0db-94dbd3ba3d5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1752099836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1752099836 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.2203482613
Short name	T582
Test name
Test status
Simulation time	79570346283 ps
CPU time	2058.89 seconds
Started	Dec 24 01:20:11 PM PST 23
Finished	Dec 24 01:54:33 PM PST 23
Peak memory	384520 kb
Host	smart-2a88e2a9-bb96-4f8a-b8da-b7248a11b9df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2203482613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2203482613 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.1363371106
Short name	T1082
Test name
Test status
Simulation time	84881951882 ps
CPU time	1694.38 seconds
Started	Dec 24 01:20:03 PM PST 23
Finished	Dec 24 01:48:23 PM PST 23
Peak memory	339676 kb
Host	smart-e7e3476d-0768-40aa-a35f-89e0573b9656
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1363371106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1363371106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.3634724538
Short name	T296
Test name
Test status
Simulation time	126682144621 ps
CPU time	1331.69 seconds
Started	Dec 24 01:20:17 PM PST 23
Finished	Dec 24 01:42:30 PM PST 23
Peak memory	299980 kb
Host	smart-1f24c264-b33a-4d91-b057-5cd4cf14ab7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3634724538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3634724538 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.352971656
Short name	T246
Test name
Test status
Simulation time	183936165878 ps
CPU time	5726.62 seconds
Started	Dec 24 01:20:12 PM PST 23
Finished	Dec 24 02:55:41 PM PST 23
Peak memory	668684 kb
Host	smart-32109cea-2bef-443e-b146-557c00f1ee3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=352971656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.352971656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.701213931
Short name	T1112
Test name
Test status
Simulation time	295795819950 ps
CPU time	4576.13 seconds
Started	Dec 24 01:20:03 PM PST 23
Finished	Dec 24 02:36:25 PM PST 23
Peak memory	577772 kb
Host	smart-b545111c-663c-4cf1-b214-e9e08a3edeee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=701213931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.701213931 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.2126652902
Short name	T750
Test name
Test status
Simulation time	55781030 ps
CPU time	0.89 seconds
Started	Dec 24 01:20:20 PM PST 23
Finished	Dec 24 01:20:22 PM PST 23
Peak memory	218604 kb
Host	smart-65e7a48c-4110-4e97-bd87-ed00dfaf6325
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126652902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2126652902 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.604216992
Short name	T1009
Test name
Test status
Simulation time	12576513324 ps
CPU time	379.62 seconds
Started	Dec 24 01:20:18 PM PST 23
Finished	Dec 24 01:26:39 PM PST 23
Peak memory	253960 kb
Host	smart-1576d1d2-371e-43f3-b46c-7e2a8d69ed07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604216992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.604216992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.2056055333
Short name	T1047
Test name
Test status
Simulation time	50462205299 ps
CPU time	1190.9 seconds
Started	Dec 24 01:20:20 PM PST 23
Finished	Dec 24 01:40:12 PM PST 23
Peak memory	243232 kb
Host	smart-714010aa-4a91-4872-b2ec-59e9eb5346e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056055333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2056055333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.1669843539
Short name	T836
Test name
Test status
Simulation time	5036469818 ps
CPU time	75.55 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:21:33 PM PST 23
Peak memory	243396 kb
Host	smart-b64bb742-eba6-468b-b128-da9bd72a3dcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669843539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1669843539 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.2924713771
Short name	T44
Test name
Test status
Simulation time	16597858363 ps
CPU time	124.26 seconds
Started	Dec 24 01:20:17 PM PST 23
Finished	Dec 24 01:22:23 PM PST 23
Peak memory	251608 kb
Host	smart-ac551a6d-ff7a-4ebe-9e7d-1110e70d134b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924713771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2924713771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.3643415006
Short name	T608
Test name
Test status
Simulation time	1314299353 ps
CPU time	2.37 seconds
Started	Dec 24 01:20:15 PM PST 23
Finished	Dec 24 01:20:19 PM PST 23
Peak memory	218704 kb
Host	smart-8d686c2f-bbd3-42f5-ac8f-394760d436ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643415006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3643415006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.905993205
Short name	T700
Test name
Test status
Simulation time	3774799990 ps
CPU time	24.48 seconds
Started	Dec 24 01:20:19 PM PST 23
Finished	Dec 24 01:20:45 PM PST 23
Peak memory	236392 kb
Host	smart-66f812ae-33db-4330-817b-bb5c6b02e966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905993205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.905993205 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.3995208946
Short name	T410
Test name
Test status
Simulation time	86034397679 ps
CPU time	3000.01 seconds
Started	Dec 24 01:20:19 PM PST 23
Finished	Dec 24 02:10:20 PM PST 23
Peak memory	461664 kb
Host	smart-2af40e08-c53e-409e-88b5-930aa338eab7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995208946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.3995208946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.4129964825
Short name	T713
Test name
Test status
Simulation time	2170594095 ps
CPU time	74.06 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:21:31 PM PST 23
Peak memory	229204 kb
Host	smart-b46bb7a3-dc5a-4dc1-bdc2-cfdd5b4f7f49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129964825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4129964825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.2301693779
Short name	T1029
Test name
Test status
Simulation time	1175310789 ps
CPU time	48.01 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:21:05 PM PST 23
Peak memory	226928 kb
Host	smart-6bb73dbc-0248-473b-aa17-9ed337cd028e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301693779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2301693779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.3549802206
Short name	T698
Test name
Test status
Simulation time	28025839520 ps
CPU time	910.81 seconds
Started	Dec 24 01:20:20 PM PST 23
Finished	Dec 24 01:35:33 PM PST 23
Peak memory	336076 kb
Host	smart-03092197-e0f6-468a-b8a8-1e642aeef2b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3549802206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3549802206 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_stress_all_with_rand_reset.3501420242
Short name	T1049
Test name
Test status
Simulation time	335908522403 ps
CPU time	1973.87 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:53:28 PM PST 23
Peak memory	358352 kb
Host	smart-ed04c3a6-86a9-4e48-b893-b0037b232a60
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3501420242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all_with_rand_reset.3501420242 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.2150844857
Short name	T925
Test name
Test status
Simulation time	102929854 ps
CPU time	5.94 seconds
Started	Dec 24 01:20:15 PM PST 23
Finished	Dec 24 01:20:22 PM PST 23
Peak memory	218768 kb
Host	smart-f2ccc0c3-c08e-4d59-892b-77899c340e5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150844857 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.2150844857 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2180951355
Short name	T279
Test name
Test status
Simulation time	542121693 ps
CPU time	6.26 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:20:24 PM PST 23
Peak memory	220100 kb
Host	smart-12378969-d38a-4609-bcf5-af2da3559d7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180951355 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2180951355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.1546576400
Short name	T676
Test name
Test status
Simulation time	66013599772 ps
CPU time	2205.67 seconds
Started	Dec 24 01:20:16 PM PST 23
Finished	Dec 24 01:57:03 PM PST 23
Peak memory	393836 kb
Host	smart-992db500-9839-4991-8eed-a5549ebc339e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1546576400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1546576400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.3433278224
Short name	T347
Test name
Test status
Simulation time	63495829427 ps
CPU time	2382.84 seconds
Started	Dec 24 01:20:05 PM PST 23
Finished	Dec 24 01:59:53 PM PST 23
Peak memory	392908 kb
Host	smart-e4812a57-7c59-484d-bc30-52e6ec1a4d70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3433278224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.3433278224 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.630227479
Short name	T652
Test name
Test status
Simulation time	72046652162 ps
CPU time	1789.86 seconds
Started	Dec 24 01:20:15 PM PST 23
Finished	Dec 24 01:50:06 PM PST 23
Peak memory	340156 kb
Host	smart-97ade41e-8f4a-458a-aa36-b33c13a0afa8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=630227479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.630227479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.3272876017
Short name	T278
Test name
Test status
Simulation time	11326552796 ps
CPU time	1162.34 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 01:39:33 PM PST 23
Peak memory	303200 kb
Host	smart-cf6317c0-94b0-465e-a109-6ea8f65638c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3272876017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3272876017 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.1552671069
Short name	T513
Test name
Test status
Simulation time	271605070981 ps
CPU time	6246.5 seconds
Started	Dec 24 01:20:07 PM PST 23
Finished	Dec 24 03:04:18 PM PST 23
Peak memory	661960 kb
Host	smart-6f4175ec-7de1-42ad-9479-86adf1bf0597
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1552671069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1552671069 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.2257383001
Short name	T1012
Test name
Test status
Simulation time	66877342914 ps
CPU time	4356.53 seconds
Started	Dec 24 01:20:06 PM PST 23
Finished	Dec 24 02:32:47 PM PST 23
Peak memory	573964 kb
Host	smart-37355ffd-11a9-4fdc-936d-a033b2f076ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2257383001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2257383001 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.3944949774
Short name	T257
Test name
Test status
Simulation time	76597445 ps
CPU time	0.9 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:20:35 PM PST 23
Peak memory	219668 kb
Host	smart-42932048-2945-4347-a749-387565f5f5cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944949774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3944949774 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.1792507303
Short name	T360
Test name
Test status
Simulation time	106547126864 ps
CPU time	298.53 seconds
Started	Dec 24 01:20:36 PM PST 23
Finished	Dec 24 01:25:35 PM PST 23
Peak memory	248824 kb
Host	smart-bc164454-5afa-4305-bc16-b9697730a0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792507303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1792507303 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.4217100247
Short name	T900
Test name
Test status
Simulation time	4267736159 ps
CPU time	444.4 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:27:58 PM PST 23
Peak memory	232900 kb
Host	smart-bd662825-caee-42a8-936b-91639d09abee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217100247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.4217100247 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.2066386611
Short name	T757
Test name
Test status
Simulation time	5824917630 ps
CPU time	97.85 seconds
Started	Dec 24 01:20:45 PM PST 23
Finished	Dec 24 01:22:24 PM PST 23
Peak memory	232956 kb
Host	smart-e8098965-ab14-4e18-b1e5-c5090ebe7994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066386611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2066386611 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.105056644
Short name	T675
Test name
Test status
Simulation time	20530091995 ps
CPU time	134.56 seconds
Started	Dec 24 01:20:34 PM PST 23
Finished	Dec 24 01:22:50 PM PST 23
Peak memory	251648 kb
Host	smart-5a5ac43f-2085-466d-9793-82fcca1a4f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105056644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.105056644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.2759414988
Short name	T837
Test name
Test status
Simulation time	2495401776 ps
CPU time	4.09 seconds
Started	Dec 24 01:20:30 PM PST 23
Finished	Dec 24 01:20:35 PM PST 23
Peak memory	218852 kb
Host	smart-4f77ce7e-0a11-40f3-a500-ad8ca3fe0cdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759414988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2759414988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.2227454293
Short name	T45
Test name
Test status
Simulation time	6295752965 ps
CPU time	27.18 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:21:14 PM PST 23
Peak memory	236428 kb
Host	smart-f76dba49-ef95-401c-b08f-dc352bbab593
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227454293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2227454293 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.3510777767
Short name	T414
Test name
Test status
Simulation time	205536711540 ps
CPU time	1452.41 seconds
Started	Dec 24 01:20:34 PM PST 23
Finished	Dec 24 01:44:48 PM PST 23
Peak memory	323248 kb
Host	smart-9bf7dc96-24d5-4519-a7e8-5474ca879408
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510777767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.3510777767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.2326697097
Short name	T841
Test name
Test status
Simulation time	6324264392 ps
CPU time	502.16 seconds
Started	Dec 24 01:20:35 PM PST 23
Finished	Dec 24 01:28:58 PM PST 23
Peak memory	257964 kb
Host	smart-ef9acab7-228c-4343-9d8d-44e227699106
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326697097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2326697097 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.2293729458
Short name	T160
Test name
Test status
Simulation time	43943978410 ps
CPU time	91.13 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:22:05 PM PST 23
Peak memory	225024 kb
Host	smart-8432e607-6c28-4a8f-a17d-ac48a6c6da3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293729458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2293729458 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.4092002198
Short name	T758
Test name
Test status
Simulation time	30577943394 ps
CPU time	1250.82 seconds
Started	Dec 24 01:20:45 PM PST 23
Finished	Dec 24 01:41:36 PM PST 23
Peak memory	325464 kb
Host	smart-cef35147-ab43-4a74-8bee-87565372e844
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4092002198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.4092002198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_stress_all_with_rand_reset.476462120
Short name	T496
Test name
Test status
Simulation time	313221747907 ps
CPU time	1903.1 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:52:18 PM PST 23
Peak memory	325284 kb
Host	smart-ab9ca4fa-edc6-4c38-bbc0-26b73b9b506d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=476462120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.476462120 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.4161348955
Short name	T185
Test name
Test status
Simulation time	217514453 ps
CPU time	6.4 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:20:41 PM PST 23
Peak memory	220348 kb
Host	smart-6ec863a3-83cc-4e42-b05f-583d3d62a2bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161348955 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.4161348955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2000171764
Short name	T921
Test name
Test status
Simulation time	119916459 ps
CPU time	6.03 seconds
Started	Dec 24 01:20:34 PM PST 23
Finished	Dec 24 01:20:41 PM PST 23
Peak memory	220304 kb
Host	smart-7c0216bb-98a1-4d94-b987-e1cf58e75361
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000171764 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2000171764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.929939613
Short name	T198
Test name
Test status
Simulation time	115561443260 ps
CPU time	2133.55 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:56:07 PM PST 23
Peak memory	403904 kb
Host	smart-26f31e08-56dd-4e72-903d-2425faa47ac2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=929939613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.929939613 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.1264454030
Short name	T28
Test name
Test status
Simulation time	131088837027 ps
CPU time	2296.49 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:58:51 PM PST 23
Peak memory	395056 kb
Host	smart-ae5ab6d3-525b-49b5-8f6f-fd149da4da1a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1264454030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1264454030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.3908997058
Short name	T579
Test name
Test status
Simulation time	104455450066 ps
CPU time	1464.09 seconds
Started	Dec 24 01:20:31 PM PST 23
Finished	Dec 24 01:44:56 PM PST 23
Peak memory	340956 kb
Host	smart-f59624a0-7967-49ff-86e9-049a178d0a42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3908997058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3908997058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.1372789959
Short name	T503
Test name
Test status
Simulation time	556173088706 ps
CPU time	1195.26 seconds
Started	Dec 24 01:20:44 PM PST 23
Finished	Dec 24 01:40:40 PM PST 23
Peak memory	301404 kb
Host	smart-aa871719-6bc6-4fe1-ab40-8e8272e4b40b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1372789959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1372789959 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.120223610
Short name	T158
Test name
Test status
Simulation time	1350585146262 ps
CPU time	5645.61 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 02:54:55 PM PST 23
Peak memory	652472 kb
Host	smart-104e5a2c-ea58-4dc6-bafd-cce0e6660bb2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=120223610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.120223610 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.2062167561
Short name	T1067
Test name
Test status
Simulation time	218104196560 ps
CPU time	4512.16 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 02:35:47 PM PST 23
Peak memory	556936 kb
Host	smart-dd5a5454-529b-4dd8-9615-68ee4183430f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2062167561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.2062167561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.1236296129
Short name	T980
Test name
Test status
Simulation time	17794165 ps
CPU time	0.86 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:20:34 PM PST 23
Peak memory	218388 kb
Host	smart-fb022125-a27a-4be8-9dfc-bf33c973c6e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236296129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1236296129 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.2633050543
Short name	T1090
Test name
Test status
Simulation time	21971078831 ps
CPU time	321.93 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:26:10 PM PST 23
Peak memory	250200 kb
Host	smart-5d3a2d7d-7224-4a6c-b7a9-93b57a621558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633050543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2633050543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.3916586162
Short name	T549
Test name
Test status
Simulation time	4104701830 ps
CPU time	84.57 seconds
Started	Dec 24 01:20:34 PM PST 23
Finished	Dec 24 01:22:00 PM PST 23
Peak memory	225644 kb
Host	smart-7bbbf9f7-6ca8-4575-9797-0143f8e55eee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916586162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3916586162 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.2904995903
Short name	T270
Test name
Test status
Simulation time	151747136 ps
CPU time	3.19 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:20:36 PM PST 23
Peak memory	218700 kb
Host	smart-0a2a12f7-3acb-4175-a84c-16f0fa4502d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904995903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2904995903 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.3721511094
Short name	T896
Test name
Test status
Simulation time	11993528201 ps
CPU time	305.71 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:25:52 PM PST 23
Peak memory	259764 kb
Host	smart-69990e11-5fa3-42eb-848f-3e0540bdbbf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721511094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3721511094 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.1340711484
Short name	T102
Test name
Test status
Simulation time	1148469777 ps
CPU time	2.09 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	218692 kb
Host	smart-6be110e9-baaf-4b46-a5af-12587a2e918b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340711484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1340711484 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.1789575264
Short name	T11
Test name
Test status
Simulation time	53852537 ps
CPU time	1.51 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:20:34 PM PST 23
Peak memory	219920 kb
Host	smart-eca03389-251a-4e9d-8567-8fdf1491adc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789575264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1789575264 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.1817735261
Short name	T1033
Test name
Test status
Simulation time	10254485523 ps
CPU time	353.46 seconds
Started	Dec 24 01:20:38 PM PST 23
Finished	Dec 24 01:26:32 PM PST 23
Peak memory	253760 kb
Host	smart-00567718-b7e6-4cee-b0cc-dec417eec7b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817735261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.1817735261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.1571572559
Short name	T744
Test name
Test status
Simulation time	27475190170 ps
CPU time	376.12 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:27:03 PM PST 23
Peak memory	251660 kb
Host	smart-f3f60746-cd71-48fc-9319-88831a116497
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571572559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1571572559 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.322880900
Short name	T1045
Test name
Test status
Simulation time	12518201895 ps
CPU time	58.12 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:21:31 PM PST 23
Peak memory	226928 kb
Host	smart-38763203-2060-4657-b027-11447af22a43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322880900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.322880900 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.3245025053
Short name	T639
Test name
Test status
Simulation time	29649099553 ps
CPU time	511 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:29:06 PM PST 23
Peak memory	264640 kb
Host	smart-a572bda1-9f0b-4f5c-925f-903681952225
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3245025053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3245025053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.2853355735
Short name	T340
Test name
Test status
Simulation time	246815438 ps
CPU time	6.13 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:20:41 PM PST 23
Peak memory	218848 kb
Host	smart-7ae0e01a-2ab6-4a25-9f62-00434ec846c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853355735 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.2853355735 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3102683085
Short name	T107
Test name
Test status
Simulation time	339383687 ps
CPU time	5.23 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 01:20:38 PM PST 23
Peak memory	218840 kb
Host	smart-9420f4c5-4f13-4690-a294-fd937d68233c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102683085 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3102683085 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.2396406510
Short name	T874
Test name
Test status
Simulation time	248829221735 ps
CPU time	2356.92 seconds
Started	Dec 24 01:20:49 PM PST 23
Finished	Dec 24 02:00:08 PM PST 23
Peak memory	394316 kb
Host	smart-5da45b18-5f1e-463c-aad7-25925891f015
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2396406510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2396406510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.730331490
Short name	T587
Test name
Test status
Simulation time	23502785234 ps
CPU time	1924.43 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:52:40 PM PST 23
Peak memory	383656 kb
Host	smart-b2743d1f-5c64-4cc0-b603-c34f4d5d9a8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=730331490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.730331490 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.1454020865
Short name	T373
Test name
Test status
Simulation time	67460141697 ps
CPU time	1556.68 seconds
Started	Dec 24 01:20:44 PM PST 23
Finished	Dec 24 01:46:42 PM PST 23
Peak memory	346792 kb
Host	smart-c5e6585f-f36a-43d8-969d-10138265541a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1454020865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1454020865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.2057663348
Short name	T184
Test name
Test status
Simulation time	117268306049 ps
CPU time	1306.25 seconds
Started	Dec 24 01:20:35 PM PST 23
Finished	Dec 24 01:42:23 PM PST 23
Peak memory	299992 kb
Host	smart-f35d5503-625b-4c72-85de-5762d5fb5add
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2057663348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2057663348 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.3096292127
Short name	T552
Test name
Test status
Simulation time	1024936758873 ps
CPU time	6131.17 seconds
Started	Dec 24 01:20:32 PM PST 23
Finished	Dec 24 03:02:45 PM PST 23
Peak memory	650136 kb
Host	smart-bfea1d49-d5e0-4d2e-a27c-ee54a6f5834e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3096292127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.3096292127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.3446854485
Short name	T739
Test name
Test status
Simulation time	1040157472271 ps
CPU time	5001.27 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 02:44:10 PM PST 23
Peak memory	553520 kb
Host	smart-5f7cf910-1484-4ed1-a951-a8c51dfcacdb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3446854485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3446854485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.1915029067
Short name	T636
Test name
Test status
Simulation time	38629814 ps
CPU time	0.85 seconds
Started	Dec 24 01:18:21 PM PST 23
Finished	Dec 24 01:18:39 PM PST 23
Peak memory	218508 kb
Host	smart-3abf25af-9a96-43f5-9764-daf876659da9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915029067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1915029067 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.2163558045
Short name	T1025
Test name
Test status
Simulation time	27925280552 ps
CPU time	328.83 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 01:24:17 PM PST 23
Peak memory	248748 kb
Host	smart-c42817fa-5a3e-444f-aaf3-241149689358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163558045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2163558045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.109875806
Short name	T701
Test name
Test status
Simulation time	26660229810 ps
CPU time	400.03 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:25:24 PM PST 23
Peak memory	254392 kb
Host	smart-d7d25048-d1d8-4dae-93ed-4b0abc8290ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109875806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.109875806 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.3828014581
Short name	T1126
Test name
Test status
Simulation time	17237695390 ps
CPU time	202.83 seconds
Started	Dec 24 01:18:30 PM PST 23
Finished	Dec 24 01:22:11 PM PST 23
Peak memory	230516 kb
Host	smart-17b1dfdc-1dc1-4a25-8c25-86cc7d3a7b07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828014581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3828014581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.3187643268
Short name	T574
Test name
Test status
Simulation time	17423049 ps
CPU time	0.94 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:14 PM PST 23
Peak memory	218476 kb
Host	smart-fe240346-2943-42f1-b18c-358b540f2fa7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3187643268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3187643268 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.3465291886
Short name	T948
Test name
Test status
Simulation time	14354615 ps
CPU time	0.85 seconds
Started	Dec 24 01:18:23 PM PST 23
Finished	Dec 24 01:18:44 PM PST 23
Peak memory	218604 kb
Host	smart-ea573fbe-4d5f-4cca-a679-157aa0fe37a2
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3465291886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3465291886 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.2944332153
Short name	T541
Test name
Test status
Simulation time	5429730311 ps
CPU time	16.25 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:19:00 PM PST 23
Peak memory	219948 kb
Host	smart-dd41b8ff-9df5-493d-afb1-626f9a9cb758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944332153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2944332153 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.1615777296
Short name	T74
Test name
Test status
Simulation time	38465517186 ps
CPU time	387.67 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:25:16 PM PST 23
Peak memory	253640 kb
Host	smart-2cfcd984-acc5-4403-994f-32f5afbc0a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615777296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1615777296 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.3294617008
Short name	T858
Test name
Test status
Simulation time	21552665151 ps
CPU time	411.07 seconds
Started	Dec 24 01:18:13 PM PST 23
Finished	Dec 24 01:25:06 PM PST 23
Peak memory	259664 kb
Host	smart-b819461b-6e21-4bec-9f9c-9fe7243afc83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294617008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3294617008 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.2115082061
Short name	T813
Test name
Test status
Simulation time	142977449 ps
CPU time	1.62 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:18:50 PM PST 23
Peak memory	218736 kb
Host	smart-24923c29-86b8-43f1-b0d3-23443b0f4aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115082061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2115082061 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.2868057839
Short name	T271
Test name
Test status
Simulation time	103514329 ps
CPU time	1.34 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:18:44 PM PST 23
Peak memory	219944 kb
Host	smart-c8d73a0c-d984-46da-bcde-95052097be6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868057839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2868057839 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.2853636459
Short name	T244
Test name
Test status
Simulation time	8450102832 ps
CPU time	492.42 seconds
Started	Dec 24 01:18:21 PM PST 23
Finished	Dec 24 01:26:51 PM PST 23
Peak memory	272852 kb
Host	smart-5c90f55b-0d9c-4e36-98d0-358e1924a582
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853636459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.2853636459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.4115513190
Short name	T18
Test name
Test status
Simulation time	8166456962 ps
CPU time	202.1 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:22:11 PM PST 23
Peak memory	242368 kb
Host	smart-f777ab05-fb85-4f00-8338-62d57a3b9997
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115513190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4115513190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sideload.123890641
Short name	T23
Test name
Test status
Simulation time	14096971636 ps
CPU time	172.2 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:21:35 PM PST 23
Peak memory	240624 kb
Host	smart-2a3870e0-a2f6-4386-be6b-c541639b258d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123890641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.123890641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.2973271600
Short name	T322
Test name
Test status
Simulation time	7805136852 ps
CPU time	48.26 seconds
Started	Dec 24 01:18:21 PM PST 23
Finished	Dec 24 01:19:26 PM PST 23
Peak memory	227076 kb
Host	smart-c447b490-3c58-4648-938a-00b43ea9c083
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973271600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2973271600 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.2572597455
Short name	T926
Test name
Test status
Simulation time	29351260301 ps
CPU time	990.52 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:35:14 PM PST 23
Peak memory	343176 kb
Host	smart-fe0b9e90-a273-49d6-a056-233c32b3fe7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2572597455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2572597455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_stress_all_with_rand_reset.439575299
Short name	T556
Test name
Test status
Simulation time	62118092342 ps
CPU time	2924.98 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 02:06:58 PM PST 23
Peak memory	417608 kb
Host	smart-5ce31924-81b2-495b-838e-703cab5ffb3a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=439575299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.439575299 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.16173944
Short name	T807
Test name
Test status
Simulation time	821982297 ps
CPU time	6.38 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:18:49 PM PST 23
Peak memory	220272 kb
Host	smart-b1f2dcb4-5490-46d1-bd17-a38746aa59ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173944 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.kmac_test_vectors_kmac.16173944 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.603270398
Short name	T976
Test name
Test status
Simulation time	1009030257 ps
CPU time	5.76 seconds
Started	Dec 24 01:18:21 PM PST 23
Finished	Dec 24 01:18:39 PM PST 23
Peak memory	220324 kb
Host	smart-cb678833-3770-4ed4-a12b-1607dc92f787
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603270398 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.kmac_test_vectors_kmac_xof.603270398 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.2471915806
Short name	T323
Test name
Test status
Simulation time	78186328628 ps
CPU time	2031.2 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:52:05 PM PST 23
Peak memory	400644 kb
Host	smart-c173c82f-28b2-42d1-95d8-44bdc16572ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2471915806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2471915806 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.2064329057
Short name	T1107
Test name
Test status
Simulation time	386622574873 ps
CPU time	2025.95 seconds
Started	Dec 24 01:18:27 PM PST 23
Finished	Dec 24 01:52:35 PM PST 23
Peak memory	387340 kb
Host	smart-f6f7b27e-ba4d-4e8c-a6f6-09a7f708faea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2064329057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2064329057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.2179824761
Short name	T766
Test name
Test status
Simulation time	247169485530 ps
CPU time	1712.18 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:47:15 PM PST 23
Peak memory	333468 kb
Host	smart-fec7d7eb-bd0b-4af4-bb93-abb05d22c682
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2179824761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2179824761 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.3091492124
Short name	T196
Test name
Test status
Simulation time	20797044053 ps
CPU time	1107.95 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:37:11 PM PST 23
Peak memory	302000 kb
Host	smart-96d8ea0e-8e71-44c2-8954-025459f345d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3091492124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3091492124 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.2337894839
Short name	T241
Test name
Test status
Simulation time	270219113352 ps
CPU time	5429.36 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 02:49:13 PM PST 23
Peak memory	655108 kb
Host	smart-180f2e58-d7b7-4953-ab34-d91cd0a91cab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2337894839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2337894839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.184349945
Short name	T898
Test name
Test status
Simulation time	54105941955 ps
CPU time	4429.21 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 02:32:38 PM PST 23
Peak memory	565096 kb
Host	smart-971bebe3-cfe4-46c2-a345-55864a603f61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=184349945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.184349945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.2040787590
Short name	T467
Test name
Test status
Simulation time	137807777 ps
CPU time	0.88 seconds
Started	Dec 24 01:20:56 PM PST 23
Finished	Dec 24 01:20:57 PM PST 23
Peak memory	218624 kb
Host	smart-339d3835-f389-4941-92db-8c09069f6d57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040787590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2040787590 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.1860394771
Short name	T1058
Test name
Test status
Simulation time	55751356281 ps
CPU time	290.96 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:25:38 PM PST 23
Peak memory	247844 kb
Host	smart-f5c23501-1dbb-4c8d-8c01-41cb401f2546
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860394771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1860394771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.344097233
Short name	T1072
Test name
Test status
Simulation time	23543990427 ps
CPU time	821.34 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:34:30 PM PST 23
Peak memory	237912 kb
Host	smart-43d4d52a-0802-4cd0-9195-38304ad176f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344097233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.344097233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.1683542274
Short name	T1080
Test name
Test status
Simulation time	5084987487 ps
CPU time	202.18 seconds
Started	Dec 24 01:20:58 PM PST 23
Finished	Dec 24 01:24:21 PM PST 23
Peak memory	244420 kb
Host	smart-ac4841d9-125c-4eea-bfe9-cac116330475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683542274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1683542274 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.1537340046
Short name	T1037
Test name
Test status
Simulation time	25708470598 ps
CPU time	473.17 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:28:42 PM PST 23
Peak memory	268088 kb
Host	smart-d06f1abe-3830-445e-adfc-9382ba738746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537340046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1537340046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.1379973688
Short name	T34
Test name
Test status
Simulation time	474100016 ps
CPU time	3.08 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:20:52 PM PST 23
Peak memory	218780 kb
Host	smart-86af897b-34c1-4abc-b99e-9e43b5361483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379973688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1379973688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.3669241283
Short name	T73
Test name
Test status
Simulation time	107133179 ps
CPU time	1.36 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:20:51 PM PST 23
Peak memory	219880 kb
Host	smart-8f6b8539-a0e3-471f-83f5-f110ff20c1d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669241283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3669241283 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.382596668
Short name	T289
Test name
Test status
Simulation time	2298405410 ps
CPU time	54.29 seconds
Started	Dec 24 01:20:59 PM PST 23
Finished	Dec 24 01:21:54 PM PST 23
Peak memory	239388 kb
Host	smart-02725766-489f-4765-92c2-b761c486388e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382596668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an d_output.382596668 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.2670885258
Short name	T785
Test name
Test status
Simulation time	4624887226 ps
CPU time	359.9 seconds
Started	Dec 24 01:20:58 PM PST 23
Finished	Dec 24 01:26:58 PM PST 23
Peak memory	251652 kb
Host	smart-827c2ed5-490c-43c9-9b32-471bfbe0edee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670885258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2670885258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.249631646
Short name	T217
Test name
Test status
Simulation time	1260687666 ps
CPU time	11.4 seconds
Started	Dec 24 01:20:33 PM PST 23
Finished	Dec 24 01:20:45 PM PST 23
Peak memory	226936 kb
Host	smart-556eecd8-7234-4871-887c-435c16ede7e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249631646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.249631646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.2684978920
Short name	T923
Test name
Test status
Simulation time	58191132301 ps
CPU time	725.28 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:32:54 PM PST 23
Peak memory	316392 kb
Host	smart-1143effc-ced3-4807-9c29-d15df99db74f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2684978920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2684978920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.3961069430
Short name	T370
Test name
Test status
Simulation time	141886522330 ps
CPU time	614.35 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:31:03 PM PST 23
Peak memory	289272 kb
Host	smart-ae751484-f4d0-4e21-84ae-15575df46a19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3961069430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.3961069430 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.2005757617
Short name	T959
Test name
Test status
Simulation time	226726944 ps
CPU time	6.14 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:20:54 PM PST 23
Peak memory	220228 kb
Host	smart-532371b3-29a9-4b48-971c-46b7ef40484b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005757617 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.2005757617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.118729923
Short name	T1088
Test name
Test status
Simulation time	946356863 ps
CPU time	6.01 seconds
Started	Dec 24 01:20:49 PM PST 23
Finished	Dec 24 01:20:56 PM PST 23
Peak memory	220132 kb
Host	smart-2d5258c2-2ad0-4168-bb56-e9a91cdcfc75
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118729923 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 40.kmac_test_vectors_kmac_xof.118729923 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.3516134550
Short name	T314
Test name
Test status
Simulation time	193628419721 ps
CPU time	2222.41 seconds
Started	Dec 24 01:20:57 PM PST 23
Finished	Dec 24 01:58:01 PM PST 23
Peak memory	399140 kb
Host	smart-81002960-d4ef-4aab-93bf-0ea23a3efaf7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3516134550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3516134550 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.1896938153
Short name	T420
Test name
Test status
Simulation time	62870067206 ps
CPU time	2130.45 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:56:17 PM PST 23
Peak memory	392496 kb
Host	smart-05651769-29a2-4393-b1bb-2a16b7ac8f22
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1896938153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1896938153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.2263822311
Short name	T774
Test name
Test status
Simulation time	143433071605 ps
CPU time	1938.16 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:53:07 PM PST 23
Peak memory	340872 kb
Host	smart-934eb8a1-caa9-409b-96ab-2cd28f1ad918
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2263822311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2263822311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.1460438000
Short name	T624
Test name
Test status
Simulation time	21941699352 ps
CPU time	1131.06 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:39:39 PM PST 23
Peak memory	304304 kb
Host	smart-b16c66e9-9e34-4407-a9ed-ba4c2f332332
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1460438000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1460438000 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.354502534
Short name	T1041
Test name
Test status
Simulation time	366956611007 ps
CPU time	5845.23 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 02:58:14 PM PST 23
Peak memory	671668 kb
Host	smart-285f56e8-bd93-4be3-b8e2-90915cedbb0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=354502534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.354502534 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.2361670587
Short name	T1128
Test name
Test status
Simulation time	218096990755 ps
CPU time	5140.09 seconds
Started	Dec 24 01:20:59 PM PST 23
Finished	Dec 24 02:46:41 PM PST 23
Peak memory	570552 kb
Host	smart-dc1e9a22-c2ca-4bfd-ac7b-8d75a5ace0ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2361670587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2361670587 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.3121128318
Short name	T328
Test name
Test status
Simulation time	99595620 ps
CPU time	0.85 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:20:49 PM PST 23
Peak memory	219744 kb
Host	smart-b5965f8e-8702-4426-9eef-6e7411e33ffc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121128318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3121128318 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.3910081103
Short name	T678
Test name
Test status
Simulation time	9944337186 ps
CPU time	125.01 seconds
Started	Dec 24 01:20:45 PM PST 23
Finished	Dec 24 01:22:51 PM PST 23
Peak memory	238668 kb
Host	smart-f7c4241e-386a-45dc-9795-bbac809bc198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910081103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3910081103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.3104340664
Short name	T233
Test name
Test status
Simulation time	45641599198 ps
CPU time	1174.83 seconds
Started	Dec 24 01:20:49 PM PST 23
Finished	Dec 24 01:40:25 PM PST 23
Peak memory	241496 kb
Host	smart-61a6e03d-0028-48be-8dfe-f8df13dd11c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104340664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3104340664 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.2147806923
Short name	T1007
Test name
Test status
Simulation time	162623969625 ps
CPU time	221.21 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:24:30 PM PST 23
Peak memory	243700 kb
Host	smart-07e1d5a8-5f3a-4155-a8de-30703f716f29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147806923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2147806923 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.679128966
Short name	T338
Test name
Test status
Simulation time	44398839140 ps
CPU time	305.99 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:25:55 PM PST 23
Peak memory	258404 kb
Host	smart-89cbc897-928f-4d31-b706-6c7a2ed84b09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679128966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.679128966 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.325891100
Short name	T286
Test name
Test status
Simulation time	1453774612 ps
CPU time	4.68 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:20:52 PM PST 23
Peak memory	218788 kb
Host	smart-ab99345c-8de0-4710-9760-09c40c9cfd92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325891100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.325891100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.910136504
Short name	T714
Test name
Test status
Simulation time	40243165 ps
CPU time	1.22 seconds
Started	Dec 24 01:20:59 PM PST 23
Finished	Dec 24 01:21:01 PM PST 23
Peak memory	220176 kb
Host	smart-2e171537-2477-43dc-820d-ec26e90b3c76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910136504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.910136504 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_sideload.2957406171
Short name	T318
Test name
Test status
Simulation time	24510901895 ps
CPU time	216.91 seconds
Started	Dec 24 01:20:58 PM PST 23
Finished	Dec 24 01:24:35 PM PST 23
Peak memory	243380 kb
Host	smart-2a3e2723-e2bd-4a89-9aa1-9fe65f07767a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2957406171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2957406171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.1137549502
Short name	T302
Test name
Test status
Simulation time	18179974566 ps
CPU time	89.88 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:22:17 PM PST 23
Peak memory	226992 kb
Host	smart-c6dfc288-b1e1-4957-9d15-77b02efbbbb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137549502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1137549502 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.1024959860
Short name	T947
Test name
Test status
Simulation time	47883506729 ps
CPU time	1829.4 seconds
Started	Dec 24 01:20:45 PM PST 23
Finished	Dec 24 01:51:16 PM PST 23
Peak memory	391088 kb
Host	smart-995e277b-b4b2-4d58-a330-1a1e0eb6baf6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1024959860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1024959860 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/41.kmac_stress_all_with_rand_reset.3778884377
Short name	T1006
Test name
Test status
Simulation time	41664344840 ps
CPU time	1033.74 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:38:02 PM PST 23
Peak memory	336860 kb
Host	smart-ab14260f-7e99-437d-aa8f-390ecf512bad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3778884377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.3778884377 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.2999493220
Short name	T222
Test name
Test status
Simulation time	188382075 ps
CPU time	5.87 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 01:20:56 PM PST 23
Peak memory	218892 kb
Host	smart-d44c744f-c317-45a1-87e5-90f34cc9ab6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999493220 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.2999493220 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2892881695
Short name	T1140
Test name
Test status
Simulation time	325073646 ps
CPU time	5.41 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:20:52 PM PST 23
Peak memory	218756 kb
Host	smart-f5c03529-c920-4490-9613-4c028dbd070b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892881695 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2892881695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.3145286850
Short name	T659
Test name
Test status
Simulation time	105096531507 ps
CPU time	2362.93 seconds
Started	Dec 24 01:20:59 PM PST 23
Finished	Dec 24 02:00:24 PM PST 23
Peak memory	400104 kb
Host	smart-1af69bc3-c064-4ae6-8615-696671ad2439
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3145286850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3145286850 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.1290215578
Short name	T633
Test name
Test status
Simulation time	95300721048 ps
CPU time	2221.19 seconds
Started	Dec 24 01:20:57 PM PST 23
Finished	Dec 24 01:57:59 PM PST 23
Peak memory	384664 kb
Host	smart-54dbec79-870b-4724-8cd3-a5b981b17fd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1290215578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1290215578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.1991802921
Short name	T326
Test name
Test status
Simulation time	16410682702 ps
CPU time	1499.33 seconds
Started	Dec 24 01:20:49 PM PST 23
Finished	Dec 24 01:45:50 PM PST 23
Peak memory	338436 kb
Host	smart-b4bb0eec-3efd-42b5-8a52-5a1cbf3a9eb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1991802921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1991802921 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.3463196278
Short name	T672
Test name
Test status
Simulation time	51665500841 ps
CPU time	1365.17 seconds
Started	Dec 24 01:20:57 PM PST 23
Finished	Dec 24 01:43:43 PM PST 23
Peak memory	303736 kb
Host	smart-789698d0-f3ee-4952-85e6-76b1fe512ccb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3463196278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3463196278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.1647688871
Short name	T569
Test name
Test status
Simulation time	187745320095 ps
CPU time	5654.91 seconds
Started	Dec 24 01:20:48 PM PST 23
Finished	Dec 24 02:55:06 PM PST 23
Peak memory	654012 kb
Host	smart-9f47ed6d-6b62-4ba3-805c-6d8a26773ece
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1647688871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1647688871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.3191787012
Short name	T835
Test name
Test status
Simulation time	55008242719 ps
CPU time	4412.32 seconds
Started	Dec 24 01:20:59 PM PST 23
Finished	Dec 24 02:34:33 PM PST 23
Peak memory	574756 kb
Host	smart-3e11d1b2-ef4d-45ce-ad2d-03dfbd77ea27
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3191787012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.3191787012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.1532314400
Short name	T520
Test name
Test status
Simulation time	13253204 ps
CPU time	0.84 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	219724 kb
Host	smart-848c1940-48f7-4e6b-ac10-887283993e9d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532314400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1532314400 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.1836675153
Short name	T737
Test name
Test status
Simulation time	6645245966 ps
CPU time	285.09 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:25:57 PM PST 23
Peak memory	249124 kb
Host	smart-103fe763-cf9a-43c9-86d4-b824bb939dde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836675153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1836675153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.1947387439
Short name	T312
Test name
Test status
Simulation time	35102243134 ps
CPU time	680.68 seconds
Started	Dec 24 01:20:49 PM PST 23
Finished	Dec 24 01:32:11 PM PST 23
Peak memory	236888 kb
Host	smart-06cb78f6-f1ae-4995-8447-b8a99492f392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947387439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1947387439 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.3273111940
Short name	T388
Test name
Test status
Simulation time	3621008680 ps
CPU time	74.4 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:22:28 PM PST 23
Peak memory	240128 kb
Host	smart-a98485a4-93e1-400d-8e7f-6a72fd34655f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273111940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3273111940 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_error.3725401044
Short name	T507
Test name
Test status
Simulation time	31086850409 ps
CPU time	192.28 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:24:27 PM PST 23
Peak memory	251568 kb
Host	smart-b3b71cbd-6078-44cc-9964-58b71ece6c6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725401044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3725401044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/42.kmac_key_error.196098468
Short name	T416
Test name
Test status
Simulation time	780906065 ps
CPU time	4.72 seconds
Started	Dec 24 01:21:07 PM PST 23
Finished	Dec 24 01:21:13 PM PST 23
Peak memory	218748 kb
Host	smart-2da9735f-8e29-413f-8105-c381b0d14cfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196098468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.196098468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.1805069217
Short name	T555
Test name
Test status
Simulation time	153173658 ps
CPU time	1.44 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 01:21:11 PM PST 23
Peak memory	218928 kb
Host	smart-ce8576a0-a1ec-4ca9-8fb4-10a36b9e8e61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805069217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1805069217 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.242431390
Short name	T333
Test name
Test status
Simulation time	376633193810 ps
CPU time	3099.05 seconds
Started	Dec 24 01:20:45 PM PST 23
Finished	Dec 24 02:12:26 PM PST 23
Peak memory	489984 kb
Host	smart-f431e89a-af46-456c-af49-8b592374f1cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242431390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an d_output.242431390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.1995108909
Short name	T732
Test name
Test status
Simulation time	22106301227 ps
CPU time	411.2 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:27:40 PM PST 23
Peak memory	254060 kb
Host	smart-6a34ddfe-1c08-40a3-84b7-ffb5baef7a15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995108909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1995108909 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.2179066448
Short name	T303
Test name
Test status
Simulation time	307512242 ps
CPU time	9.95 seconds
Started	Dec 24 01:20:47 PM PST 23
Finished	Dec 24 01:20:57 PM PST 23
Peak memory	224876 kb
Host	smart-fff4c484-efb3-4b13-9edd-371ec7480efd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179066448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2179066448 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.2114634128
Short name	T996
Test name
Test status
Simulation time	24065404961 ps
CPU time	828.62 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:35:01 PM PST 23
Peak memory	276088 kb
Host	smart-8e1335f6-34e4-4917-8ab1-ffad0a04bbba
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2114634128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2114634128 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.383579463
Short name	T570
Test name
Test status
Simulation time	120348725 ps
CPU time	5.99 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:21:09 PM PST 23
Peak memory	220232 kb
Host	smart-f857a249-a97f-4b61-ac79-16e57caf5117
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383579463 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.kmac_test_vectors_kmac.383579463 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2930971881
Short name	T449
Test name
Test status
Simulation time	1155555947 ps
CPU time	6.2 seconds
Started	Dec 24 01:21:01 PM PST 23
Finished	Dec 24 01:21:08 PM PST 23
Peak memory	220388 kb
Host	smart-94929d44-b2be-44d6-8f46-8c8eac5f9288
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930971881 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2930971881 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.2897885887
Short name	T385
Test name
Test status
Simulation time	68543418750 ps
CPU time	2225.91 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:57:53 PM PST 23
Peak memory	401096 kb
Host	smart-18de993e-bb0a-4561-92ab-1f6f4c551f5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2897885887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2897885887 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.1376793369
Short name	T567
Test name
Test status
Simulation time	157815372024 ps
CPU time	2171.28 seconds
Started	Dec 24 01:20:46 PM PST 23
Finished	Dec 24 01:56:58 PM PST 23
Peak memory	383692 kb
Host	smart-0d1eb5a0-c7c8-49d4-8ac5-f7fa69cc8e2f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1376793369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1376793369 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.184298936
Short name	T1142
Test name
Test status
Simulation time	66274270583 ps
CPU time	1536.44 seconds
Started	Dec 24 01:21:03 PM PST 23
Finished	Dec 24 01:46:40 PM PST 23
Peak memory	337144 kb
Host	smart-af47664b-cb20-4d02-9ea7-6adf1823e68f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=184298936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.184298936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.3250670893
Short name	T798
Test name
Test status
Simulation time	79263695535 ps
CPU time	1338.72 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 01:43:30 PM PST 23
Peak memory	293076 kb
Host	smart-e696fa2b-c6c6-4e9d-b158-eaa8cca769b6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3250670893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3250670893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.1815085464
Short name	T651
Test name
Test status
Simulation time	954148804295 ps
CPU time	5888.51 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 02:59:12 PM PST 23
Peak memory	670232 kb
Host	smart-eef2b17e-aea7-4e8d-a752-ccd81055c167
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1815085464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.1815085464 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.2977870764
Short name	T1074
Test name
Test status
Simulation time	2503448503016 ps
CPU time	5408.24 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 02:51:20 PM PST 23
Peak memory	572360 kb
Host	smart-70c058a4-82fa-477a-94b6-6d10a11294ff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2977870764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2977870764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.2131895426
Short name	T94
Test name
Test status
Simulation time	56300916 ps
CPU time	0.86 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:21:16 PM PST 23
Peak memory	218496 kb
Host	smart-3a9534f8-45a7-4454-ae2c-e07970895c08
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131895426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2131895426 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.1878386830
Short name	T913
Test name
Test status
Simulation time	863795820 ps
CPU time	22.56 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:21:36 PM PST 23
Peak memory	224188 kb
Host	smart-b1df379d-3889-4c7d-98ac-628248a9fba2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878386830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1878386830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.2237616699
Short name	T534
Test name
Test status
Simulation time	1193366142 ps
CPU time	112.69 seconds
Started	Dec 24 01:21:00 PM PST 23
Finished	Dec 24 01:22:54 PM PST 23
Peak memory	226724 kb
Host	smart-ac212406-7acd-454f-aaf9-d097997e641d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237616699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.2237616699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.792717193
Short name	T733
Test name
Test status
Simulation time	3110686753 ps
CPU time	18.56 seconds
Started	Dec 24 01:21:00 PM PST 23
Finished	Dec 24 01:21:20 PM PST 23
Peak memory	227820 kb
Host	smart-06a5f50f-ffee-440b-a15e-ae232f9ce220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792717193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.792717193 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.2394760236
Short name	T447
Test name
Test status
Simulation time	13780627104 ps
CPU time	337.26 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:26:49 PM PST 23
Peak memory	259736 kb
Host	smart-52229db8-b987-4578-bb44-37963578cc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394760236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2394760236 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.342300073
Short name	T879
Test name
Test status
Simulation time	1830466407 ps
CPU time	3.44 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	218716 kb
Host	smart-72e3c536-0fa1-4a60-810e-0f8c2f7906a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342300073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.342300073 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.2116245490
Short name	T389
Test name
Test status
Simulation time	89431723 ps
CPU time	1.34 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:21:04 PM PST 23
Peak memory	219864 kb
Host	smart-b89437cb-9744-44ae-b36e-bdf6c7c1e1b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116245490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2116245490 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.2570951155
Short name	T928
Test name
Test status
Simulation time	440413491792 ps
CPU time	3417.63 seconds
Started	Dec 24 01:21:03 PM PST 23
Finished	Dec 24 02:18:02 PM PST 23
Peak memory	482496 kb
Host	smart-e7aab0a9-0d2b-4179-b1bf-29e51c5f43a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570951155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.2570951155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.1611100091
Short name	T483
Test name
Test status
Simulation time	2000553877 ps
CPU time	70.67 seconds
Started	Dec 24 01:21:01 PM PST 23
Finished	Dec 24 01:22:13 PM PST 23
Peak memory	230332 kb
Host	smart-57a7c632-107b-464d-bc7e-f03f918833cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611100091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1611100091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.319980867
Short name	T245
Test name
Test status
Simulation time	1018498371 ps
CPU time	43.9 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:21:47 PM PST 23
Peak memory	226912 kb
Host	smart-9cfad065-74fb-4d91-a0ae-aec74d0ab3d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319980867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.319980867 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.390472433
Short name	T885
Test name
Test status
Simulation time	61107161801 ps
CPU time	2252.63 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:58:47 PM PST 23
Peak memory	423464 kb
Host	smart-b3d4b63c-3835-4cba-94af-4e39fa04978c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=390472433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.390472433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.2200206093
Short name	T1109
Test name
Test status
Simulation time	209500645 ps
CPU time	6.21 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:19 PM PST 23
Peak memory	220244 kb
Host	smart-d5ab3221-5264-4193-94f9-f060733d0c22
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200206093 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.2200206093 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1953519171
Short name	T687
Test name
Test status
Simulation time	458725155 ps
CPU time	6.05 seconds
Started	Dec 24 01:21:03 PM PST 23
Finished	Dec 24 01:21:10 PM PST 23
Peak memory	218856 kb
Host	smart-8f4452e4-814f-4484-ab14-adf3c63014bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953519171 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1953519171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.28735280
Short name	T392
Test name
Test status
Simulation time	351655402709 ps
CPU time	2470.74 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 02:02:22 PM PST 23
Peak memory	403248 kb
Host	smart-8a875d58-6402-4b0b-9b09-3f633344d82e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=28735280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.28735280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.2171482528
Short name	T839
Test name
Test status
Simulation time	20270016545 ps
CPU time	1925.96 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 01:53:16 PM PST 23
Peak memory	389996 kb
Host	smart-68cf19f7-9901-4fd0-94f5-210b84e6065a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2171482528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2171482528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.2142727695
Short name	T940
Test name
Test status
Simulation time	292006746774 ps
CPU time	1937.42 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:53:33 PM PST 23
Peak memory	341016 kb
Host	smart-5cd21f42-eadc-4cf7-b001-93e8117366cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2142727695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2142727695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.1409395331
Short name	T915
Test name
Test status
Simulation time	10598980821 ps
CPU time	1195.48 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:40:59 PM PST 23
Peak memory	303192 kb
Host	smart-00db0ce5-f105-4c14-9e99-06d08986a03f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1409395331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1409395331 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.1784899293
Short name	T231
Test name
Test status
Simulation time	87385182792 ps
CPU time	4965.76 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 02:44:00 PM PST 23
Peak memory	642972 kb
Host	smart-ae7fd3bd-5fbe-4293-84fe-96846f7a3e07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1784899293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1784899293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.1533152357
Short name	T284
Test name
Test status
Simulation time	206719615336 ps
CPU time	4979.05 seconds
Started	Dec 24 01:21:04 PM PST 23
Finished	Dec 24 02:44:04 PM PST 23
Peak memory	579380 kb
Host	smart-b2424788-d514-4a9b-ab98-43981ae3f687
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1533152357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1533152357 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.2789378055
Short name	T343
Test name
Test status
Simulation time	173047077 ps
CPU time	0.87 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:21:15 PM PST 23
Peak memory	219700 kb
Host	smart-8bd596bb-4f53-4cec-a983-3609f080843a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789378055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2789378055 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.3155086907
Short name	T42
Test name
Test status
Simulation time	41460127836 ps
CPU time	252.57 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:25:26 PM PST 23
Peak memory	247452 kb
Host	smart-ac5e1df1-a982-42b1-b78c-44021cdfdb40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155086907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3155086907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.1099880807
Short name	T834
Test name
Test status
Simulation time	20671098945 ps
CPU time	971.19 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:37:27 PM PST 23
Peak memory	239872 kb
Host	smart-cbc93942-ad8b-4ca6-b1a6-c0c8891fd409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099880807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1099880807 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.1658716208
Short name	T137
Test name
Test status
Simulation time	7541952134 ps
CPU time	347.17 seconds
Started	Dec 24 01:21:00 PM PST 23
Finished	Dec 24 01:26:49 PM PST 23
Peak memory	252480 kb
Host	smart-f9dd9356-995b-4ad1-87f9-74799998398a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658716208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1658716208 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.3462076901
Short name	T24
Test name
Test status
Simulation time	49959189599 ps
CPU time	336.92 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:26:52 PM PST 23
Peak memory	255036 kb
Host	smart-79db9b58-813e-461c-bfbc-6b495efb1aa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462076901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3462076901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.259033884
Short name	T631
Test name
Test status
Simulation time	3798540836 ps
CPU time	5.64 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	218560 kb
Host	smart-7e3c8db7-6165-43b5-83cc-2838cf7d2bab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259033884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.259033884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.2423165890
Short name	T545
Test name
Test status
Simulation time	96297105 ps
CPU time	1.19 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:21:18 PM PST 23
Peak memory	218748 kb
Host	smart-92d30737-8f58-4d91-bb41-ce318018011d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423165890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2423165890 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.1791535249
Short name	T251
Test name
Test status
Simulation time	205600496187 ps
CPU time	1794.05 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:50:57 PM PST 23
Peak memory	386832 kb
Host	smart-e5cf3722-2702-48f9-b17d-a7a0af1c351c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791535249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.1791535249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.179215689
Short name	T936
Test name
Test status
Simulation time	7208207158 ps
CPU time	123.84 seconds
Started	Dec 24 01:21:01 PM PST 23
Finished	Dec 24 01:23:06 PM PST 23
Peak memory	235300 kb
Host	smart-8b2a90a1-c618-470f-9fb4-500a221328d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179215689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.179215689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.996418874
Short name	T616
Test name
Test status
Simulation time	859396340 ps
CPU time	22.59 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:35 PM PST 23
Peak memory	226848 kb
Host	smart-02cc5cee-841a-4935-b71e-16da8d5205a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996418874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.996418874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.4277443727
Short name	T20
Test name
Test status
Simulation time	1401164887 ps
CPU time	24.27 seconds
Started	Dec 24 01:21:03 PM PST 23
Finished	Dec 24 01:21:28 PM PST 23
Peak memory	235116 kb
Host	smart-088124a0-17ac-4c90-a12c-cd94433d9cfb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4277443727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4277443727 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.731430069
Short name	T461
Test name
Test status
Simulation time	443023243 ps
CPU time	6.35 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:21:20 PM PST 23
Peak memory	218684 kb
Host	smart-02354237-90f0-46ee-ba18-fa5e8321a243
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731430069 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.kmac_test_vectors_kmac.731430069 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.792420377
Short name	T497
Test name
Test status
Simulation time	408795661 ps
CPU time	6.3 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:18 PM PST 23
Peak memory	218684 kb
Host	smart-f535824b-6078-40c6-8433-70872a72efdd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792420377 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 44.kmac_test_vectors_kmac_xof.792420377 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.1956864617
Short name	T607
Test name
Test status
Simulation time	138536732037 ps
CPU time	2249.34 seconds
Started	Dec 24 01:21:02 PM PST 23
Finished	Dec 24 01:58:33 PM PST 23
Peak memory	403204 kb
Host	smart-d3367aaa-b3c1-4891-8fe5-26268c6d9c62
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1956864617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.1956864617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.2798691433
Short name	T1144
Test name
Test status
Simulation time	338767731167 ps
CPU time	2330.16 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 02:00:02 PM PST 23
Peak memory	383072 kb
Host	smart-efd86f00-ad97-4dfb-8b78-5be2bcd5784f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2798691433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2798691433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.2387622221
Short name	T267
Test name
Test status
Simulation time	15421661217 ps
CPU time	1609.92 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:48:04 PM PST 23
Peak memory	343036 kb
Host	smart-0054c445-4265-4c1c-9f72-4b8a1b327b5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2387622221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2387622221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.314568455
Short name	T563
Test name
Test status
Simulation time	200657170928 ps
CPU time	1336.89 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:43:30 PM PST 23
Peak memory	299632 kb
Host	smart-1be8b9ca-1e8e-4319-83d8-72f5e9c11be0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=314568455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.314568455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.4155017017
Short name	T430
Test name
Test status
Simulation time	516449704204 ps
CPU time	6040.49 seconds
Started	Dec 24 01:21:00 PM PST 23
Finished	Dec 24 03:01:43 PM PST 23
Peak memory	653968 kb
Host	smart-443fdf63-c968-4c12-b74b-e21a14112122
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4155017017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.4155017017 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.1583595074
Short name	T621
Test name
Test status
Simulation time	158778258880 ps
CPU time	4801.85 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 02:41:13 PM PST 23
Peak memory	576080 kb
Host	smart-c145d67b-26d7-473f-90d0-d9bdcbeacaaa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1583595074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1583595074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.344464807
Short name	T622
Test name
Test status
Simulation time	18452771 ps
CPU time	0.88 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:21:16 PM PST 23
Peak memory	218676 kb
Host	smart-2947a882-88e7-47de-aab6-fb121f419660
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344464807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.344464807 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.944720906
Short name	T920
Test name
Test status
Simulation time	17190521004 ps
CPU time	366.19 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 01:27:16 PM PST 23
Peak memory	251080 kb
Host	smart-574f7f87-da43-41ca-932d-1f5197cc9836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944720906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.944720906 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.3920106946
Short name	T611
Test name
Test status
Simulation time	11656686186 ps
CPU time	1094.78 seconds
Started	Dec 24 01:21:00 PM PST 23
Finished	Dec 24 01:39:16 PM PST 23
Peak memory	243384 kb
Host	smart-b2bf6867-8a9f-409f-a31e-920ff5be4ba6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920106946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3920106946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.1027900273
Short name	T564
Test name
Test status
Simulation time	17911866195 ps
CPU time	404.96 seconds
Started	Dec 24 01:21:08 PM PST 23
Finished	Dec 24 01:27:54 PM PST 23
Peak memory	255388 kb
Host	smart-da5a585e-417c-4ef3-a4cc-25a26027885f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027900273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1027900273 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.4018179532
Short name	T796
Test name
Test status
Simulation time	3681559595 ps
CPU time	17.38 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 01:21:28 PM PST 23
Peak memory	227016 kb
Host	smart-1de47527-75d4-41d0-92f0-543a88701aa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018179532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.4018179532 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.1868886109
Short name	T886
Test name
Test status
Simulation time	3711354757 ps
CPU time	6.97 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:21:25 PM PST 23
Peak memory	218704 kb
Host	smart-a3e7d30a-fc6a-459d-bd2d-53183a35b128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868886109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1868886109 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.3513019827
Short name	T561
Test name
Test status
Simulation time	79913154 ps
CPU time	1.3 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:13 PM PST 23
Peak memory	219820 kb
Host	smart-fb75d41d-d80a-4227-885f-b60ca3fd3b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513019827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3513019827 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.4086329653
Short name	T543
Test name
Test status
Simulation time	32370064658 ps
CPU time	2899.79 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 02:09:34 PM PST 23
Peak memory	469920 kb
Host	smart-cac9f32b-7c0c-45f3-bbf6-beb2338bdc18
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086329653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.4086329653 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.1694872072
Short name	T575
Test name
Test status
Simulation time	80229844773 ps
CPU time	278.52 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:25:54 PM PST 23
Peak memory	244980 kb
Host	smart-d8d8bff1-c8d2-49da-9081-c0ffcd7499af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694872072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1694872072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.1983142954
Short name	T708
Test name
Test status
Simulation time	33006125339 ps
CPU time	64.52 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:22:19 PM PST 23
Peak memory	224536 kb
Host	smart-52c09c0e-e9b0-44b9-9f9c-4841306ea0a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983142954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1983142954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.957623250
Short name	T506
Test name
Test status
Simulation time	256286086349 ps
CPU time	2212.99 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:58:10 PM PST 23
Peak memory	423672 kb
Host	smart-f5200bc9-8434-420b-a524-5c7deb2a9070
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=957623250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.957623250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.2612337223
Short name	T399
Test name
Test status
Simulation time	234900787130 ps
CPU time	3751.5 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 02:23:47 PM PST 23
Peak memory	423948 kb
Host	smart-f856256f-27c0-437f-9adb-ffd9fe9c8d28
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2612337223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.2612337223 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.1135266729
Short name	T712
Test name
Test status
Simulation time	101253411 ps
CPU time	5.44 seconds
Started	Dec 24 01:21:08 PM PST 23
Finished	Dec 24 01:21:14 PM PST 23
Peak memory	218840 kb
Host	smart-258661c3-2e11-481e-90fd-1a13defa2fe7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135266729 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.1135266729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3497765244
Short name	T966
Test name
Test status
Simulation time	216751226 ps
CPU time	6.46 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:21:22 PM PST 23
Peak memory	218804 kb
Host	smart-8f6a2b63-aa9c-4114-ab21-38e03ffd5bd9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497765244 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3497765244 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.869652719
Short name	T335
Test name
Test status
Simulation time	55359952979 ps
CPU time	2104.03 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:56:19 PM PST 23
Peak memory	399008 kb
Host	smart-706a7ecd-29a4-48f6-9ea6-ba0f5dcc70c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=869652719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.869652719 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.2080724872
Short name	T647
Test name
Test status
Simulation time	99271890444 ps
CPU time	2395.67 seconds
Started	Dec 24 01:21:08 PM PST 23
Finished	Dec 24 02:01:04 PM PST 23
Peak memory	388104 kb
Host	smart-bd5c4d83-8d30-435f-a19d-d48144ad2ad3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2080724872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2080724872 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.3708000586
Short name	T290
Test name
Test status
Simulation time	598655234309 ps
CPU time	1987.23 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:54:19 PM PST 23
Peak memory	346964 kb
Host	smart-b9c7957f-7aa4-434d-9f41-87aa3f607f0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3708000586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.3708000586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.2310181839
Short name	T413
Test name
Test status
Simulation time	51595138949 ps
CPU time	1234.96 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:41:48 PM PST 23
Peak memory	306880 kb
Host	smart-85cc4f9c-1de0-435a-9887-13ca88af3b5c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2310181839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.2310181839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.1635328619
Short name	T826
Test name
Test status
Simulation time	737531213650 ps
CPU time	5635.32 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 02:55:11 PM PST 23
Peak memory	657740 kb
Host	smart-2f7d5440-1eb8-4138-a34b-dbcda477459b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1635328619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1635328619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.2883173375
Short name	T451
Test name
Test status
Simulation time	370790899848 ps
CPU time	5019.89 seconds
Started	Dec 24 01:21:09 PM PST 23
Finished	Dec 24 02:44:51 PM PST 23
Peak memory	581996 kb
Host	smart-e128535b-7bfa-4170-a5e4-1a053c24cd52
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2883173375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.2883173375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.3899101670
Short name	T932
Test name
Test status
Simulation time	15703867 ps
CPU time	0.84 seconds
Started	Dec 24 01:21:08 PM PST 23
Finished	Dec 24 01:21:10 PM PST 23
Peak memory	219768 kb
Host	smart-3bed9a7f-7d4f-4b17-b691-7363b65c5121
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899101670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3899101670 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.1661507651
Short name	T783
Test name
Test status
Simulation time	25390401526 ps
CPU time	68.32 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:22:25 PM PST 23
Peak memory	230984 kb
Host	smart-1f59f874-61ff-4040-b183-c3ec4fe142a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661507651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1661507651 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.1478529985
Short name	T390
Test name
Test status
Simulation time	2496178536 ps
CPU time	55.84 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:22:07 PM PST 23
Peak memory	232408 kb
Host	smart-7e07bdfb-a16e-43ae-9dcd-f5914daa72d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478529985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1478529985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.1641767778
Short name	T140
Test name
Test status
Simulation time	20434462476 ps
CPU time	315.51 seconds
Started	Dec 24 01:21:11 PM PST 23
Finished	Dec 24 01:26:29 PM PST 23
Peak memory	249272 kb
Host	smart-fe8eb8fa-a035-44de-a0c0-21213dea3821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641767778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1641767778 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.4261401636
Short name	T458
Test name
Test status
Simulation time	9457612746 ps
CPU time	81.1 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:22:37 PM PST 23
Peak memory	241708 kb
Host	smart-6d9bb843-766a-4852-8187-f5a2da22dc83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261401636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4261401636 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.2754188496
Short name	T1110
Test name
Test status
Simulation time	208216288 ps
CPU time	2.24 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:14 PM PST 23
Peak memory	218616 kb
Host	smart-9fcfdbdd-e43f-438e-ad1b-ca134da23f8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754188496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2754188496 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.1413730885
Short name	T432
Test name
Test status
Simulation time	174954122 ps
CPU time	1.3 seconds
Started	Dec 24 01:21:14 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	218744 kb
Host	smart-01b03772-8f94-4515-a14d-d3bd0b651626
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413730885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1413730885 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.129526215
Short name	T324
Test name
Test status
Simulation time	59624029089 ps
CPU time	880.76 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:35:58 PM PST 23
Peak memory	296168 kb
Host	smart-85d181eb-bc8c-451b-8939-5b0050b42aae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129526215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an d_output.129526215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.3609239144
Short name	T519
Test name
Test status
Simulation time	97235181148 ps
CPU time	469.9 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:29:04 PM PST 23
Peak memory	257540 kb
Host	smart-a9c1ec31-71b4-4019-b7fe-d025cabf2415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609239144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3609239144 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.1082626708
Short name	T192
Test name
Test status
Simulation time	4515489564 ps
CPU time	42.11 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:21:59 PM PST 23
Peak memory	219340 kb
Host	smart-dadca5a6-8819-421b-bf2e-72da6ef873c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082626708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1082626708 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.3381073009
Short name	T484
Test name
Test status
Simulation time	48813498473 ps
CPU time	680.3 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:32:36 PM PST 23
Peak memory	291040 kb
Host	smart-71f81f89-9d78-4d8e-89c5-bf90646c1955
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3381073009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3381073009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.97179507
Short name	T884
Test name
Test status
Simulation time	234342599 ps
CPU time	6.19 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 01:21:21 PM PST 23
Peak memory	218796 kb
Host	smart-55012488-e8ea-46a5-a273-503bb4d3c9cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97179507 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 46.kmac_test_vectors_kmac.97179507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2938972258
Short name	T576
Test name
Test status
Simulation time	257067821 ps
CPU time	6.09 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:21:17 PM PST 23
Peak memory	218740 kb
Host	smart-3b5592c6-77b9-4e8d-86fa-27fa13c8c4c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938972258 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2938972258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.3357642605
Short name	T526
Test name
Test status
Simulation time	186514906901 ps
CPU time	2125.18 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:56:43 PM PST 23
Peak memory	404212 kb
Host	smart-b8d737fd-a53c-4b30-be8f-9b683b3d51b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3357642605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3357642605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.3997105283
Short name	T509
Test name
Test status
Simulation time	40730507850 ps
CPU time	2016.37 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:54:53 PM PST 23
Peak memory	379736 kb
Host	smart-564ec49f-5942-4536-bcba-fc0b3b058be0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3997105283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3997105283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.2852901725
Short name	T186
Test name
Test status
Simulation time	50290375784 ps
CPU time	1751.63 seconds
Started	Dec 24 01:21:12 PM PST 23
Finished	Dec 24 01:50:26 PM PST 23
Peak memory	346332 kb
Host	smart-688f44b5-15b6-47a9-9862-4493d5f8127a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2852901725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2852901725 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.3367348246
Short name	T790
Test name
Test status
Simulation time	191698365829 ps
CPU time	1334.83 seconds
Started	Dec 24 01:21:10 PM PST 23
Finished	Dec 24 01:43:27 PM PST 23
Peak memory	297380 kb
Host	smart-095a120b-5906-411c-a127-ad4261b08375
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3367348246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.3367348246 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.2741170316
Short name	T349
Test name
Test status
Simulation time	243434465792 ps
CPU time	5042.48 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 02:45:18 PM PST 23
Peak memory	651512 kb
Host	smart-237a52fb-1cf7-4fbb-897e-ce69143c6510
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2741170316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2741170316 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.1953999594
Short name	T558
Test name
Test status
Simulation time	112558840480 ps
CPU time	4406.92 seconds
Started	Dec 24 01:21:13 PM PST 23
Finished	Dec 24 02:34:43 PM PST 23
Peak memory	570284 kb
Host	smart-a24fe4cf-df9f-4e02-a0bb-80afaf94efee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1953999594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1953999594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.1236975737
Short name	T974
Test name
Test status
Simulation time	119980813 ps
CPU time	0.83 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 01:21:21 PM PST 23
Peak memory	218584 kb
Host	smart-608ee5ba-da68-4750-9354-444b3521c88a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236975737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1236975737 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.2311376588
Short name	T283
Test name
Test status
Simulation time	6117244986 ps
CPU time	172.2 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:24:15 PM PST 23
Peak memory	240728 kb
Host	smart-fc6fb75d-8fae-48b7-bb32-bd59f0a50ecd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311376588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2311376588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.3235187347
Short name	T653
Test name
Test status
Simulation time	170855326798 ps
CPU time	532.6 seconds
Started	Dec 24 01:21:16 PM PST 23
Finished	Dec 24 01:30:11 PM PST 23
Peak memory	236388 kb
Host	smart-758564d2-7937-4fb4-b078-6e0d5baec535
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235187347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3235187347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.1680782126
Short name	T215
Test name
Test status
Simulation time	4974769387 ps
CPU time	46.32 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:22:11 PM PST 23
Peak memory	229200 kb
Host	smart-4644cce6-ce6c-4c08-83e3-6c4651ad23fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680782126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1680782126 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.372521249
Short name	T812
Test name
Test status
Simulation time	25274897226 ps
CPU time	495.72 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 01:29:35 PM PST 23
Peak memory	270988 kb
Host	smart-c76ae5c2-dcc8-4544-8831-0a054bd3bed6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372521249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.372521249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.2636572175
Short name	T486
Test name
Test status
Simulation time	399234330 ps
CPU time	1.25 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:21:27 PM PST 23
Peak memory	218584 kb
Host	smart-97d7a8ff-b024-4749-a244-5340cc023ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636572175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2636572175 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.2751272587
Short name	T1079
Test name
Test status
Simulation time	261049602 ps
CPU time	1.42 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:21:24 PM PST 23
Peak memory	219960 kb
Host	smart-452b2636-8c37-4b79-b510-fe4b5f54f2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751272587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2751272587 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.277047955
Short name	T547
Test name
Test status
Simulation time	162962774977 ps
CPU time	1140.03 seconds
Started	Dec 24 01:21:19 PM PST 23
Finished	Dec 24 01:40:20 PM PST 23
Peak memory	304632 kb
Host	smart-2163f0f7-2805-445a-84f3-ea7457c1b5fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277047955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an d_output.277047955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.1423870153
Short name	T619
Test name
Test status
Simulation time	14588980235 ps
CPU time	364.49 seconds
Started	Dec 24 01:21:19 PM PST 23
Finished	Dec 24 01:27:24 PM PST 23
Peak memory	249200 kb
Host	smart-e83888b1-371e-4ebb-b55c-7fa230e06421
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423870153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1423870153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.622377450
Short name	T181
Test name
Test status
Simulation time	2235304484 ps
CPU time	34.04 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:21:51 PM PST 23
Peak memory	226900 kb
Host	smart-9d1f02a2-85e0-400f-a22d-831054775ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622377450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.622377450 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.970511715
Short name	T786
Test name
Test status
Simulation time	114659012268 ps
CPU time	1063.33 seconds
Started	Dec 24 01:21:15 PM PST 23
Finished	Dec 24 01:39:01 PM PST 23
Peak memory	329284 kb
Host	smart-a1a680b2-3072-4680-b7e3-8e26323b1773
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=970511715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.970511715 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.2287737590
Short name	T693
Test name
Test status
Simulation time	308878504 ps
CPU time	5.73 seconds
Started	Dec 24 01:21:19 PM PST 23
Finished	Dec 24 01:21:26 PM PST 23
Peak memory	218796 kb
Host	smart-2503b433-6eb2-40d4-baf3-96836ee55291
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287737590 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.2287737590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.1965038615
Short name	T963
Test name
Test status
Simulation time	590326732 ps
CPU time	6.6 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:21:29 PM PST 23
Peak memory	218808 kb
Host	smart-96f02816-b186-402d-9bd2-e4d79acefadc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965038615 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.1965038615 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.1173859677
Short name	T808
Test name
Test status
Simulation time	120576125459 ps
CPU time	2011.78 seconds
Started	Dec 24 01:21:17 PM PST 23
Finished	Dec 24 01:54:51 PM PST 23
Peak memory	398536 kb
Host	smart-275be85b-b6b8-4bba-a853-4aab8f728499
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1173859677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1173859677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.3554664565
Short name	T1036
Test name
Test status
Simulation time	63639628656 ps
CPU time	2132.42 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 01:56:52 PM PST 23
Peak memory	395424 kb
Host	smart-c742041e-f4db-401f-9840-d5c90ad8503f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3554664565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3554664565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.2607244932
Short name	T1134
Test name
Test status
Simulation time	48355826749 ps
CPU time	1601.59 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 01:48:02 PM PST 23
Peak memory	339632 kb
Host	smart-d8cc4eef-a88a-4b91-901b-2f7b74834025
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2607244932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2607244932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.600036282
Short name	T726
Test name
Test status
Simulation time	34557898466 ps
CPU time	1340.56 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:43:45 PM PST 23
Peak memory	303568 kb
Host	smart-5be68f63-d0ec-494c-9ed1-948b0f4d7021
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=600036282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.600036282 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.1922993362
Short name	T269
Test name
Test status
Simulation time	178361908992 ps
CPU time	5505.61 seconds
Started	Dec 24 01:21:16 PM PST 23
Finished	Dec 24 02:53:04 PM PST 23
Peak memory	655164 kb
Host	smart-43148c9c-4e25-4e76-b2f5-d27afbb7aa8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1922993362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.1922993362 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.3713414510
Short name	T368
Test name
Test status
Simulation time	122947669432 ps
CPU time	4366.6 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 02:34:09 PM PST 23
Peak memory	573056 kb
Host	smart-13fbe91d-4bbf-4acb-88d4-579105f5cadc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3713414510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3713414510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.3248458474
Short name	T364
Test name
Test status
Simulation time	16322021 ps
CPU time	0.86 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:21:25 PM PST 23
Peak memory	218540 kb
Host	smart-6d7170d7-5777-47c5-8011-d22c791f5b98
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248458474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3248458474 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.3465030376
Short name	T801
Test name
Test status
Simulation time	11106835764 ps
CPU time	161.07 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:24:03 PM PST 23
Peak memory	239096 kb
Host	smart-2c302c2e-7f6a-4d6c-bf8d-e82a96de2187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465030376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3465030376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.2924353275
Short name	T263
Test name
Test status
Simulation time	28137028929 ps
CPU time	677.74 seconds
Started	Dec 24 01:21:16 PM PST 23
Finished	Dec 24 01:32:36 PM PST 23
Peak memory	236840 kb
Host	smart-c8c707b7-5bec-4e4e-a8c6-bfe638572a0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924353275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2924353275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.1775819332
Short name	T917
Test name
Test status
Simulation time	16101330043 ps
CPU time	347.43 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 01:27:07 PM PST 23
Peak memory	252228 kb
Host	smart-74833699-61bf-4673-bc7c-67369ede33b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775819332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1775819332 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.1749403694
Short name	T933
Test name
Test status
Simulation time	31136170851 ps
CPU time	476.62 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:29:19 PM PST 23
Peak memory	259748 kb
Host	smart-c5ab1d5e-ec02-4ad3-a25b-721bb321d0c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749403694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1749403694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.739984901
Short name	T252
Test name
Test status
Simulation time	482386059 ps
CPU time	1.5 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:21:27 PM PST 23
Peak memory	218516 kb
Host	smart-7475cbeb-02c1-400c-ba35-6f8aa7aa275a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739984901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.739984901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.1365636594
Short name	T212
Test name
Test status
Simulation time	87131082 ps
CPU time	1.4 seconds
Started	Dec 24 01:21:30 PM PST 23
Finished	Dec 24 01:21:33 PM PST 23
Peak memory	219784 kb
Host	smart-395b614b-dc3c-40be-96d6-ecabda7b716f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365636594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1365636594 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.3317697783
Short name	T223
Test name
Test status
Simulation time	12752187925 ps
CPU time	1319.74 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 01:43:19 PM PST 23
Peak memory	341944 kb
Host	smart-fca3eedd-3dba-4bd4-8c3b-fa24de6d0d3d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317697783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.3317697783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.1115160418
Short name	T942
Test name
Test status
Simulation time	22736520822 ps
CPU time	352.31 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:27:15 PM PST 23
Peak memory	246504 kb
Host	smart-0e1cc771-6e06-4601-8c90-333b37508045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115160418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1115160418 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.3053978713
Short name	T532
Test name
Test status
Simulation time	14268090360 ps
CPU time	67.86 seconds
Started	Dec 24 01:21:16 PM PST 23
Finished	Dec 24 01:22:26 PM PST 23
Peak memory	226980 kb
Host	smart-864055e6-6e94-4360-afc1-d308c1d3f509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053978713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3053978713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.3224866361
Short name	T957
Test name
Test status
Simulation time	5307320679 ps
CPU time	34.05 seconds
Started	Dec 24 01:21:26 PM PST 23
Finished	Dec 24 01:22:01 PM PST 23
Peak memory	236536 kb
Host	smart-0bffffa0-6ca8-4c4a-9e7d-d86dc9303797
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3224866361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3224866361 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_stress_all_with_rand_reset.2089461476
Short name	T802
Test name
Test status
Simulation time	89944499806 ps
CPU time	748.16 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:33:52 PM PST 23
Peak memory	272824 kb
Host	smart-e2c2b643-07a5-40c7-9d05-b1693e9ba7a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2089461476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.2089461476 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.4105447143
Short name	T951
Test name
Test status
Simulation time	586745282 ps
CPU time	6.67 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:21:29 PM PST 23
Peak memory	220060 kb
Host	smart-fb817474-a513-43ab-a6d8-6b09d5a5559b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105447143 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.4105447143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1950736202
Short name	T243
Test name
Test status
Simulation time	750561132 ps
CPU time	7.05 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 01:21:28 PM PST 23
Peak memory	218744 kb
Host	smart-bfdc90f3-74b2-4997-8328-bc5eb370e8bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950736202 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1950736202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.2993964175
Short name	T738
Test name
Test status
Simulation time	378086885013 ps
CPU time	2405.81 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 02:01:26 PM PST 23
Peak memory	389012 kb
Host	smart-6132b4da-d83d-42e0-87d1-f54df7dc8df6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2993964175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2993964175 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.2718887777
Short name	T613
Test name
Test status
Simulation time	375566618201 ps
CPU time	2303.25 seconds
Started	Dec 24 01:21:18 PM PST 23
Finished	Dec 24 01:59:43 PM PST 23
Peak memory	396956 kb
Host	smart-e1950854-6701-443e-b508-c4cc754e44ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2718887777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2718887777 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.3017137513
Short name	T755
Test name
Test status
Simulation time	63943455143 ps
CPU time	1732.23 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:50:15 PM PST 23
Peak memory	341776 kb
Host	smart-c2fe50cd-9d11-4a4d-a3f2-247a9a9a033d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3017137513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3017137513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.3781248525
Short name	T968
Test name
Test status
Simulation time	49506939329 ps
CPU time	1314.54 seconds
Started	Dec 24 01:21:16 PM PST 23
Finished	Dec 24 01:43:14 PM PST 23
Peak memory	300080 kb
Host	smart-1b8f5c77-8b9e-4bf1-b503-615dbbd18423
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3781248525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3781248525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.3815074893
Short name	T353
Test name
Test status
Simulation time	781775540355 ps
CPU time	5019.97 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 02:45:02 PM PST 23
Peak memory	672952 kb
Host	smart-bf186a6d-3afb-46f2-8a76-a1f5ed205d29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3815074893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3815074893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.3956333963
Short name	T999
Test name
Test status
Simulation time	403711935800 ps
CPU time	4435.2 seconds
Started	Dec 24 01:21:20 PM PST 23
Finished	Dec 24 02:35:17 PM PST 23
Peak memory	574640 kb
Host	smart-e43ba137-e88f-42eb-bfdd-d765c7eda4dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3956333963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3956333963 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.2126540459
Short name	T511
Test name
Test status
Simulation time	14970549 ps
CPU time	0.84 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:21:24 PM PST 23
Peak memory	218680 kb
Host	smart-5fa7c6cc-bf4e-42f9-a5fb-75cdc1acdc4f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126540459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2126540459 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.1831579985
Short name	T219
Test name
Test status
Simulation time	8942635019 ps
CPU time	285.48 seconds
Started	Dec 24 01:21:31 PM PST 23
Finished	Dec 24 01:26:17 PM PST 23
Peak memory	248320 kb
Host	smart-065f7fe8-0da5-4a87-a8d0-d2439c42d967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831579985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1831579985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.1452449765
Short name	T533
Test name
Test status
Simulation time	5258483494 ps
CPU time	168.47 seconds
Started	Dec 24 01:21:29 PM PST 23
Finished	Dec 24 01:24:19 PM PST 23
Peak memory	228484 kb
Host	smart-e6b6a647-dc4b-4954-ad0a-6c5193b78651
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452449765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1452449765 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.2356998698
Short name	T754
Test name
Test status
Simulation time	41073877192 ps
CPU time	211.79 seconds
Started	Dec 24 01:21:30 PM PST 23
Finished	Dec 24 01:25:03 PM PST 23
Peak memory	241320 kb
Host	smart-9cd25aaa-1ba7-4426-8571-aaebf0b4908f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356998698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2356998698 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.1636279363
Short name	T1136
Test name
Test status
Simulation time	9701579760 ps
CPU time	163.74 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:24:09 PM PST 23
Peak memory	243316 kb
Host	smart-8a41aab0-0522-4814-8bc3-309ecc06efb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636279363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1636279363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.3002004038
Short name	T553
Test name
Test status
Simulation time	1722629961 ps
CPU time	2.97 seconds
Started	Dec 24 01:21:26 PM PST 23
Finished	Dec 24 01:21:30 PM PST 23
Peak memory	218760 kb
Host	smart-2e1b7dcc-c8bb-4bd7-ad68-e61d12d2bce6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002004038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3002004038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.180428775
Short name	T995
Test name
Test status
Simulation time	397169743 ps
CPU time	1.61 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:21:27 PM PST 23
Peak memory	220320 kb
Host	smart-7deed418-500d-492c-aace-8ac52af9ce43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180428775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.180428775 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.1245415814
Short name	T325
Test name
Test status
Simulation time	188803498709 ps
CPU time	3530.76 seconds
Started	Dec 24 01:21:29 PM PST 23
Finished	Dec 24 02:20:22 PM PST 23
Peak memory	487668 kb
Host	smart-6bac8bbd-b956-4766-a09d-bf25f2310452
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245415814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.1245415814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.2401338810
Short name	T1043
Test name
Test status
Simulation time	53936257372 ps
CPU time	442.12 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:28:48 PM PST 23
Peak memory	255592 kb
Host	smart-fa693aa8-95c1-4a3a-be7c-b3d3062a1ce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401338810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2401338810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.1651873871
Short name	T515
Test name
Test status
Simulation time	9712290641 ps
CPU time	57.74 seconds
Started	Dec 24 01:21:29 PM PST 23
Finished	Dec 24 01:22:27 PM PST 23
Peak memory	223880 kb
Host	smart-b386208c-c7eb-4354-b413-497d928b64d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651873871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1651873871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.2043195946
Short name	T878
Test name
Test status
Simulation time	64971132912 ps
CPU time	953.05 seconds
Started	Dec 24 01:21:25 PM PST 23
Finished	Dec 24 01:37:19 PM PST 23
Peak memory	328696 kb
Host	smart-0c309fbe-c76d-4d7a-92aa-ab93b9b5419e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2043195946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2043195946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_stress_all_with_rand_reset.98297290
Short name	T13
Test name
Test status
Simulation time	12315352770 ps
CPU time	658.76 seconds
Started	Dec 24 01:21:29 PM PST 23
Finished	Dec 24 01:32:29 PM PST 23
Peak memory	309204 kb
Host	smart-d7a47ccf-2407-4a56-8ed5-356c2ad1afd0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=98297290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.98297290 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.4187692282
Short name	T656
Test name
Test status
Simulation time	254719028 ps
CPU time	6.74 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 01:21:29 PM PST 23
Peak memory	220272 kb
Host	smart-ee7c3cb9-2deb-47ca-bf30-02bd991a7236
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187692282 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.4187692282 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.912337349
Short name	T524
Test name
Test status
Simulation time	216231899 ps
CPU time	5.98 seconds
Started	Dec 24 01:21:25 PM PST 23
Finished	Dec 24 01:21:32 PM PST 23
Peak memory	220268 kb
Host	smart-fa229ea4-be47-4c27-9dc1-b2dab09cafea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912337349 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 49.kmac_test_vectors_kmac_xof.912337349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.3338131419
Short name	T753
Test name
Test status
Simulation time	74831545368 ps
CPU time	2120.11 seconds
Started	Dec 24 01:21:22 PM PST 23
Finished	Dec 24 01:56:43 PM PST 23
Peak memory	396844 kb
Host	smart-72ea0fdb-9cb9-4e4a-9e63-edb9650249fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3338131419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3338131419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.720867582
Short name	T378
Test name
Test status
Simulation time	801887454128 ps
CPU time	2283.91 seconds
Started	Dec 24 01:21:23 PM PST 23
Finished	Dec 24 01:59:29 PM PST 23
Peak memory	391292 kb
Host	smart-328a43cc-1a01-4ae8-bdfe-e61d174b27fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=720867582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.720867582 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.1392884302
Short name	T512
Test name
Test status
Simulation time	14724222967 ps
CPU time	1480.02 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:46:05 PM PST 23
Peak memory	338772 kb
Host	smart-7f6c80ae-3255-4b98-9438-eba9e1640190
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1392884302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1392884302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.134025112
Short name	T1028
Test name
Test status
Simulation time	81204220596 ps
CPU time	1119.24 seconds
Started	Dec 24 01:21:24 PM PST 23
Finished	Dec 24 01:40:05 PM PST 23
Peak memory	301672 kb
Host	smart-f0752df3-76da-410f-b9ed-80622a4ddc0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=134025112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.134025112 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.2065827301
Short name	T1083
Test name
Test status
Simulation time	285958913063 ps
CPU time	4790.78 seconds
Started	Dec 24 01:21:30 PM PST 23
Finished	Dec 24 02:41:23 PM PST 23
Peak memory	650440 kb
Host	smart-c2fa2c75-76db-416c-b330-774edc0ebc06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2065827301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2065827301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.1788034984
Short name	T446
Test name
Test status
Simulation time	608575082047 ps
CPU time	5090.08 seconds
Started	Dec 24 01:21:21 PM PST 23
Finished	Dec 24 02:46:13 PM PST 23
Peak memory	579320 kb
Host	smart-49e03eca-1a0e-4670-bc1d-e96215b236e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1788034984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1788034984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.1463589988
Short name	T1060
Test name
Test status
Simulation time	19073552 ps
CPU time	0.82 seconds
Started	Dec 24 01:18:37 PM PST 23
Finished	Dec 24 01:18:56 PM PST 23
Peak memory	218604 kb
Host	smart-7f1ac37c-39c8-48bb-ae12-9d082e97202c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463589988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1463589988 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.1020145938
Short name	T691
Test name
Test status
Simulation time	41154643647 ps
CPU time	259.22 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:23:22 PM PST 23
Peak memory	245636 kb
Host	smart-2e338546-7d01-473f-8c06-ef6ff2854da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020145938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1020145938 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.3051629214
Short name	T859
Test name
Test status
Simulation time	9271677641 ps
CPU time	124.98 seconds
Started	Dec 24 01:18:10 PM PST 23
Finished	Dec 24 01:20:16 PM PST 23
Peak memory	239156 kb
Host	smart-a7ce4c80-0665-436b-a50d-4055508c17d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051629214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3051629214 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.3214496109
Short name	T359
Test name
Test status
Simulation time	6085635312 ps
CPU time	590.04 seconds
Started	Dec 24 01:18:12 PM PST 23
Finished	Dec 24 01:28:04 PM PST 23
Peak memory	243028 kb
Host	smart-92d9a02a-5fcb-4875-b4ec-64b5df40f0f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214496109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3214496109 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.4188972089
Short name	T406
Test name
Test status
Simulation time	232189310 ps
CPU time	15.82 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	238784 kb
Host	smart-dd1f9fe5-b220-4427-88d6-2e5481cbaf21
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4188972089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.4188972089 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.4064048925
Short name	T77
Test name
Test status
Simulation time	36540738 ps
CPU time	1.17 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	218692 kb
Host	smart-abf2c682-61fc-415c-be02-a45c2eea63b4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4064048925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.4064048925 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.2881180192
Short name	T39
Test name
Test status
Simulation time	13234746315 ps
CPU time	72.18 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 01:20:08 PM PST 23
Peak memory	221516 kb
Host	smart-5aed41a4-7dfe-4b6f-b4e6-7b9be842d925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881180192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2881180192 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.3183231363
Short name	T306
Test name
Test status
Simulation time	13095347959 ps
CPU time	164.92 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:21:28 PM PST 23
Peak memory	242088 kb
Host	smart-865dae86-d847-48d7-a985-0be2633e5002
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183231363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3183231363 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_key_error.164789901
Short name	T256
Test name
Test status
Simulation time	929904602 ps
CPU time	5.92 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:19:09 PM PST 23
Peak memory	218544 kb
Host	smart-a1031b1e-a9e0-474a-9e0b-1f61fdf663f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164789901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.164789901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.2337623594
Short name	T684
Test name
Test status
Simulation time	116872276 ps
CPU time	1.38 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	219920 kb
Host	smart-6970a43f-74c7-4f00-8185-49b2b189aa1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337623594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2337623594 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.832247945
Short name	T518
Test name
Test status
Simulation time	196377225103 ps
CPU time	2644.4 seconds
Started	Dec 24 01:18:30 PM PST 23
Finished	Dec 24 02:02:53 PM PST 23
Peak memory	426180 kb
Host	smart-22d08d97-15c8-4b7c-b854-f09e30ba2736
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832247945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and _output.832247945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.2899924641
Short name	T136
Test name
Test status
Simulation time	11633867165 ps
CPU time	342.38 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 01:24:31 PM PST 23
Peak memory	254628 kb
Host	smart-e39c5ce9-b22c-4e3e-9d9c-26e1b38efce3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899924641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2899924641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.3574086450
Short name	T1099
Test name
Test status
Simulation time	2135302978 ps
CPU time	82.37 seconds
Started	Dec 24 01:18:22 PM PST 23
Finished	Dec 24 01:20:05 PM PST 23
Peak memory	239188 kb
Host	smart-d40ba24f-ed50-4b6e-ad0e-fe9c01cfd20b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574086450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3574086450 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.2696652441
Short name	T987
Test name
Test status
Simulation time	17709092832 ps
CPU time	30.93 seconds
Started	Dec 24 01:18:11 PM PST 23
Finished	Dec 24 01:18:44 PM PST 23
Peak memory	226904 kb
Host	smart-8c9419df-4567-490a-9963-4d55d4954ccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696652441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2696652441 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.594407373
Short name	T428
Test name
Test status
Simulation time	40300779571 ps
CPU time	228.54 seconds
Started	Dec 24 01:18:31 PM PST 23
Finished	Dec 24 01:22:38 PM PST 23
Peak memory	243108 kb
Host	smart-8401d5ab-d38f-4a96-b577-fa7da9fd9b5c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=594407373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.594407373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.1729897065
Short name	T612
Test name
Test status
Simulation time	61230774770 ps
CPU time	1059.63 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:36:37 PM PST 23
Peak memory	292736 kb
Host	smart-fb26f7f2-84a8-4444-84f7-0dc8d07abc50
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1729897065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.1729897065 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.3852695352
Short name	T1122
Test name
Test status
Simulation time	284680973 ps
CPU time	6.52 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:18:50 PM PST 23
Peak memory	220468 kb
Host	smart-99bf72b2-49f8-4f09-88bc-cdb445001a3e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852695352 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.kmac_test_vectors_kmac.3852695352 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3363512311
Short name	T805
Test name
Test status
Simulation time	109330069 ps
CPU time	5.62 seconds
Started	Dec 24 01:18:23 PM PST 23
Finished	Dec 24 01:18:49 PM PST 23
Peak memory	218744 kb
Host	smart-d163531f-d0d7-4aa9-8e0a-b2c1a94276a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363512311 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3363512311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.882788474
Short name	T1042
Test name
Test status
Simulation time	201646509758 ps
CPU time	2437.35 seconds
Started	Dec 24 01:18:23 PM PST 23
Finished	Dec 24 01:59:21 PM PST 23
Peak memory	396976 kb
Host	smart-2f379f8f-2c46-4e35-8a5a-43ff5ecaec50
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=882788474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.882788474 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.2072201031
Short name	T1096
Test name
Test status
Simulation time	194069197868 ps
CPU time	1935.17 seconds
Started	Dec 24 01:18:25 PM PST 23
Finished	Dec 24 01:50:59 PM PST 23
Peak memory	392116 kb
Host	smart-5fce1345-7445-4602-9b35-5ff300fd4e9a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2072201031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2072201031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.3185195808
Short name	T747
Test name
Test status
Simulation time	63285219047 ps
CPU time	1557.73 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:44:41 PM PST 23
Peak memory	347208 kb
Host	smart-c24212e9-122f-4585-b576-3066b1f553bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3185195808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3185195808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.3929506168
Short name	T877
Test name
Test status
Simulation time	10564912975 ps
CPU time	1114.86 seconds
Started	Dec 24 01:18:20 PM PST 23
Finished	Dec 24 01:37:05 PM PST 23
Peak memory	304352 kb
Host	smart-7ac1d811-3f6b-4818-aa65-e48a2f2e9ecf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3929506168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.3929506168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.3521472301
Short name	T565
Test name
Test status
Simulation time	480046974811 ps
CPU time	5911.82 seconds
Started	Dec 24 01:18:13 PM PST 23
Finished	Dec 24 02:56:48 PM PST 23
Peak memory	661560 kb
Host	smart-df712760-03a1-421d-bf22-74597ab32ee3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3521472301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3521472301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.2874310092
Short name	T1064
Test name
Test status
Simulation time	153260470199 ps
CPU time	4639.98 seconds
Started	Dec 24 01:18:30 PM PST 23
Finished	Dec 24 02:36:09 PM PST 23
Peak memory	570900 kb
Host	smart-4eae1b0d-20f1-4bf8-ae52-078fceba9c9e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2874310092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2874310092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.2648414015
Short name	T1002
Test name
Test status
Simulation time	18814173 ps
CPU time	0.87 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	218428 kb
Host	smart-c730a405-9816-4aa1-9199-22505a7a0387
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648414015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2648414015 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.1094353428
Short name	T321
Test name
Test status
Simulation time	971030110 ps
CPU time	15.85 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:27 PM PST 23
Peak memory	221952 kb
Host	smart-8a668de2-3ad1-432d-a492-9fabe1f028f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094353428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1094353428 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.2734515564
Short name	T938
Test name
Test status
Simulation time	2494982015 ps
CPU time	50.85 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:20:02 PM PST 23
Peak memory	229396 kb
Host	smart-93ebf601-9774-46bc-97a0-ab6e49976658
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734515564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2734515564 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.506425263
Short name	T472
Test name
Test status
Simulation time	17121583768 ps
CPU time	345.36 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:24:54 PM PST 23
Peak memory	234096 kb
Host	smart-28cabfe0-4ae6-4ff3-a7da-a0e1172fdfc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506425263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.506425263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.2773994854
Short name	T209
Test name
Test status
Simulation time	155334364 ps
CPU time	11.44 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:26 PM PST 23
Peak memory	230924 kb
Host	smart-65829deb-21bd-4466-a40a-ce53339f246b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2773994854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2773994854 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.766259939
Short name	T1056
Test name
Test status
Simulation time	143810476 ps
CPU time	1.18 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	218692 kb
Host	smart-78fe9465-8c91-4f51-aeef-9dd416f93c55
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=766259939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.766259939 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.3643339496
Short name	T38
Test name
Test status
Simulation time	2795913185 ps
CPU time	39.43 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:53 PM PST 23
Peak memory	219444 kb
Host	smart-02ec19c8-e5e8-4144-a809-12fd05f437a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643339496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3643339496 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.570390293
Short name	T1048
Test name
Test status
Simulation time	10240673629 ps
CPU time	230.06 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:23:04 PM PST 23
Peak memory	243968 kb
Host	smart-0847a28b-92e3-4fed-8e0b-20843490111c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570390293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.570390293 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.816629275
Short name	T474
Test name
Test status
Simulation time	12856643300 ps
CPU time	105.47 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:20:58 PM PST 23
Peak memory	243428 kb
Host	smart-78967853-4b0f-416e-807f-0f69bce0e658
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816629275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.816629275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.2074962412
Short name	T603
Test name
Test status
Simulation time	2850434852 ps
CPU time	4.01 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:19:19 PM PST 23
Peak memory	218580 kb
Host	smart-d6d3775e-e7f1-4a84-a657-0d32beeabb95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074962412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2074962412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.426542476
Short name	T12
Test name
Test status
Simulation time	104328178 ps
CPU time	1.18 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	218896 kb
Host	smart-48023939-f642-436f-a6de-a196e8daa220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426542476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.426542476 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.2556546934
Short name	T795
Test name
Test status
Simulation time	43176272887 ps
CPU time	297.39 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:24:01 PM PST 23
Peak memory	246064 kb
Host	smart-bd1915ac-9831-41f6-987e-6dac2439d58f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556546934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.2556546934 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.2020680925
Short name	T1087
Test name
Test status
Simulation time	2481037041 ps
CPU time	57.96 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:20:06 PM PST 23
Peak memory	238512 kb
Host	smart-7354bb6e-fc82-44a9-9855-c0733f575c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020680925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2020680925 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.1853075888
Short name	T232
Test name
Test status
Simulation time	11896215414 ps
CPU time	271.68 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:23:37 PM PST 23
Peak memory	247288 kb
Host	smart-d74638db-0bd4-4329-909a-52e3a3e34a3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853075888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1853075888 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.3319659971
Short name	T240
Test name
Test status
Simulation time	2800476927 ps
CPU time	47.43 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:19:47 PM PST 23
Peak memory	227072 kb
Host	smart-17f86476-5eb1-4aaf-b447-5f161f01bdb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319659971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3319659971 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.2288345656
Short name	T1133
Test name
Test status
Simulation time	233516879494 ps
CPU time	1281.04 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:40:27 PM PST 23
Peak memory	358416 kb
Host	smart-718e0dfc-d381-4235-8e18-9838025280cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2288345656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2288345656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.2983780193
Short name	T342
Test name
Test status
Simulation time	176056547 ps
CPU time	5.24 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	220280 kb
Host	smart-070bf73c-7b9d-4a12-815b-278307ad2a17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983780193 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.2983780193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.2867700883
Short name	T985
Test name
Test status
Simulation time	1154753165 ps
CPU time	6.41 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:19:15 PM PST 23
Peak memory	220464 kb
Host	smart-2c48987b-385f-4fef-8f97-d74d28eb0361
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867700883 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.2867700883 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.3117094879
Short name	T704
Test name
Test status
Simulation time	84846153461 ps
CPU time	2087.5 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:53:46 PM PST 23
Peak memory	398884 kb
Host	smart-fdb2cb0c-b22b-4021-9af6-07b6963cd849
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3117094879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3117094879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.2298227949
Short name	T1052
Test name
Test status
Simulation time	63005225351 ps
CPU time	2217.57 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:56:04 PM PST 23
Peak memory	382896 kb
Host	smart-452b1b14-d2c5-4b44-a8ad-cf19722779d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2298227949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2298227949 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.1814780795
Short name	T227
Test name
Test status
Simulation time	95524231261 ps
CPU time	1711.14 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:47:39 PM PST 23
Peak memory	335752 kb
Host	smart-99af4e84-9e6d-4231-a16b-31f579a38581
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1814780795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1814780795 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.3248435854
Short name	T365
Test name
Test status
Simulation time	227449447454 ps
CPU time	1331.98 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:41:16 PM PST 23
Peak memory	297196 kb
Host	smart-b60b0ab3-cb1a-41f7-9f20-b05633c274fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3248435854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.3248435854 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.2047673578
Short name	T103
Test name
Test status
Simulation time	2091105699666 ps
CPU time	5708.89 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 02:54:15 PM PST 23
Peak memory	674252 kb
Host	smart-bb3bd76c-fc41-40b1-a0c9-a3505bda4713
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2047673578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2047673578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.679419229
Short name	T1093
Test name
Test status
Simulation time	153594175480 ps
CPU time	4879.18 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 02:40:27 PM PST 23
Peak memory	575440 kb
Host	smart-6cf1cfad-52d5-449b-a23e-86bf81b24ad5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=679419229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.679419229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.227357435
Short name	T366
Test name
Test status
Simulation time	21277890 ps
CPU time	0.86 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:19:07 PM PST 23
Peak memory	218484 kb
Host	smart-46de8126-92d7-4944-accc-d969ed0dfca1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227357435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.227357435 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.2592683007
Short name	T339
Test name
Test status
Simulation time	24904260036 ps
CPU time	348.94 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:24:47 PM PST 23
Peak memory	253216 kb
Host	smart-98f6d9b7-77e9-4642-b424-7d18ead33e65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592683007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2592683007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.4124493069
Short name	T911
Test name
Test status
Simulation time	7626127327 ps
CPU time	195.81 seconds
Started	Dec 24 01:18:32 PM PST 23
Finished	Dec 24 01:22:07 PM PST 23
Peak memory	244268 kb
Host	smart-0fcd0a51-5571-4373-b715-604e3978384a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124493069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.4124493069 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.317565046
Short name	T480
Test name
Test status
Simulation time	139342910653 ps
CPU time	1227.53 seconds
Started	Dec 24 01:18:52 PM PST 23
Finished	Dec 24 01:39:43 PM PST 23
Peak memory	239700 kb
Host	smart-dec2d315-db97-4949-bac0-80c48967e5b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317565046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.317565046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.3851508568
Short name	T492
Test name
Test status
Simulation time	1367784905 ps
CPU time	35.16 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:19:33 PM PST 23
Peak memory	237624 kb
Host	smart-5c8a9a17-ce47-4489-bf2d-a9684da94b77
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3851508568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3851508568 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.2621780775
Short name	T499
Test name
Test status
Simulation time	2047496366 ps
CPU time	48.85 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:52 PM PST 23
Peak memory	229136 kb
Host	smart-598c2d55-7727-44e3-bb5d-d471c3505a92
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2621780775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2621780775 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.3795339366
Short name	T761
Test name
Test status
Simulation time	20728065790 ps
CPU time	73.64 seconds
Started	Dec 24 01:18:42 PM PST 23
Finished	Dec 24 01:20:13 PM PST 23
Peak memory	221736 kb
Host	smart-4fa8d711-b5b8-40da-85c9-9575a04ff3a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795339366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3795339366 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.2709173240
Short name	T929
Test name
Test status
Simulation time	66681021675 ps
CPU time	329.43 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 01:24:25 PM PST 23
Peak memory	249584 kb
Host	smart-5a5930a2-e957-4048-b74d-1e414aeb6fb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709173240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2709173240 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_key_error.3999077960
Short name	T101
Test name
Test status
Simulation time	1156591242 ps
CPU time	3.92 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:19:02 PM PST 23
Peak memory	218812 kb
Host	smart-8208b9f3-533f-421b-bf59-292dab76d35a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999077960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3999077960 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.68448654
Short name	T97
Test name
Test status
Simulation time	478185641 ps
CPU time	1.3 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:18:50 PM PST 23
Peak memory	218924 kb
Host	smart-f945e6b0-d937-4b5b-b171-afc2eb3be37b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68448654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.68448654 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.2023657137
Short name	T800
Test name
Test status
Simulation time	36537457892 ps
CPU time	962.81 seconds
Started	Dec 24 01:18:55 PM PST 23
Finished	Dec 24 01:35:21 PM PST 23
Peak memory	294744 kb
Host	smart-e002ec4b-34d9-48ea-b602-49f13d449fef
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023657137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.2023657137 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.1095131394
Short name	T16
Test name
Test status
Simulation time	13448575422 ps
CPU time	279.98 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:23:43 PM PST 23
Peak memory	247536 kb
Host	smart-fb069e69-a759-4724-b11e-309cb31c44b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095131394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1095131394 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.2619804967
Short name	T460
Test name
Test status
Simulation time	23718231591 ps
CPU time	153 seconds
Started	Dec 24 01:18:30 PM PST 23
Finished	Dec 24 01:21:22 PM PST 23
Peak memory	235424 kb
Host	smart-566300eb-b7ef-434f-9a57-cf8fb4b1de40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619804967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2619804967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.352543049
Short name	T1046
Test name
Test status
Simulation time	4157413436 ps
CPU time	79.42 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:20:25 PM PST 23
Peak memory	223548 kb
Host	smart-c5576646-ce58-48b8-b652-e72e6f7b146b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352543049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.352543049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.650647530
Short name	T1117
Test name
Test status
Simulation time	27645246280 ps
CPU time	1055.36 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:36:39 PM PST 23
Peak memory	312676 kb
Host	smart-b1c2a7af-b646-49df-b9eb-47b42cf1a676
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=650647530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.650647530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_stress_all_with_rand_reset.3843897610
Short name	T1086
Test name
Test status
Simulation time	532210581575 ps
CPU time	1402.45 seconds
Started	Dec 24 01:18:24 PM PST 23
Finished	Dec 24 01:42:06 PM PST 23
Peak memory	340048 kb
Host	smart-8d6c8203-ed96-4458-9261-a9c3522f5bb9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3843897610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.3843897610 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.2258999402
Short name	T404
Test name
Test status
Simulation time	233073789 ps
CPU time	6.68 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	220332 kb
Host	smart-79b7ba93-42b5-417b-9ac6-bb0f6c8ca6cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258999402 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.2258999402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3172981533
Short name	T261
Test name
Test status
Simulation time	236666282 ps
CPU time	6.73 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:19:05 PM PST 23
Peak memory	218848 kb
Host	smart-4db15c7f-46de-466b-a767-338a0f5a0fe9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172981533 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3172981533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.2378432021
Short name	T781
Test name
Test status
Simulation time	66763032072 ps
CPU time	2221.13 seconds
Started	Dec 24 01:18:27 PM PST 23
Finished	Dec 24 01:55:49 PM PST 23
Peak memory	401108 kb
Host	smart-6e923ab0-1692-42df-80a0-b2c88a30db42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2378432021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2378432021 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.1221711463
Short name	T1065
Test name
Test status
Simulation time	620254670999 ps
CPU time	2059.1 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:53:08 PM PST 23
Peak memory	387712 kb
Host	smart-d3cc95fd-3f42-4dbd-acbf-e238d0766c02
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1221711463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1221711463 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.2975043297
Short name	T743
Test name
Test status
Simulation time	68890710790 ps
CPU time	1559.46 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:45:03 PM PST 23
Peak memory	342640 kb
Host	smart-f521febe-b903-409b-9c13-d4a86c5a1317
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2975043297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2975043297 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.3284453575
Short name	T978
Test name
Test status
Simulation time	46804804159 ps
CPU time	1241.84 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:39:44 PM PST 23
Peak memory	308832 kb
Host	smart-9642576d-8150-4c12-8cdb-1f47ddcf31da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3284453575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3284453575 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.2783015172
Short name	T764
Test name
Test status
Simulation time	135900546854 ps
CPU time	5094.13 seconds
Started	Dec 24 01:18:36 PM PST 23
Finished	Dec 24 02:43:50 PM PST 23
Peak memory	667408 kb
Host	smart-2580db77-b322-4650-acfe-820b52a4a93a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2783015172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.2783015172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.4213938858
Short name	T1026
Test name
Test status
Simulation time	106358262019 ps
CPU time	4180.27 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 02:28:38 PM PST 23
Peak memory	579120 kb
Host	smart-eac072a6-a322-495e-a433-dc75ec8aa6aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4213938858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.4213938858 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.3153049183
Short name	T914
Test name
Test status
Simulation time	17493072 ps
CPU time	0.85 seconds
Started	Dec 24 01:18:37 PM PST 23
Finished	Dec 24 01:18:56 PM PST 23
Peak memory	219780 kb
Host	smart-675cea69-2a5b-438a-a34e-7f00c4f45536
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153049183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3153049183 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.1002605007
Short name	T253
Test name
Test status
Simulation time	14465596491 ps
CPU time	358.39 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:24:57 PM PST 23
Peak memory	253416 kb
Host	smart-25133a0a-f3a2-4228-a314-011bbfe61c59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002605007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1002605007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.587229254
Short name	T992
Test name
Test status
Simulation time	6845619731 ps
CPU time	241.77 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:23:06 PM PST 23
Peak memory	246800 kb
Host	smart-bbbc7b7c-40b7-4c1d-b1c6-2b600e3f779b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587229254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.587229254 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.3470480154
Short name	T902
Test name
Test status
Simulation time	7966816816 ps
CPU time	414.65 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:26:06 PM PST 23
Peak memory	232792 kb
Host	smart-561e4b36-bb53-4144-a6ce-a6eebf63b44a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470480154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3470480154 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.3238470391
Short name	T68
Test name
Test status
Simulation time	155625113 ps
CPU time	1.24 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:10 PM PST 23
Peak memory	218596 kb
Host	smart-8e07800a-fbea-4333-8a86-59692f837189
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3238470391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3238470391 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.56611714
Short name	T752
Test name
Test status
Simulation time	20057005 ps
CPU time	0.95 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 01:18:59 PM PST 23
Peak memory	218612 kb
Host	smart-f13072dd-4772-4d3c-b66b-06b01107250a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=56611714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.56611714 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.1805101174
Short name	T649
Test name
Test status
Simulation time	22500358949 ps
CPU time	66.1 seconds
Started	Dec 24 01:18:34 PM PST 23
Finished	Dec 24 01:20:01 PM PST 23
Peak memory	222236 kb
Host	smart-469e6d26-9b6f-4b1a-90b5-0bd815762b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805101174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1805101174 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.386091376
Short name	T961
Test name
Test status
Simulation time	8318448924 ps
CPU time	221.89 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:22:43 PM PST 23
Peak memory	243052 kb
Host	smart-17a6171d-2501-40da-b087-9bb726babd08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386091376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.386091376 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_error.2323251672
Short name	T426
Test name
Test status
Simulation time	5409076498 ps
CPU time	386.53 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:25:27 PM PST 23
Peak memory	268040 kb
Host	smart-5e04b79a-5155-4de8-bb8a-6c0b1af69024
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323251672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2323251672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.3126405915
Short name	T740
Test name
Test status
Simulation time	363806139 ps
CPU time	1.96 seconds
Started	Dec 24 01:18:38 PM PST 23
Finished	Dec 24 01:19:00 PM PST 23
Peak memory	218716 kb
Host	smart-94f66027-facc-4cd0-8d07-9d3855507feb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126405915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3126405915 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.1687738635
Short name	T960
Test name
Test status
Simulation time	178398780 ps
CPU time	1.47 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 01:18:50 PM PST 23
Peak memory	219900 kb
Host	smart-a54e54ee-575b-40c0-8177-77f7ffac4b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687738635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1687738635 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.1627279406
Short name	T883
Test name
Test status
Simulation time	99077713290 ps
CPU time	2722.49 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 02:04:11 PM PST 23
Peak memory	454264 kb
Host	smart-d24ed385-4e72-45bc-8e05-fcd463ac7d9d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627279406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.1627279406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.2827174051
Short name	T910
Test name
Test status
Simulation time	6618764055 ps
CPU time	162.94 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:21:41 PM PST 23
Peak memory	243244 kb
Host	smart-49582dbe-a84d-4a7b-9de3-76e729452652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827174051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2827174051 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.1394153360
Short name	T821
Test name
Test status
Simulation time	2369030960 ps
CPU time	76 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:20:22 PM PST 23
Peak memory	230724 kb
Host	smart-9850af43-c6f9-4462-9acf-2afa4963ecd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394153360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1394153360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.1135515549
Short name	T823
Test name
Test status
Simulation time	1386723041 ps
CPU time	54.21 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 01:20:03 PM PST 23
Peak memory	226908 kb
Host	smart-9ae3efbf-4428-4f8d-bde2-dac938ab2df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1135515549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1135515549 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.198704851
Short name	T1116
Test name
Test status
Simulation time	86292314004 ps
CPU time	1483.01 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 01:43:41 PM PST 23
Peak memory	404588 kb
Host	smart-e24b7175-9d63-4d3b-aa3d-839623933ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=198704851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.198704851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_stress_all_with_rand_reset.4239127719
Short name	T686
Test name
Test status
Simulation time	99190224169 ps
CPU time	1646.95 seconds
Started	Dec 24 01:18:37 PM PST 23
Finished	Dec 24 01:46:22 PM PST 23
Peak memory	352452 kb
Host	smart-b0dacbec-fe38-41e1-a2cf-4a6a65ed9ceb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4239127719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.4239127719 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.3342313422
Short name	T463
Test name
Test status
Simulation time	439029388 ps
CPU time	5.98 seconds
Started	Dec 24 01:18:37 PM PST 23
Finished	Dec 24 01:19:01 PM PST 23
Peak memory	220372 kb
Host	smart-a654710c-4ac3-49d8-a1d4-fa1df37beb67
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342313422 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.3342313422 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1653404075
Short name	T183
Test name
Test status
Simulation time	231452880 ps
CPU time	5.94 seconds
Started	Dec 24 01:18:36 PM PST 23
Finished	Dec 24 01:19:02 PM PST 23
Peak memory	218840 kb
Host	smart-9e5c09fd-04d3-4d32-88c3-82daa94d0454
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653404075 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1653404075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.1765603664
Short name	T772
Test name
Test status
Simulation time	175584887608 ps
CPU time	2349.89 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:58:14 PM PST 23
Peak memory	405328 kb
Host	smart-efdc6ff7-f54c-442a-bd30-bbd8b426eabd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1765603664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1765603664 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.2634473473
Short name	T216
Test name
Test status
Simulation time	515648394734 ps
CPU time	2630.92 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 02:02:55 PM PST 23
Peak memory	392620 kb
Host	smart-4c275ad0-06b2-4810-8f6e-8ec9ec445198
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2634473473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2634473473 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.2256793537
Short name	T1089
Test name
Test status
Simulation time	30962616345 ps
CPU time	1661.83 seconds
Started	Dec 24 01:18:29 PM PST 23
Finished	Dec 24 01:46:30 PM PST 23
Peak memory	340120 kb
Host	smart-051cbfdd-fb7a-44d7-9ec3-2a24ea1b7852
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2256793537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2256793537 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.2318859436
Short name	T434
Test name
Test status
Simulation time	132820861145 ps
CPU time	1255.97 seconds
Started	Dec 24 01:18:44 PM PST 23
Finished	Dec 24 01:39:59 PM PST 23
Peak memory	298216 kb
Host	smart-9afaf4b2-2d4e-4ce5-bf06-ee33c3ff0f5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2318859436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2318859436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.2798663633
Short name	T1131
Test name
Test status
Simulation time	1035403894619 ps
CPU time	6134.64 seconds
Started	Dec 24 01:18:40 PM PST 23
Finished	Dec 24 03:01:13 PM PST 23
Peak memory	656144 kb
Host	smart-6956cbbf-7930-4862-bc24-15f17749a245
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2798663633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2798663633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.2952234832
Short name	T690
Test name
Test status
Simulation time	227974917898 ps
CPU time	5081.09 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 02:43:49 PM PST 23
Peak memory	572704 kb
Host	smart-125850be-f4df-4f62-a9d5-401a05ec649e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2952234832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.2952234832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.3055859814
Short name	T394
Test name
Test status
Simulation time	18938999 ps
CPU time	0.84 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:12 PM PST 23
Peak memory	219748 kb
Host	smart-2328873b-9cae-499a-81e0-1683e811389c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055859814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3055859814 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.4169915485
Short name	T1011
Test name
Test status
Simulation time	2662143407 ps
CPU time	135.28 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:21:20 PM PST 23
Peak memory	240636 kb
Host	smart-9172fc77-92ab-4006-a9c6-eeb23a86db07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169915485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.4169915485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.1248272755
Short name	T857
Test name
Test status
Simulation time	24439440648 ps
CPU time	334.92 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:24:46 PM PST 23
Peak memory	249532 kb
Host	smart-5d7cf8b5-a705-462c-b822-f1d9a9cd0c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248272755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1248272755 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.3231620518
Short name	T419
Test name
Test status
Simulation time	68574162502 ps
CPU time	1385.68 seconds
Started	Dec 24 01:18:43 PM PST 23
Finished	Dec 24 01:42:08 PM PST 23
Peak memory	242588 kb
Host	smart-abde72e2-a9b5-47b0-aac3-e20556128d10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231620518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3231620518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.3558053057
Short name	T29
Test name
Test status
Simulation time	144040916 ps
CPU time	5.12 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	225400 kb
Host	smart-226ae60e-d5fa-46b8-bbc8-55480dcbeeba
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3558053057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3558053057 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.4248168033
Short name	T78
Test name
Test status
Simulation time	66509822 ps
CPU time	1.03 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:19:14 PM PST 23
Peak memory	218784 kb
Host	smart-8b7f3069-7efd-464c-bff6-39b1872a576e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4248168033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.4248168033 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.704321164
Short name	T487
Test name
Test status
Simulation time	40544100793 ps
CPU time	85.55 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:20:38 PM PST 23
Peak memory	222352 kb
Host	smart-983bab8a-5b1c-4a6d-a72e-f416c9b627c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704321164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.704321164 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_error.3109887326
Short name	T585
Test name
Test status
Simulation time	5820968287 ps
CPU time	337.91 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:24:52 PM PST 23
Peak memory	259580 kb
Host	smart-cc8047f9-f778-412e-bd1c-9f5f0f4e3c7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109887326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3109887326 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.193897630
Short name	T36
Test name
Test status
Simulation time	6139778844 ps
CPU time	5.8 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:19:17 PM PST 23
Peak memory	219000 kb
Host	smart-89f3b91f-1db7-4563-a1d2-f7cb6d62f6b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193897630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.193897630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.420703595
Short name	T710
Test name
Test status
Simulation time	96192270 ps
CPU time	1.5 seconds
Started	Dec 24 01:18:51 PM PST 23
Finished	Dec 24 01:19:16 PM PST 23
Peak memory	221676 kb
Host	smart-6a952c36-df77-40cf-8f80-7de297de5ba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420703595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.420703595 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.1125241698
Short name	T762
Test name
Test status
Simulation time	33249687712 ps
CPU time	841.99 seconds
Started	Dec 24 01:18:28 PM PST 23
Finished	Dec 24 01:32:51 PM PST 23
Peak memory	299528 kb
Host	smart-279ddd56-f57e-4575-b60c-0ae963276ff2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125241698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an d_output.1125241698 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.2889444716
Short name	T1010
Test name
Test status
Simulation time	147033637716 ps
CPU time	276.6 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:23:45 PM PST 23
Peak memory	246096 kb
Host	smart-9cad2d7a-e613-41b0-bf17-35d53d0cf456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889444716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2889444716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.695719845
Short name	T448
Test name
Test status
Simulation time	36805970708 ps
CPU time	498.5 seconds
Started	Dec 24 01:18:49 PM PST 23
Finished	Dec 24 01:27:30 PM PST 23
Peak memory	254364 kb
Host	smart-1c69ce90-1b9e-4d7e-8976-0cdbed6f1479
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695719845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.695719845 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.60786158
Short name	T258
Test name
Test status
Simulation time	2383176082 ps
CPU time	30.71 seconds
Started	Dec 24 01:18:35 PM PST 23
Finished	Dec 24 01:19:25 PM PST 23
Peak memory	226936 kb
Host	smart-9adc7985-2ee5-4c0d-b92b-0b4ac8c07317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60786158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.60786158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1376467219
Short name	T1114
Test name
Test status
Simulation time	65077920630 ps
CPU time	1067.07 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:36:53 PM PST 23
Peak memory	298660 kb
Host	smart-29f36969-01fa-436c-b320-1b725b192dda
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1376467219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1376467219 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.111514750
Short name	T249
Test name
Test status
Simulation time	138629845 ps
CPU time	5.86 seconds
Started	Dec 24 01:18:50 PM PST 23
Finished	Dec 24 01:19:18 PM PST 23
Peak memory	220208 kb
Host	smart-40262e68-c4fa-45d2-a56d-b1e90f735a23
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111514750 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.111514750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3187505884
Short name	T69
Test name
Test status
Simulation time	138222772 ps
CPU time	5.82 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:19:14 PM PST 23
Peak memory	220064 kb
Host	smart-2435e7f0-13e2-4524-b872-ea8d11cae693
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187505884 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3187505884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.4094701584
Short name	T888
Test name
Test status
Simulation time	128906522089 ps
CPU time	2287.59 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 01:57:13 PM PST 23
Peak memory	393516 kb
Host	smart-c199dd49-e24e-4b13-beca-7625ab3d9ab6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4094701584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.4094701584 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.630875648
Short name	T728
Test name
Test status
Simulation time	81633476409 ps
CPU time	1924.77 seconds
Started	Dec 24 01:18:45 PM PST 23
Finished	Dec 24 01:51:10 PM PST 23
Peak memory	395840 kb
Host	smart-9379280c-4e35-4bf2-b472-dea8b7748b3b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=630875648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.630875648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.3581702279
Short name	T551
Test name
Test status
Simulation time	47981462246 ps
CPU time	1718.1 seconds
Started	Dec 24 01:18:47 PM PST 23
Finished	Dec 24 01:47:46 PM PST 23
Peak memory	344016 kb
Host	smart-35e5e345-e8cc-40c8-88d7-74f4fe7a60fe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3581702279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3581702279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.4103817992
Short name	T382
Test name
Test status
Simulation time	23101435348 ps
CPU time	1216.07 seconds
Started	Dec 24 01:18:41 PM PST 23
Finished	Dec 24 01:39:15 PM PST 23
Peak memory	305088 kb
Host	smart-ddc90b78-c40a-482b-b6bd-e169bcf98188
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4103817992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.4103817992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.4250420287
Short name	T433
Test name
Test status
Simulation time	310344748302 ps
CPU time	4939.13 seconds
Started	Dec 24 01:18:46 PM PST 23
Finished	Dec 24 02:41:26 PM PST 23
Peak memory	642236 kb
Host	smart-c0970f77-d65e-48c9-985b-a4f3bbb4ff89
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4250420287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.4250420287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.1353193811
Short name	T609
Test name
Test status
Simulation time	217823365101 ps
CPU time	4395.23 seconds
Started	Dec 24 01:18:48 PM PST 23
Finished	Dec 24 02:32:25 PM PST 23
Peak memory	566272 kb
Host	smart-5fabaa68-e41f-4196-a839-ddadab703e73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1353193811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1353193811 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%