Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100949608	1			T1	5		T56	5		T57	8
all_values[1]	100949608	1			T1	5		T56	5		T57	8
all_values[2]	100949608	1			T1	5		T56	5		T57	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

629118

1

T1

6

T56

13

T57

10

auto[1]

302219706

1

T1

9

T56

2

T57

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301316058

1

T1

3

T56

6

T57

18

auto[1]

1532766

1

T1

12

T56

9

T57

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	221035	1			T56	2		T57	3		T60	1
all_values[0]	auto[0]	auto[1]	2319	1			T1	2		T56	3		T69	2
all_values[0]	auto[1]	auto[0]	100217651	1			T1	1		T57	3		T62	3
all_values[0]	auto[1]	auto[1]	508603	1			T1	2		T57	2		T69	1
all_values[1]	auto[0]	auto[0]	182988	1			T56	1		T57	4		T60	1
all_values[1]	auto[0]	auto[1]	1696	1			T1	1		T56	3		T57	2
all_values[1]	auto[1]	auto[0]	100255698	1			T1	1		T56	1		T57	2
all_values[1]	auto[1]	auto[1]	509226	1			T1	3		T69	1		T124	1
all_values[2]	auto[0]	auto[0]	219496	1			T1	1		T56	2		T57	1
all_values[2]	auto[0]	auto[1]	1584	1			T1	2		T56	2		T69	1
all_values[2]	auto[1]	auto[0]	100219190	1			T57	5		T62	4		T69	2
all_values[2]	auto[1]	auto[1]	509338	1			T1	2		T56	1		T57	2