Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
391266 |
1 |
|
|
T4 |
696 |
|
T5 |
2 |
|
T6 |
2 |
auto[1] |
304686 |
1 |
|
|
T4 |
298 |
|
T5 |
16 |
|
T6 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174006 |
1 |
|
|
T4 |
271 |
|
T5 |
4 |
|
T6 |
2 |
lower_val |
172286 |
1 |
|
|
T4 |
234 |
|
T5 |
6 |
|
T6 |
2 |
zero_val |
2000 |
1 |
|
|
T4 |
14 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
272080 |
1 |
|
|
T4 |
440 |
|
T5 |
6 |
|
T6 |
4 |
lower_val |
271076 |
1 |
|
|
T4 |
420 |
|
T5 |
4 |
|
T6 |
2 |
zero_val |
152796 |
1 |
|
|
T4 |
134 |
|
T5 |
8 |
|
T6 |
12 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48597 |
1 |
|
|
T4 |
94 |
|
T11 |
19 |
|
T28 |
39 |
higher_val |
higher_val |
auto[1] |
19153 |
1 |
|
|
T4 |
27 |
|
T5 |
2 |
|
T6 |
1 |
higher_val |
lower_val |
auto[0] |
48667 |
1 |
|
|
T4 |
92 |
|
T6 |
1 |
|
T11 |
34 |
higher_val |
lower_val |
auto[1] |
19379 |
1 |
|
|
T4 |
23 |
|
T5 |
1 |
|
T23 |
49 |
higher_val |
zero_val |
auto[0] |
94 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
2 |
higher_val |
zero_val |
auto[1] |
38116 |
1 |
|
|
T4 |
34 |
|
T23 |
90 |
|
T10 |
558 |
lower_val |
higher_val |
auto[0] |
48666 |
1 |
|
|
T4 |
75 |
|
T11 |
13 |
|
T26 |
1 |
lower_val |
higher_val |
auto[1] |
18972 |
1 |
|
|
T4 |
22 |
|
T5 |
2 |
|
T6 |
1 |
lower_val |
lower_val |
auto[0] |
48092 |
1 |
|
|
T4 |
85 |
|
T11 |
13 |
|
T28 |
58 |
lower_val |
lower_val |
auto[1] |
18563 |
1 |
|
|
T4 |
20 |
|
T5 |
1 |
|
T23 |
42 |
lower_val |
zero_val |
auto[0] |
114 |
1 |
|
|
T23 |
1 |
|
T11 |
1 |
|
T28 |
1 |
lower_val |
zero_val |
auto[1] |
37879 |
1 |
|
|
T4 |
32 |
|
T5 |
3 |
|
T6 |
1 |
zero_val |
higher_val |
auto[0] |
622 |
1 |
|
|
T4 |
7 |
|
T11 |
2 |
|
T26 |
1 |
zero_val |
higher_val |
auto[1] |
180 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T161 |
1 |
zero_val |
lower_val |
auto[0] |
565 |
1 |
|
|
T4 |
5 |
|
T6 |
1 |
|
T11 |
2 |
zero_val |
lower_val |
auto[1] |
146 |
1 |
|
|
T4 |
1 |
|
T23 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[0] |
284 |
1 |
|
|
T5 |
1 |
|
T23 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[1] |
203 |
1 |
|
|
T23 |
1 |
|
T10 |
2 |
|
T34 |
1 |