Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10227	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9093	1			T4	19		T23	17		T10	38
len_5001_7500	14555	1			T4	38		T23	17		T10	36
len_2501_5000	9283	1			T4	5		T23	17		T10	36
len_1025_2500	5404	1			T4	9		T23	10		T10	22
len_769_1024	6594	1			T4	61		T23	2		T10	4
len_513_768	6811	1			T4	60		T23	2		T10	4
len_257_512	21262	1			T4	60		T23	2		T10	52
len_0_256	257481	1			T4	182		T5	9		T6	9
len_keccak_block_sizes[72]	714	1			T23	2		T10	3		T29	3
len_keccak_block_sizes[104]	614	1			T23	2		T10	3		T29	3
len_keccak_block_sizes[136]	514	1			T23	2		T10	3		T29	3
len_keccak_block_sizes[144]	423	1			T23	2		T10	3		T29	3
len_keccak_block_sizes[168]	314	1			T4	1		T10	3		T29	3
len_1	745	1			T4	1		T23	2		T10	3
len_0	1217	1			T4	3		T23	2		T10	3