Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100949608	1			T1	5		T56	5		T57	8
all_pins[1]	100949608	1			T1	5		T56	5		T57	8
all_pins[2]	100949608	1			T1	5		T56	5		T57	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	252527679	1			T1	9		T56	15		T57	17
values[0x1]	50321145	1			T1	6		T57	7		T62	2
transitions[0x0=>0x1]	49897348	1			T1	3		T57	5		T62	2
transitions[0x1=>0x0]	49897375	1			T1	3		T57	5		T62	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100441005	1			T1	3		T56	5		T57	6
all_pins[0]	values[0x1]	508603	1			T1	2		T57	2		T69	1
all_pins[0]	transitions[0x0=>0x1]	214936	1			T57	2		T69	1		T123	2
all_pins[0]	transitions[0x1=>0x0]	49188648	1			T1	1		T57	1		T62	2
all_pins[1]	values[0x0]	51467293	1			T1	2		T56	5		T57	7
all_pins[1]	values[0x1]	49482315	1			T1	3		T57	1		T62	2
all_pins[1]	transitions[0x0=>0x1]	49354184	1			T1	2		T62	2		T123	1
all_pins[1]	transitions[0x1=>0x0]	202096	1			T57	3		T69	2		T149	2
all_pins[2]	values[0x0]	100619381	1			T1	4		T56	5		T57	4
all_pins[2]	values[0x1]	330227	1			T1	1		T57	4		T69	2
all_pins[2]	transitions[0x0=>0x1]	328228	1			T1	1		T57	3		T69	1
all_pins[2]	transitions[0x1=>0x0]	506631	1			T1	2		T57	1		T123	2