Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	675	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5891	1			T4	53		T11	15		T25	6
len_601_800	12839	1			T4	93		T11	35		T25	13
len_401_600	8851	1			T4	82		T11	34		T25	20
len_201_400	16789	1			T4	44		T10	251		T11	14
len_65_200	73830	1			T4	63		T10	680		T11	38
len_min_for_xof_require_squeeze	991	1			T10	10		T11	1		T29	10
len_keccak_block_sizes[72]	753	1			T4	3		T10	5		T28	1
len_keccak_block_sizes[104]	743	1			T4	2		T10	5		T29	5
len_keccak_block_sizes[136]	763	1			T4	1		T10	5		T29	5
len_keccak_block_sizes[144]	293	1			T4	1		T10	5		T11	1
len_keccak_block_sizes[168]	280	1			T10	5		T28	1		T29	5
len_datapath_width	14319	1			T4	18		T5	3		T6	3
len_2_63	213024	1			T4	138		T5	6		T6	6
len_1	59	1			T11	2		T162	1		T163	2