Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11041068 |
1 |
|
|
T4 |
55824 |
|
T5 |
96 |
|
T6 |
96 |
auto[1] |
11040757 |
1 |
|
|
T4 |
55824 |
|
T5 |
96 |
|
T6 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21840749 |
1 |
|
|
T4 |
111092 |
|
T5 |
192 |
|
T6 |
192 |
triple_byte_access |
80184 |
1 |
|
|
T4 |
192 |
|
T10 |
620 |
|
T11 |
92 |
halfword_access |
80694 |
1 |
|
|
T4 |
170 |
|
T10 |
632 |
|
T11 |
84 |
byte_access |
80198 |
1 |
|
|
T4 |
194 |
|
T10 |
620 |
|
T11 |
72 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10920530 |
1 |
|
|
T4 |
55546 |
|
T5 |
96 |
|
T6 |
96 |
auto[0] |
triple_byte_access |
40092 |
1 |
|
|
T4 |
96 |
|
T10 |
310 |
|
T11 |
46 |
auto[0] |
halfword_access |
40347 |
1 |
|
|
T4 |
85 |
|
T10 |
316 |
|
T11 |
42 |
auto[0] |
byte_access |
40099 |
1 |
|
|
T4 |
97 |
|
T10 |
310 |
|
T11 |
36 |
auto[1] |
word_access |
10920219 |
1 |
|
|
T4 |
55546 |
|
T5 |
96 |
|
T6 |
96 |
auto[1] |
triple_byte_access |
40092 |
1 |
|
|
T4 |
96 |
|
T10 |
310 |
|
T11 |
46 |
auto[1] |
halfword_access |
40347 |
1 |
|
|
T4 |
85 |
|
T10 |
316 |
|
T11 |
42 |
auto[1] |
byte_access |
40099 |
1 |
|
|
T4 |
97 |
|
T10 |
310 |
|
T11 |
36 |