Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 266 1 T1 4 T56 4 T57 7
all_values[1] 266 1 T1 4 T56 4 T57 7
all_values[2] 266 1 T1 4 T56 4 T57 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 413 1 T1 6 T56 10 T57 11
auto[1] 385 1 T1 6 T56 2 T57 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356 1 T1 1 T56 4 T57 6
auto[1] 442 1 T1 11 T56 8 T57 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 501 1 T1 5 T56 7 T57 11
auto[1] 297 1 T1 7 T56 5 T57 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 70 1 T56 1 T57 2 T62 1
all_values[0] auto[0] auto[0] auto[1] 19 1 T56 1 T69 2 T124 2
all_values[0] auto[0] auto[1] auto[0] 58 1 T57 2 T62 2 T123 1
all_values[0] auto[0] auto[1] auto[1] 23 1 T1 1 T57 1 T123 1
all_values[0] auto[1] auto[0] auto[1] 49 1 T1 3 T56 2 T57 1
all_values[0] auto[1] auto[1] auto[1] 47 1 T57 1 T124 2 T149 3
all_values[1] auto[0] auto[0] auto[0] 67 1 T56 2 T62 2 T69 3
all_values[1] auto[0] auto[0] auto[1] 24 1 T56 1 T57 2 T124 1
all_values[1] auto[0] auto[1] auto[0] 46 1 T57 1 T123 1 T149 1
all_values[1] auto[0] auto[1] auto[1] 30 1 T1 1 T62 1 T124 1
all_values[1] auto[1] auto[0] auto[1] 49 1 T1 1 T56 1 T57 3
all_values[1] auto[1] auto[1] auto[1] 50 1 T1 2 T57 1 T62 1
all_values[2] auto[0] auto[0] auto[0] 59 1 T1 1 T57 1 T69 1
all_values[2] auto[0] auto[0] auto[1] 22 1 T1 1 T56 1 T124 1
all_values[2] auto[0] auto[1] auto[0] 56 1 T56 1 T62 2 T69 1
all_values[2] auto[0] auto[1] auto[1] 27 1 T1 1 T57 2 T69 1
all_values[2] auto[1] auto[0] auto[1] 54 1 T56 1 T57 2 T62 2
all_values[2] auto[1] auto[1] auto[1] 48 1 T1 1 T56 1 T57 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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