Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100306888	1			T58	5		T61	1		T65	1
all_values[1]	100306888	1			T58	5		T61	1		T65	1
all_values[2]	100306888	1			T58	5		T61	1		T65	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676014

1

T58

5

T61

3

T65

3

auto[1]

300244650

1

T58

10

T76

8

T104

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299393655

1

T58

9

T61

3

T65

3

auto[1]

1527009

1

T58

6

T76

15

T104

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	237917	1			T58	3		T61	1		T65	1
all_values[0]	auto[0]	auto[1]	2405	1			T58	2		T76	4		T104	3
all_values[0]	auto[1]	auto[0]	99559968	1			T76	1		T104	1		T106	5
all_values[0]	auto[1]	auto[1]	506598	1			T76	1		T104	4		T105	2
all_values[1]	auto[0]	auto[0]	232262	1			T61	1		T65	1		T76	3
all_values[1]	auto[0]	auto[1]	1803	1			T76	5		T104	2		T105	1
all_values[1]	auto[1]	auto[0]	99565623	1			T58	3		T104	1		T106	3
all_values[1]	auto[1]	auto[1]	507200	1			T58	2		T104	5		T105	1
all_values[2]	auto[0]	auto[0]	199726	1			T61	1		T65	1		T76	1
all_values[2]	auto[0]	auto[1]	1901	1			T76	1		T104	4		T105	1
all_values[2]	auto[1]	auto[0]	99598159	1			T58	3		T76	2		T105	3
all_values[2]	auto[1]	auto[1]	507102	1			T58	2		T76	4		T104	3