Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
357040 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T10 |
2 |
auto[1] |
334908 |
1 |
|
|
T5 |
386 |
|
T6 |
618 |
|
T12 |
124 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174000 |
1 |
|
|
T5 |
125 |
|
T6 |
150 |
|
T11 |
86 |
lower_val |
171235 |
1 |
|
|
T5 |
72 |
|
T6 |
155 |
|
T13 |
1 |
zero_val |
2045 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263180 |
1 |
|
|
T5 |
94 |
|
T6 |
128 |
|
T13 |
2 |
lower_val |
261168 |
1 |
|
|
T5 |
92 |
|
T6 |
152 |
|
T10 |
2 |
zero_val |
167600 |
1 |
|
|
T5 |
202 |
|
T6 |
340 |
|
T12 |
70 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45059 |
1 |
|
|
T11 |
45 |
|
T12 |
28 |
|
T42 |
1 |
higher_val |
higher_val |
auto[1] |
21183 |
1 |
|
|
T5 |
29 |
|
T6 |
31 |
|
T12 |
6 |
higher_val |
lower_val |
auto[0] |
44572 |
1 |
|
|
T11 |
41 |
|
T12 |
47 |
|
T43 |
71 |
higher_val |
lower_val |
auto[1] |
21066 |
1 |
|
|
T5 |
35 |
|
T6 |
36 |
|
T12 |
5 |
higher_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T5 |
1 |
|
T12 |
1 |
|
T37 |
3 |
higher_val |
zero_val |
auto[1] |
42030 |
1 |
|
|
T5 |
60 |
|
T6 |
83 |
|
T12 |
10 |
lower_val |
higher_val |
auto[0] |
44392 |
1 |
|
|
T13 |
1 |
|
T11 |
31 |
|
T12 |
41 |
lower_val |
higher_val |
auto[1] |
20881 |
1 |
|
|
T5 |
14 |
|
T6 |
28 |
|
T12 |
9 |
lower_val |
lower_val |
auto[0] |
43838 |
1 |
|
|
T11 |
34 |
|
T12 |
28 |
|
T43 |
61 |
lower_val |
lower_val |
auto[1] |
20798 |
1 |
|
|
T5 |
14 |
|
T6 |
39 |
|
T12 |
9 |
lower_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T12 |
2 |
|
T15 |
1 |
|
T171 |
1 |
lower_val |
zero_val |
auto[1] |
41224 |
1 |
|
|
T5 |
44 |
|
T6 |
88 |
|
T12 |
24 |
zero_val |
higher_val |
auto[0] |
615 |
1 |
|
|
T13 |
1 |
|
T11 |
1 |
|
T12 |
1 |
zero_val |
higher_val |
auto[1] |
174 |
1 |
|
|
T12 |
1 |
|
T56 |
1 |
|
T15 |
2 |
zero_val |
lower_val |
auto[0] |
572 |
1 |
|
|
T6 |
1 |
|
T10 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
160 |
1 |
|
|
T12 |
1 |
|
T37 |
1 |
|
T56 |
2 |
zero_val |
zero_val |
auto[0] |
270 |
1 |
|
|
T5 |
1 |
|
T12 |
1 |
|
T32 |
1 |
zero_val |
zero_val |
auto[1] |
254 |
1 |
|
|
T37 |
1 |
|
T44 |
2 |
|
T56 |
1 |