Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.66	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	3	18	85.71
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	3	6	66.67	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	0	7	100.00	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	635	1			T32	20		T33	28		T55	11
auto[CmdProcess]	81	1			T32	4		T33	1		T55	4
auto[CmdManualRun]	283	1			T32	13		T33	3		T55	9
auto[CmdDone]	1206	1			T32	45		T33	44		T55	35

---

Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	3	6	66.67

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T48	1		T52	1		T50	1
auto[ErrSwPushedMsgFifo]	37	1			T32	1		T55	1		T54	1
auto[ErrSwIssuedCmdInAppActive]	46	1			T32	2		T33	3		T54	1
auto[ErrUnexpectedModeStrength]	545	1			T32	20		T33	18		T55	14
auto[ErrIncorrectFunctionName]	532	1			T32	16		T33	23		T55	10
auto[ErrSwCmdSequence]	1062	1			T32	43		T33	32		T55	34

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	369	1			T32	17		T33	16		T55	16
auto[Shake]	329	1			T32	14		T33	11		T55	8
auto[CShake]	1524	1			T32	51		T33	49		T55	35

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	749	1			T32	27		T33	28		T55	20
auto[L224]	243	1			T32	18		T33	13		T55	2
auto[L256]	777	1			T32	27		T33	24		T55	18
auto[L384]	240	1			T32	6		T55	15		T54	5
auto[L512]	263	1			T32	4		T33	11		T55	4

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

45

1

T32

2

T33

3

T54

1

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	0	7	100.00

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	172	1			T32	6		T33	8		T55	5
shake_224_invalid_cfg	27	1			T32	2		T33	2		T156	1
shake_384_invalid_cfg	31	1			T32	2		T55	1		T26	1
shake_512_invalid_cfg	31	1			T33	2		T54	1		T26	1
cshake_224_invalid_cfg	98	1			T32	6		T33	3		T55	2
cshake_384_invalid_cfg	95	1			T32	2		T55	5		T54	3
cshake_512_invalid_cfg	91	1			T32	2		T33	3		T55	1