Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10211	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9218	1			T6	24		T11	29		T12	3
len_5001_7500	15022	1			T6	24		T11	65		T12	20
len_2501_5000	9353	1			T6	24		T11	24		T12	3
len_1025_2500	5484	1			T6	14		T11	11		T12	1
len_769_1024	6464	1			T5	45		T6	2		T11	1
len_513_768	6816	1			T5	42		T6	3		T11	1
len_257_512	21083	1			T5	51		T6	2		T11	1
len_0_256	255434	1			T5	56		T6	211		T11	15
len_keccak_block_sizes[72]	715	1			T6	2		T32	1		T43	2
len_keccak_block_sizes[104]	618	1			T5	1		T6	2		T33	1
len_keccak_block_sizes[136]	523	1			T33	1		T36	3		T38	1
len_keccak_block_sizes[144]	418	1			T33	1		T36	3		T44	1
len_keccak_block_sizes[168]	312	1			T5	1		T32	1		T36	3
len_1	763	1			T6	2		T43	2		T36	3
len_0	1249	1			T6	2		T11	6		T12	5