Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16803295	1			T5	46789		T11	184745		T12	40774
shake	56674137	1			T5	15497		T11	60112		T12	27249
sha3	35551372	1			T5	468		T6	158821		T11	4101

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Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92224368

1

T5

15965

T6

158821

T11

64213

auto[1]

16804436

1

T5

46789

T11

184745

T12

40773

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	92937623	1			T5	51414		T6	103898		T11	190775
depth[0x01]	3655670	1			T5	1620		T6	11969		T11	12153
depth[0x02]	3157731	1			T5	1631		T6	13124		T11	12839
depth[0x03]	2940733	1			T5	1580		T6	12415		T11	12298
depth[0x04]	2617175	1			T5	1390		T6	11606		T11	10685
depth[0x05]	1490251	1			T5	870		T6	5808		T11	5820
depth[0x06]	455946	1			T5	429		T6	1		T11	1498
depth[0x07]	368504	1			T5	314		T11	222		T12	129
depth[0x08]	363142	1			T5	425		T11	325		T12	170
depth[0x09]	341420	1			T5	297		T11	215		T12	115
depth[0x0a]	700609	1			T5	2784		T11	2128		T12	1224

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16091181

1

T5

11340

T6

54923

T11

58183

auto[1]

92937623

1

T5

51414

T6

103898

T11

190775

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108328195

1

T5

59970

T6

158821

T11

246830

auto[1]

700609

1

T5

2784

T11

2128

T12

1224