Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100306888	1			T58	5		T61	1		T65	1
all_pins[1]	100306888	1			T58	5		T61	1		T65	1
all_pins[2]	100306888	1			T58	5		T61	1		T65	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	249725701	1			T58	13		T61	3		T65	3
values[0x1]	51194963	1			T58	2		T76	3		T104	8
transitions[0x0=>0x1]	50772508	1			T58	2		T76	2		T104	7
transitions[0x1=>0x0]	50772529	1			T58	2		T76	3		T104	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99800290	1			T58	5		T61	1		T65	1
all_pins[0]	values[0x1]	506598	1			T76	1		T104	4		T105	2
all_pins[0]	transitions[0x0=>0x1]	213256	1			T76	1		T104	3		T105	2
all_pins[0]	transitions[0x1=>0x0]	50069173	1			T104	2		T106	1		T151	1
all_pins[1]	values[0x0]	49944373	1			T58	5		T61	1		T65	1
all_pins[1]	values[0x1]	50362515	1			T104	3		T106	1		T162	2
all_pins[1]	transitions[0x0=>0x1]	50235375	1			T104	3		T106	1		T162	2
all_pins[1]	transitions[0x1=>0x0]	198710	1			T58	2		T76	2		T104	1
all_pins[2]	values[0x0]	99981038	1			T58	3		T61	1		T65	1
all_pins[2]	values[0x1]	325850	1			T58	2		T76	2		T104	1
all_pins[2]	transitions[0x0=>0x1]	323877	1			T58	2		T76	1		T104	1
all_pins[2]	transitions[0x1=>0x0]	504646	1			T76	1		T104	4		T162	2