Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	682	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5759	1			T5	29		T11	23		T12	9
len_601_800	13235	1			T5	65		T11	53		T12	33
len_401_600	8752	1			T5	47		T11	36		T12	18
len_201_400	16636	1			T5	25		T11	13		T12	11
len_65_200	72922	1			T5	17		T11	13		T12	32
len_min_for_xof_require_squeeze	991	1			T32	1		T36	10		T37	1
len_keccak_block_sizes[72]	733	1			T36	5		T56	1		T30	5
len_keccak_block_sizes[104]	756	1			T34	1		T36	5		T99	1
len_keccak_block_sizes[136]	739	1			T5	1		T36	5		T37	2
len_keccak_block_sizes[144]	291	1			T5	1		T36	5		T37	1
len_keccak_block_sizes[168]	285	1			T36	5		T37	1		T30	5
len_datapath_width	14341	1			T12	9		T43	246		T36	5
len_2_63	211832	1			T5	9		T6	310		T11	7
len_1	57	1			T12	2		T15	1		T81	1