Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	236	1			T58	4		T76	7		T104	7
all_values[1]	236	1			T58	4		T76	7		T104	7
all_values[2]	236	1			T58	4		T76	7		T104	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

372

1

T58

6

T76

13

T104

11

auto[1]

336

1

T58

6

T76

8

T104

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302

1

T58

5

T76

7

T104

5

auto[1]

406

1

T58

7

T76

14

T104

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

438

1

T58

7

T76

12

T104

14

auto[1]

270

1

T58

5

T76

9

T104

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

47

1

T58

2

T76

1

T105

1

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T58

1

T76

2

T151

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T106

5

T162

1

T152

1

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T76

2

T104

4

T162

1

all_values[0]

auto[1]

auto[0]

auto[1]

49

1

T58

1

T76

2

T104

3

all_values[0]

auto[1]

auto[1]

auto[1]

41

1

T105

2

T162

1

T152

2

all_values[1]

auto[0]

auto[0]

auto[0]

60

1

T76

3

T105

4

T151

1

all_values[1]

auto[0]

auto[0]

auto[1]

15

1

T104

1

T106

1

T153

1

all_values[1]

auto[0]

auto[1]

auto[0]

41

1

T58

2

T104

1

T106

2

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T104

2

T162

1

T152

1

all_values[1]

auto[1]

auto[0]

auto[1]

48

1

T58

1

T76

4

T104

3

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T58

1

T106

1

T162

1

all_values[2]

auto[0]

auto[0]

auto[0]

65

1

T76

1

T104

3

T105

1

all_values[2]

auto[0]

auto[0]

auto[1]

18

1

T104

1

T151

1

T152

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T58

1

T76

2

T104

1

all_values[2]

auto[0]

auto[1]

auto[1]

28

1

T58

1

T76

1

T104

1

all_values[2]

auto[1]

auto[0]

auto[1]

43

1

T58

1

T151

1

T152

4

all_values[2]

auto[1]

auto[1]

auto[1]

39

1

T58

1

T76

3

T104

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal