Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.77	98.38	93.15	99.93	92.73	96.04	98.89	98.31

Total test records in report: 1258

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3071244285			Jan 03 12:44:25 PM PST 24	Jan 03 12:45:53 PM PST 24	91443722 ps
T1252	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3356737403			Jan 03 12:44:30 PM PST 24	Jan 03 12:45:52 PM PST 24	59351959 ps
T1253	/workspace/coverage/cover_reg_top/16.kmac_intr_test.1819187570			Jan 03 12:44:34 PM PST 24	Jan 03 12:45:56 PM PST 24	38105296 ps
T1254	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2833055758			Jan 03 12:44:32 PM PST 24	Jan 03 12:46:02 PM PST 24	835002577 ps
T1255	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3214718637			Jan 03 12:44:21 PM PST 24	Jan 03 12:45:53 PM PST 24	27814528 ps
T1256	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2883462767			Jan 03 12:44:55 PM PST 24	Jan 03 12:46:28 PM PST 24	181796082 ps
T1257	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2407783091			Jan 03 12:44:55 PM PST 24	Jan 03 12:46:21 PM PST 24	57671887 ps
T1258	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1543510136			Jan 03 12:44:17 PM PST 24	Jan 03 12:45:44 PM PST 24	144271159 ps

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.219682239
Short name	T12
Test name
Test status
Simulation time	84608851185 ps
CPU time	930.71 seconds
Started	Jan 03 01:19:49 PM PST 24
Finished	Jan 03 01:35:26 PM PST 24
Peak memory	323716 kb
Host	smart-2ae026b3-a404-4c5b-bcb5-5fb76ccb395e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=219682239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.219682239 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2719542237
Short name	T1
Test name
Test status
Simulation time	58601025 ps
CPU time	1.28 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:16 PM PST 24
Peak memory	225088 kb
Host	smart-237540e2-4a5c-45d0-b475-152887c79274
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719542237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.2719542237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3619630232
Short name	T2
Test name
Test status
Simulation time	258099439 ps
CPU time	5.3 seconds
Started	Jan 03 12:44:09 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	217652 kb
Host	smart-634b3226-658d-404b-8154-7037e5f20bf9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619630232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.36196 30232 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/30.kmac_stress_all_with_rand_reset.696099379
Short name	T15
Test name
Test status
Simulation time	34754617804 ps
CPU time	1038.67 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:41:28 PM PST 24
Peak memory	317400 kb
Host	smart-35e4fbac-7428-4757-9388-d91673928b13
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=696099379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.696099379 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3680849778
Short name	T151
Test name
Test status
Simulation time	26673072 ps
CPU time	0.81 seconds
Started	Jan 03 12:44:47 PM PST 24
Finished	Jan 03 12:46:10 PM PST 24
Peak memory	217368 kb
Host	smart-48d95525-5116-46c4-a3d1-8a708227bd64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680849778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3680849778 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.261154086
Short name	T7
Test name
Test status
Simulation time	41227626909 ps
CPU time	48.14 seconds
Started	Jan 03 01:19:40 PM PST 24
Finished	Jan 03 01:20:33 PM PST 24
Peak memory	274900 kb
Host	smart-6c71ea3b-cffa-435f-a3e4-4ba6cbb8e35f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261154086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.261154086 +enable_masking =1 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/35.kmac_error.3948447335
Short name	T32
Test name
Test status
Simulation time	3803086531 ps
CPU time	296.73 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:29:07 PM PST 24
Peak memory	259660 kb
Host	smart-0585668e-0798-4771-a72c-31091a6f4675
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948447335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3948447335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.348395279
Short name	T61
Test name
Test status
Simulation time	225967665 ps
CPU time	1.98 seconds
Started	Jan 03 12:44:38 PM PST 24
Finished	Jan 03 12:46:01 PM PST 24
Peak memory	216972 kb
Host	smart-6a91056d-a59b-456a-96e8-dbecf453736f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348395279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.348395279 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2404341440
Short name	T119
Test name
Test status
Simulation time	279554496 ps
CPU time	5.74 seconds
Started	Jan 03 12:44:32 PM PST 24
Finished	Jan 03 12:45:58 PM PST 24
Peak memory	217740 kb
Host	smart-0a31ec74-797d-4b93-823c-f65c4d3f1bfb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404341440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2404 341440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.256515263
Short name	T92
Test name
Test status
Simulation time	23170096 ps
CPU time	0.99 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:05 PM PST 24
Peak memory	217684 kb
Host	smart-954323e0-4dbc-4408-89ce-4be072893079
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256515263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e rrors.256515263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/23.kmac_key_error.118447280
Short name	T48
Test name
Test status
Simulation time	4021297200 ps
CPU time	6.51 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:24:06 PM PST 24
Peak memory	218824 kb
Host	smart-900cd072-e54c-4f6d-aa0e-49d71845c398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118447280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.118447280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1221524925
Short name	T79
Test name
Test status
Simulation time	18992903 ps
CPU time	1.38 seconds
Started	Jan 03 12:44:49 PM PST 24
Finished	Jan 03 12:46:28 PM PST 24
Peak memory	217584 kb
Host	smart-59595d00-6424-495b-96c4-1b4320824991
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221524925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.1221524925 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.4008652268
Short name	T30
Test name
Test status
Simulation time	55625610403 ps
CPU time	4166.27 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 02:33:33 PM PST 24
Peak memory	579144 kb
Host	smart-14a71455-8e08-405b-86b4-c6c4e1a29d49
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4008652268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.4008652268 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.3652926351
Short name	T46
Test name
Test status
Simulation time	8094200361 ps
CPU time	81.98 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 01:22:22 PM PST 24
Peak memory	221864 kb
Host	smart-cbacb719-cb93-4902-a29a-9f7c627de770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652926351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3652926351 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.568840085
Short name	T22
Test name
Test status
Simulation time	605454565294 ps
CPU time	1534.71 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:49:33 PM PST 24
Peak memory	388704 kb
Host	smart-8f8b6b2e-df20-4ad3-90e8-098af1cf1ed4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=568840085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.568840085 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.906575956
Short name	T45
Test name
Test status
Simulation time	334895666 ps
CPU time	1.18 seconds
Started	Jan 03 01:20:12 PM PST 24
Finished	Jan 03 01:20:17 PM PST 24
Peak memory	218724 kb
Host	smart-88eab211-f5bd-47ff-b4f7-aa6cd8687c30
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=906575956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.906575956 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.642688538
Short name	T162
Test name
Test status
Simulation time	34657948 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:26 PM PST 24
Peak memory	216568 kb
Host	smart-63011046-fe2b-49d8-86d2-2b1c9f7ec932
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642688538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.642688538 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/default/42.kmac_error.1659887005
Short name	T26
Test name
Test status
Simulation time	9088299934 ps
CPU time	222.53 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:28:46 PM PST 24
Peak memory	252892 kb
Host	smart-f821035c-6f73-4cf7-adc4-07dcb52a18e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659887005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1659887005 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.604504932
Short name	T39
Test name
Test status
Simulation time	17365420176 ps
CPU time	317.06 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 01:29:45 PM PST 24
Peak memory	251572 kb
Host	smart-59f6a02b-34ea-478d-b1ff-85f90b6dd013
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604504932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.604504932 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.131474949
Short name	T74
Test name
Test status
Simulation time	244352449 ps
CPU time	2.65 seconds
Started	Jan 03 12:44:53 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	220736 kb
Host	smart-453fb244-c9e6-4c3b-b390-a200bd482aa1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131474949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac _shadow_reg_errors_with_csr_rw.131474949 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1124632493
Short name	T1194
Test name
Test status
Simulation time	103519877 ps
CPU time	4.24 seconds
Started	Jan 03 12:44:09 PM PST 24
Finished	Jan 03 12:45:37 PM PST 24
Peak memory	217572 kb
Host	smart-23dee04e-20fd-4b25-acc4-7d4796d9c30b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124632493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.11246 32493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.808649143
Short name	T57
Test name
Test status
Simulation time	54252092 ps
CPU time	1.14 seconds
Started	Jan 03 01:19:17 PM PST 24
Finished	Jan 03 01:19:22 PM PST 24
Peak memory	218624 kb
Host	smart-6913a810-b81e-4518-a177-6dc96d7ce7b4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=808649143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.808649143 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.1823270351
Short name	T1180
Test name
Test status
Simulation time	48167560 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:45 PM PST 24
Finished	Jan 03 12:46:22 PM PST 24
Peak memory	217392 kb
Host	smart-d0e033c6-b6bb-4c26-8cff-e424e701708a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823270351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1823270351 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2833055758
Short name	T1254
Test name
Test status
Simulation time	835002577 ps
CPU time	4.96 seconds
Started	Jan 03 12:44:32 PM PST 24
Finished	Jan 03 12:46:02 PM PST 24
Peak memory	217536 kb
Host	smart-6d2dab28-ca0d-46f4-9925-7a3c05acc385
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833055758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2833 055758 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1178692252
Short name	T164
Test name
Test status
Simulation time	199814371 ps
CPU time	5.13 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:39 PM PST 24
Peak memory	217708 kb
Host	smart-fd601bfe-8bf6-4421-8e34-e98ab7a2665b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178692252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1178 692252 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_app.3073975159
Short name	T157
Test name
Test status
Simulation time	10043145299 ps
CPU time	292.45 seconds
Started	Jan 03 01:19:41 PM PST 24
Finished	Jan 03 01:24:39 PM PST 24
Peak memory	249476 kb
Host	smart-5e31ff5f-1a99-41d2-a957-114d085090ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073975159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3073975159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.513562477
Short name	T250
Test name
Test status
Simulation time	46585614 ps
CPU time	0.86 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:23:48 PM PST 24
Peak memory	218660 kb
Host	smart-663a7cbe-143d-4ff2-ac3f-5b10fa3620fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513562477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.513562477 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.2691383765
Short name	T14
Test name
Test status
Simulation time	53539644 ps
CPU time	1.42 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:23:48 PM PST 24
Peak memory	218796 kb
Host	smart-1f73f430-4c50-4472-8935-2c37d0a7bb1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691383765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2691383765 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_error.4202520193
Short name	T381
Test name
Test status
Simulation time	57557217286 ps
CPU time	493.95 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:27:30 PM PST 24
Peak memory	267960 kb
Host	smart-30769588-8440-4955-918f-4133d54e0d76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202520193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.4202520193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3891187054
Short name	T1220
Test name
Test status
Simulation time	613024190 ps
CPU time	9.34 seconds
Started	Jan 03 12:44:02 PM PST 24
Finished	Jan 03 12:45:30 PM PST 24
Peak memory	217628 kb
Host	smart-fdbbb972-546c-4ea8-b8c3-99a43cec6331
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891187054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3891187 054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.57726920
Short name	T125
Test name
Test status
Simulation time	167177905 ps
CPU time	9.05 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:55 PM PST 24
Peak memory	216928 kb
Host	smart-fe40c012-6683-4d91-bdfa-ef5f2100dcdd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57726920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.57726920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1778013164
Short name	T175
Test name
Test status
Simulation time	19854558 ps
CPU time	0.95 seconds
Started	Jan 03 12:44:09 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	217528 kb
Host	smart-6cd37def-6d33-42f2-928d-ddbee39504d4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778013164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1778013 164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.324355239
Short name	T70
Test name
Test status
Simulation time	188921585 ps
CPU time	1.78 seconds
Started	Jan 03 12:44:50 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	222756 kb
Host	smart-4e95568b-750b-4807-9fee-6ec57477f631
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324355239 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.324355239 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2709366309
Short name	T132
Test name
Test status
Simulation time	60232256 ps
CPU time	1.09 seconds
Started	Jan 03 12:44:08 PM PST 24
Finished	Jan 03 12:45:26 PM PST 24
Peak memory	217008 kb
Host	smart-351b9426-c39f-4a59-8f84-d351d79122ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709366309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2709366309 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.3904741260
Short name	T1207
Test name
Test status
Simulation time	73127411 ps
CPU time	0.83 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:44 PM PST 24
Peak memory	216540 kb
Host	smart-eb6977dd-abf8-494c-a91f-63d6d43a7e45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904741260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3904741260 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2030464773
Short name	T137
Test name
Test status
Simulation time	75953366 ps
CPU time	1.46 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	217596 kb
Host	smart-76b0c367-072c-4e4f-a739-7c54523bff31
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030464773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.2030464773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.4184499445
Short name	T1143
Test name
Test status
Simulation time	13126934 ps
CPU time	0.72 seconds
Started	Jan 03 12:45:01 PM PST 24
Finished	Jan 03 12:46:29 PM PST 24
Peak memory	217344 kb
Host	smart-3e0c9267-b162-4bbd-b4a7-846ccc0c9cad
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184499445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4184499445 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1361701460
Short name	T130
Test name
Test status
Simulation time	29975592 ps
CPU time	1.46 seconds
Started	Jan 03 12:44:14 PM PST 24
Finished	Jan 03 12:45:38 PM PST 24
Peak memory	216800 kb
Host	smart-9ee2afa5-6a8d-4c55-87a1-03e949fb41d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361701460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1361701460 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.4277457479
Short name	T97
Test name
Test status
Simulation time	33290510 ps
CPU time	1.06 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:44 PM PST 24
Peak memory	218188 kb
Host	smart-2edfa6df-512f-4533-aeba-949b2d342166
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277457479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.4277457479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.924314813
Short name	T1200
Test name
Test status
Simulation time	108398056 ps
CPU time	2.69 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:45:44 PM PST 24
Peak memory	217612 kb
Host	smart-4b413c8a-f07b-44be-b7ac-20e2debe7f4d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924314813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.924314813 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.2384359357
Short name	T1206
Test name
Test status
Simulation time	503411323 ps
CPU time	3.58 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:52 PM PST 24
Peak memory	217100 kb
Host	smart-5da131b9-5a53-476c-a9ef-1e0e3384496f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384359357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2384359357 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3361750150
Short name	T166
Test name
Test status
Simulation time	176258158 ps
CPU time	3.08 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	216944 kb
Host	smart-6e2c4b9d-c1de-4a48-8435-d14b37c0eff8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361750150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.33617 50150 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.560288056
Short name	T1149
Test name
Test status
Simulation time	684234057 ps
CPU time	10.75 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:42 PM PST 24
Peak memory	217572 kb
Host	smart-f1cac4bb-f1f7-49ea-98c3-38c0311cf800
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560288056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.56028805 6 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.332442894
Short name	T1172
Test name
Test status
Simulation time	1207111655 ps
CPU time	16.78 seconds
Started	Jan 03 12:44:21 PM PST 24
Finished	Jan 03 12:46:09 PM PST 24
Peak memory	217708 kb
Host	smart-4ae7b49c-5427-4631-a44e-996d6fccb0ff
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332442894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.33244289 4 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.459875766
Short name	T1247
Test name
Test status
Simulation time	64230291 ps
CPU time	1.11 seconds
Started	Jan 03 12:44:12 PM PST 24
Finished	Jan 03 12:45:36 PM PST 24
Peak memory	217660 kb
Host	smart-911c48f2-5815-4e44-b08c-3a5d0a317f0d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459875766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.45987576 6 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1781777641
Short name	T1168
Test name
Test status
Simulation time	106689345 ps
CPU time	1.8 seconds
Started	Jan 03 12:44:05 PM PST 24
Finished	Jan 03 12:45:38 PM PST 24
Peak memory	221572 kb
Host	smart-024bb280-4634-455a-8122-bd9fc20fbf48
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781777641 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1781777641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.4256949381
Short name	T1148
Test name
Test status
Simulation time	18518158 ps
CPU time	1.02 seconds
Started	Jan 03 12:45:50 PM PST 24
Finished	Jan 03 12:47:19 PM PST 24
Peak memory	217360 kb
Host	smart-2e20b5a8-6885-4b3e-8497-5ab451fc947f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256949381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4256949381 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2854413047
Short name	T1182
Test name
Test status
Simulation time	13587040 ps
CPU time	0.79 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:45:42 PM PST 24
Peak memory	217468 kb
Host	smart-4be1ed92-673a-467d-a3fc-4ec13dd53b4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854413047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2854413047 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.397645865
Short name	T1198
Test name
Test status
Simulation time	58415094 ps
CPU time	0.75 seconds
Started	Jan 03 12:44:20 PM PST 24
Finished	Jan 03 12:45:52 PM PST 24
Peak memory	217288 kb
Host	smart-29e4aca6-d854-4009-9656-16dda5573b44
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397645865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.397645865 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1613784432
Short name	T1188
Test name
Test status
Simulation time	372195707 ps
CPU time	2.73 seconds
Started	Jan 03 12:44:50 PM PST 24
Finished	Jan 03 12:46:33 PM PST 24
Peak memory	217624 kb
Host	smart-02a49cf8-96d7-4ebe-9659-0a356cffff4a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613784432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.1613784432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1431856334
Short name	T91
Test name
Test status
Simulation time	15807920 ps
CPU time	0.97 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	217344 kb
Host	smart-062df05d-9cac-4009-8629-792efd0c09ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431856334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.1431856334 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.131959347
Short name	T136
Test name
Test status
Simulation time	260613155 ps
CPU time	2.07 seconds
Started	Jan 03 12:44:04 PM PST 24
Finished	Jan 03 12:45:20 PM PST 24
Peak memory	220836 kb
Host	smart-fb745bd4-ec1a-41ec-a1da-c1e99cf83fb7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131959347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.131959347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2235734457
Short name	T1210
Test name
Test status
Simulation time	86464157 ps
CPU time	2.8 seconds
Started	Jan 03 12:44:16 PM PST 24
Finished	Jan 03 12:45:33 PM PST 24
Peak memory	216768 kb
Host	smart-fa737665-cd0b-4037-a433-c00b32aa5b52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235734457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2235734457 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.220420386
Short name	T68
Test name
Test status
Simulation time	27232784 ps
CPU time	1.92 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:22 PM PST 24
Peak memory	222980 kb
Host	smart-bb3d535d-33fd-45df-9ba7-ee9f89c30656
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220420386 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.220420386 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.668315489
Short name	T1165
Test name
Test status
Simulation time	22086294 ps
CPU time	0.99 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:11 PM PST 24
Peak memory	216832 kb
Host	smart-c9329d07-36a6-4ebc-8ea5-1938403620e6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668315489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.668315489 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2791479791
Short name	T1162
Test name
Test status
Simulation time	206214868 ps
CPU time	2.73 seconds
Started	Jan 03 12:44:26 PM PST 24
Finished	Jan 03 12:45:56 PM PST 24
Peak memory	216872 kb
Host	smart-11f5a277-08bc-4060-aedd-5b6a52e17353
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791479791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.2791479791 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1461122867
Short name	T90
Test name
Test status
Simulation time	21470570 ps
CPU time	1.06 seconds
Started	Jan 03 12:44:27 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	225028 kb
Host	smart-41a0e88a-6061-45b4-8a5c-5db7234da3fe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461122867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.1461122867 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.61655593
Short name	T96
Test name
Test status
Simulation time	50898904 ps
CPU time	2.55 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	225000 kb
Host	smart-b5d8daa6-82d2-47be-9867-30853c132287
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61655593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_ shadow_reg_errors_with_csr_rw.61655593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3916358206
Short name	T62
Test name
Test status
Simulation time	25214863 ps
CPU time	1.49 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:15 PM PST 24
Peak memory	220700 kb
Host	smart-98808015-4948-4913-8478-e8107e786786
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916358206 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3916358206 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.1207896511
Short name	T1241
Test name
Test status
Simulation time	69010794 ps
CPU time	0.95 seconds
Started	Jan 03 12:45:00 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	217396 kb
Host	smart-446f66a2-6254-4d64-9383-31ff6aad1a59
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207896511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1207896511 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.546908820
Short name	T105
Test name
Test status
Simulation time	17234491 ps
CPU time	0.74 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:18 PM PST 24
Peak memory	217424 kb
Host	smart-f2d097ff-af2b-40c1-8a59-c1293ad9d4ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546908820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.546908820 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.688249114
Short name	T1214
Test name
Test status
Simulation time	194032791 ps
CPU time	2.63 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:51 PM PST 24
Peak memory	217640 kb
Host	smart-c9397deb-3ace-4c11-82c3-95d04a59274d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688249114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr _outstanding.688249114 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1891920270
Short name	T88
Test name
Test status
Simulation time	26488240 ps
CPU time	1.16 seconds
Started	Jan 03 12:44:27 PM PST 24
Finished	Jan 03 12:45:56 PM PST 24
Peak memory	218024 kb
Host	smart-cc05e1f8-91e1-4504-8b16-a8970ca3a792
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891920270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.1891920270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3071244285
Short name	T1251
Test name
Test status
Simulation time	91443722 ps
CPU time	1.62 seconds
Started	Jan 03 12:44:25 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	220476 kb
Host	smart-7a869e56-76d1-4eea-917f-1661348b69cf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071244285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.3071244285 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.3212678201
Short name	T1191
Test name
Test status
Simulation time	68316992 ps
CPU time	2.33 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:23 PM PST 24
Peak memory	217664 kb
Host	smart-4a4bf056-b4ad-4176-9ebb-df8b3654c4d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212678201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3212678201 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1887371202
Short name	T167
Test name
Test status
Simulation time	226981931 ps
CPU time	3.03 seconds
Started	Jan 03 12:44:25 PM PST 24
Finished	Jan 03 12:45:55 PM PST 24
Peak memory	217812 kb
Host	smart-24e7221e-2304-464d-bba8-4ca7bc79f87a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887371202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1887 371202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3030539485
Short name	T1217
Test name
Test status
Simulation time	31447064 ps
CPU time	1.17 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:08 PM PST 24
Peak memory	216708 kb
Host	smart-cddc00d2-7e1f-4449-9ab1-2aa890edda4a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030539485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3030539485 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.348806815
Short name	T1245
Test name
Test status
Simulation time	26780231 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:30 PM PST 24
Finished	Jan 03 12:45:47 PM PST 24
Peak memory	217364 kb
Host	smart-50852d9b-86cf-4568-a15c-83a3c5a7031f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348806815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.348806815 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2349683393
Short name	T1164
Test name
Test status
Simulation time	48632379 ps
CPU time	2.41 seconds
Started	Jan 03 12:44:59 PM PST 24
Finished	Jan 03 12:46:28 PM PST 24
Peak memory	217444 kb
Host	smart-0a628f38-f76f-493f-ae86-c76f8b069ad5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349683393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.2349683393 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4096355331
Short name	T1184
Test name
Test status
Simulation time	34604417 ps
CPU time	1.35 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:19 PM PST 24
Peak memory	218896 kb
Host	smart-8e21e5fe-40ea-4761-8791-66414943184b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096355331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.4096355331 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.85038152
Short name	T1233
Test name
Test status
Simulation time	56535915 ps
CPU time	2.52 seconds
Started	Jan 03 12:44:33 PM PST 24
Finished	Jan 03 12:45:57 PM PST 24
Peak memory	220788 kb
Host	smart-598019df-3cea-48b8-90a7-34bec1c25734
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85038152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_ shadow_reg_errors_with_csr_rw.85038152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.3604122915
Short name	T1163
Test name
Test status
Simulation time	475011067 ps
CPU time	3.05 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:28 PM PST 24
Peak memory	218004 kb
Host	smart-853593c3-2cf9-4c0d-9f39-082b2c068e99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604122915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3604122915 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1389506546
Short name	T1141
Test name
Test status
Simulation time	104105477 ps
CPU time	2.52 seconds
Started	Jan 03 12:44:44 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	223616 kb
Host	smart-b7390c10-f071-4935-9710-9f8228005af9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389506546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1389 506546 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2481051597
Short name	T1186
Test name
Test status
Simulation time	42543946 ps
CPU time	1.99 seconds
Started	Jan 03 12:44:29 PM PST 24
Finished	Jan 03 12:45:50 PM PST 24
Peak memory	222928 kb
Host	smart-d999c588-82a4-4411-bc50-5831a07c0c43
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481051597 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2481051597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.1297320631
Short name	T1179
Test name
Test status
Simulation time	46194872 ps
CPU time	0.94 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:49 PM PST 24
Peak memory	217528 kb
Host	smart-61c62528-d815-4950-ae02-adfbf28c29c7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297320631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1297320631 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1485154889
Short name	T76
Test name
Test status
Simulation time	19720965 ps
CPU time	0.84 seconds
Started	Jan 03 12:45:07 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	217388 kb
Host	smart-d41cf135-7cf0-4dd9-8ece-2ab914da465b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485154889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1485154889 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1580109333
Short name	T127
Test name
Test status
Simulation time	43335765 ps
CPU time	2.32 seconds
Started	Jan 03 12:45:00 PM PST 24
Finished	Jan 03 12:46:31 PM PST 24
Peak memory	217652 kb
Host	smart-b29edcdd-29b7-4071-b28d-3cc137fdde49
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580109333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.1580109333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.4129527340
Short name	T1189
Test name
Test status
Simulation time	139072844 ps
CPU time	1.49 seconds
Started	Jan 03 12:45:02 PM PST 24
Finished	Jan 03 12:46:36 PM PST 24
Peak memory	218528 kb
Host	smart-be695eb4-c5a1-43ed-85ea-ec49c514b10c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129527340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.4129527340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3145054192
Short name	T93
Test name
Test status
Simulation time	58953318 ps
CPU time	1.59 seconds
Started	Jan 03 12:44:20 PM PST 24
Finished	Jan 03 12:46:03 PM PST 24
Peak memory	216828 kb
Host	smart-0842ad1e-6314-44e5-8434-3fc09b4f8a92
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145054192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3145054192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.2861756843
Short name	T1183
Test name
Test status
Simulation time	299882539 ps
CPU time	2.59 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:13 PM PST 24
Peak memory	217844 kb
Host	smart-6934baa4-5a78-4c14-9632-7e3cd8343bb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861756843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2861756843 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1163975299
Short name	T168
Test name
Test status
Simulation time	105872087 ps
CPU time	4.41 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:26 PM PST 24
Peak memory	217636 kb
Host	smart-d2f1c70b-1f4d-4a51-90d3-2a5fe5e7ac71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163975299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1163 975299 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.390091719
Short name	T1212
Test name
Test status
Simulation time	52378506 ps
CPU time	1.21 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:02 PM PST 24
Peak memory	217652 kb
Host	smart-40245bd8-fbd8-4771-8dd0-7d0e68501cfc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390091719 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.390091719 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2407783091
Short name	T1257
Test name
Test status
Simulation time	57671887 ps
CPU time	1.09 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	217560 kb
Host	smart-691f1fc3-f9d4-4655-9891-60af459769e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407783091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2407783091 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1942907856
Short name	T1223
Test name
Test status
Simulation time	104197912 ps
CPU time	2.56 seconds
Started	Jan 03 12:44:50 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	216800 kb
Host	smart-06831ffd-5522-4862-a27c-fab930b549cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942907856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.1942907856 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1005194768
Short name	T1235
Test name
Test status
Simulation time	13473034 ps
CPU time	0.83 seconds
Started	Jan 03 12:44:51 PM PST 24
Finished	Jan 03 12:46:13 PM PST 24
Peak memory	216704 kb
Host	smart-f27109a4-ff6b-4b2a-bd57-5fd3bb95d363
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005194768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.1005194768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1862832526
Short name	T1167
Test name
Test status
Simulation time	119361091 ps
CPU time	2.11 seconds
Started	Jan 03 12:44:35 PM PST 24
Finished	Jan 03 12:45:58 PM PST 24
Peak memory	217916 kb
Host	smart-5b58323d-1de6-4a9c-a924-a9c27459d567
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862832526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1862832526 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2070902012
Short name	T73
Test name
Test status
Simulation time	30203274 ps
CPU time	2.01 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:02 PM PST 24
Peak memory	223660 kb
Host	smart-903abf7e-0d0f-4047-b415-b5ec98ca0b37
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070902012 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2070902012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3674209687
Short name	T1150
Test name
Test status
Simulation time	29836889 ps
CPU time	0.98 seconds
Started	Jan 03 12:44:59 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	216476 kb
Host	smart-d326ce76-b07b-43b4-998e-d42d092e704b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674209687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3674209687 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.1511682723
Short name	T1178
Test name
Test status
Simulation time	97376230 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:39 PM PST 24
Finished	Jan 03 12:46:04 PM PST 24
Peak memory	216552 kb
Host	smart-7371ba55-f77a-49be-905a-1c49354660d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511682723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1511682723 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2970616915
Short name	T145
Test name
Test status
Simulation time	53705608 ps
CPU time	1.52 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:39 PM PST 24
Peak memory	217444 kb
Host	smart-b5f4f761-535b-4ffb-b44e-c99eeaeb8ec6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970616915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2970616915 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1811003674
Short name	T1219
Test name
Test status
Simulation time	45138839 ps
CPU time	1.3 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:08 PM PST 24
Peak memory	218852 kb
Host	smart-48912b28-9c41-4b79-90da-9c52e03f169e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811003674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.1811003674 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4188620886
Short name	T1174
Test name
Test status
Simulation time	285516412 ps
CPU time	1.95 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:09 PM PST 24
Peak memory	220772 kb
Host	smart-7ea58af7-605c-4a1d-bfb4-5206cdab257e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188620886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.4188620886 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2401962414
Short name	T67
Test name
Test status
Simulation time	254136909 ps
CPU time	2.91 seconds
Started	Jan 03 12:44:29 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	217008 kb
Host	smart-f74d57c1-1710-4242-84de-ec3a7835921a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401962414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2401962414 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.779396549
Short name	T1160
Test name
Test status
Simulation time	55571959 ps
CPU time	2.54 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:33 PM PST 24
Peak memory	224684 kb
Host	smart-65c47cfb-1aff-465d-b61b-595b0392511b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779396549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.77939 6549 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1095740199
Short name	T1169
Test name
Test status
Simulation time	24899331 ps
CPU time	1.3 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	224676 kb
Host	smart-6bc5a496-ac4d-4275-986c-c8c4cbb7e426
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095740199 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1095740199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1187352544
Short name	T1197
Test name
Test status
Simulation time	35345133 ps
CPU time	1.25 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	217612 kb
Host	smart-a67dfa78-b719-4721-a072-fa2023d79f82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187352544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1187352544 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.1819187570
Short name	T1253
Test name
Test status
Simulation time	38105296 ps
CPU time	0.75 seconds
Started	Jan 03 12:44:34 PM PST 24
Finished	Jan 03 12:45:56 PM PST 24
Peak memory	217352 kb
Host	smart-cf2f763f-e3b3-41e5-ac28-3bacb469721c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819187570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1819187570 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2250702424
Short name	T1170
Test name
Test status
Simulation time	28795158 ps
CPU time	1.48 seconds
Started	Jan 03 12:44:58 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	217572 kb
Host	smart-9fdca8c8-861a-4508-ba50-8af80975eeef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250702424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.2250702424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4038553336
Short name	T120
Test name
Test status
Simulation time	62591816 ps
CPU time	1.18 seconds
Started	Jan 03 12:45:04 PM PST 24
Finished	Jan 03 12:46:33 PM PST 24
Peak memory	217860 kb
Host	smart-8218158c-b57f-4f3c-a452-5de25e04b17d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038553336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.4038553336 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3885657
Short name	T170
Test name
Test status
Simulation time	486906560 ps
CPU time	3.02 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:10 PM PST 24
Peak memory	225116 kb
Host	smart-35a7a223-410c-4fcb-baac-2bb9728f45da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ =kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_s hadow_reg_errors_with_csr_rw.3885657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.1561980279
Short name	T69
Test name
Test status
Simulation time	50921109 ps
CPU time	2.62 seconds
Started	Jan 03 12:44:37 PM PST 24
Finished	Jan 03 12:46:00 PM PST 24
Peak memory	217540 kb
Host	smart-63a07e5b-8537-4c6e-b6c9-d22499e846dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561980279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1561980279 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.885166853
Short name	T77
Test name
Test status
Simulation time	55777920 ps
CPU time	2.1 seconds
Started	Jan 03 12:44:39 PM PST 24
Finished	Jan 03 12:46:12 PM PST 24
Peak memory	218656 kb
Host	smart-8510d6a2-2671-4177-94b9-644e6a0d563c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885166853 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.885166853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1455003533
Short name	T1215
Test name
Test status
Simulation time	20170288 ps
CPU time	0.97 seconds
Started	Jan 03 12:44:25 PM PST 24
Finished	Jan 03 12:45:40 PM PST 24
Peak memory	217404 kb
Host	smart-3fba80a3-d0db-41d9-92a0-8811153f937d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455003533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1455003533 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1682362418
Short name	T1240
Test name
Test status
Simulation time	39415075 ps
CPU time	0.79 seconds
Started	Jan 03 12:44:40 PM PST 24
Finished	Jan 03 12:46:02 PM PST 24
Peak memory	216704 kb
Host	smart-fcd74338-6b36-4aae-8612-f34f5026bb97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682362418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1682362418 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4198019114
Short name	T66
Test name
Test status
Simulation time	487936892 ps
CPU time	2.79 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:23 PM PST 24
Peak memory	217584 kb
Host	smart-71703267-22fe-4bcb-8703-049c27929f4a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198019114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.4198019114 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1243176633
Short name	T94
Test name
Test status
Simulation time	147950903 ps
CPU time	1.29 seconds
Started	Jan 03 12:44:24 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	218912 kb
Host	smart-a79ab890-b854-4602-8572-ea622f0d9e77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243176633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.1243176633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.931823535
Short name	T1242
Test name
Test status
Simulation time	420557069 ps
CPU time	1.96 seconds
Started	Jan 03 12:44:45 PM PST 24
Finished	Jan 03 12:46:21 PM PST 24
Peak memory	220464 kb
Host	smart-3c168a76-85c1-41d7-9167-0677a878ffcd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931823535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac _shadow_reg_errors_with_csr_rw.931823535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1013247019
Short name	T71
Test name
Test status
Simulation time	19797492 ps
CPU time	1.35 seconds
Started	Jan 03 12:44:33 PM PST 24
Finished	Jan 03 12:45:51 PM PST 24
Peak memory	216720 kb
Host	smart-c5bb26e1-9143-45d0-ad9c-fdb71537ca0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013247019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1013247019 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2474940658
Short name	T123
Test name
Test status
Simulation time	109118811 ps
CPU time	2.97 seconds
Started	Jan 03 12:44:42 PM PST 24
Finished	Jan 03 12:46:09 PM PST 24
Peak memory	223948 kb
Host	smart-d6b51510-d74d-428e-bab9-47f3e585d5dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474940658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2474 940658 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.552765460
Short name	T1144
Test name
Test status
Simulation time	57787312 ps
CPU time	1.75 seconds
Started	Jan 03 12:44:47 PM PST 24
Finished	Jan 03 12:46:16 PM PST 24
Peak memory	221136 kb
Host	smart-43eb6c37-b12b-44e6-85ca-2a62172d8156
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552765460 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.552765460 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3682744906
Short name	T1193
Test name
Test status
Simulation time	23747420 ps
CPU time	0.95 seconds
Started	Jan 03 12:44:33 PM PST 24
Finished	Jan 03 12:46:11 PM PST 24
Peak memory	217284 kb
Host	smart-e3e62048-91b0-454c-858d-5f3b7c0d6aeb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682744906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3682744906 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.2566996883
Short name	T1209
Test name
Test status
Simulation time	27232750 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:26 PM PST 24
Finished	Jan 03 12:45:55 PM PST 24
Peak memory	216612 kb
Host	smart-22903fa1-de30-41ab-9e03-13cbb52c4d34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566996883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2566996883 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.448333490
Short name	T1161
Test name
Test status
Simulation time	95943210 ps
CPU time	2.66 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:14 PM PST 24
Peak memory	221884 kb
Host	smart-3b27e3be-6e6b-472b-b766-72b504675e8a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448333490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr _outstanding.448333490 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1990598749
Short name	T1218
Test name
Test status
Simulation time	150083703 ps
CPU time	1.08 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	217388 kb
Host	smart-49b7579c-b184-409e-921e-085e0a5d1a0a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990598749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1990598749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3271480120
Short name	T1205
Test name
Test status
Simulation time	720219614 ps
CPU time	1.75 seconds
Started	Jan 03 12:45:00 PM PST 24
Finished	Jan 03 12:46:30 PM PST 24
Peak memory	216876 kb
Host	smart-fe670ba4-12a6-4360-9128-0c2f2b529a62
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271480120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3271480120 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3129807226
Short name	T169
Test name
Test status
Simulation time	186216700 ps
CPU time	2.61 seconds
Started	Jan 03 12:44:31 PM PST 24
Finished	Jan 03 12:46:04 PM PST 24
Peak memory	217552 kb
Host	smart-c7fc10b0-85a7-4c75-92c6-f967a209c375
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129807226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3129 807226 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2611268393
Short name	T134
Test name
Test status
Simulation time	20735529 ps
CPU time	1.29 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:18 PM PST 24
Peak memory	220468 kb
Host	smart-b742d3f9-3650-4fb1-a13b-cc58a22546af
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611268393 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2611268393 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2525376269
Short name	T135
Test name
Test status
Simulation time	29846861 ps
CPU time	1.22 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:45:42 PM PST 24
Peak memory	217548 kb
Host	smart-1d0e6721-8b8e-4065-8b58-6fc683f8e0b8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525376269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2525376269 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.1151911046
Short name	T153
Test name
Test status
Simulation time	20056867 ps
CPU time	0.81 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:15 PM PST 24
Peak memory	217468 kb
Host	smart-72b7c6b4-ed18-41b6-bc35-587ca2b22df5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151911046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1151911046 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2159315293
Short name	T1248
Test name
Test status
Simulation time	56109433 ps
CPU time	1.59 seconds
Started	Jan 03 12:44:26 PM PST 24
Finished	Jan 03 12:45:59 PM PST 24
Peak memory	217544 kb
Host	smart-873f22d2-74e1-4a7e-8807-c3a35e1f85d2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159315293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.2159315293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4121883346
Short name	T1246
Test name
Test status
Simulation time	62551791 ps
CPU time	1.02 seconds
Started	Jan 03 12:44:25 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	224736 kb
Host	smart-5ce83b59-0ca6-48ef-9417-142c908fe4f6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121883346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.4121883346 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.672528597
Short name	T89
Test name
Test status
Simulation time	1222371220 ps
CPU time	3.09 seconds
Started	Jan 03 12:44:59 PM PST 24
Finished	Jan 03 12:46:34 PM PST 24
Peak memory	220532 kb
Host	smart-5aa4c1a3-5978-48ce-a42e-acca7df3e6aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672528597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac _shadow_reg_errors_with_csr_rw.672528597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.2131089113
Short name	T1221
Test name
Test status
Simulation time	50838533 ps
CPU time	1.64 seconds
Started	Jan 03 12:44:59 PM PST 24
Finished	Jan 03 12:46:44 PM PST 24
Peak memory	216988 kb
Host	smart-71fa412c-983e-4dea-a747-5843065f7cb8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131089113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2131089113 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.172528185
Short name	T59
Test name
Test status
Simulation time	1726754576 ps
CPU time	9.41 seconds
Started	Jan 03 12:44:59 PM PST 24
Finished	Jan 03 12:46:53 PM PST 24
Peak memory	217640 kb
Host	smart-dca2c06a-5024-42c4-aaec-53051fa6980d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172528185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.17252818 5 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3250838190
Short name	T126
Test name
Test status
Simulation time	652240741 ps
CPU time	8.84 seconds
Started	Jan 03 12:44:09 PM PST 24
Finished	Jan 03 12:45:47 PM PST 24
Peak memory	217628 kb
Host	smart-da7d3345-27e3-4df2-b88a-4a9c26503f18
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250838190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3250838 190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2773628514
Short name	T1239
Test name
Test status
Simulation time	75073758 ps
CPU time	0.96 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:42 PM PST 24
Peak memory	217356 kb
Host	smart-76e63b01-d23e-45ab-b924-4b693dc4aeb1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773628514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2773628 514 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3855091016
Short name	T1181
Test name
Test status
Simulation time	69729962 ps
CPU time	1.41 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:23 PM PST 24
Peak memory	219420 kb
Host	smart-7af34ded-37f5-48c2-a01e-eec42b2409cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855091016 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3855091016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3215339521
Short name	T1249
Test name
Test status
Simulation time	23390384 ps
CPU time	1.05 seconds
Started	Jan 03 12:44:42 PM PST 24
Finished	Jan 03 12:46:02 PM PST 24
Peak memory	217408 kb
Host	smart-652b4be2-6abd-40b5-978d-17ab83f823d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215339521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3215339521 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3499471261
Short name	T1151
Test name
Test status
Simulation time	18505625 ps
CPU time	0.82 seconds
Started	Jan 03 12:44:38 PM PST 24
Finished	Jan 03 12:46:08 PM PST 24
Peak memory	216568 kb
Host	smart-2605d038-d205-4568-9f67-72e69d2f1cdc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499471261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3499471261 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1355305280
Short name	T139
Test name
Test status
Simulation time	47035215 ps
CPU time	1.17 seconds
Started	Jan 03 12:44:32 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	216836 kb
Host	smart-05dc6362-9ed3-412e-b596-61260ab64f04
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355305280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.1355305280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.462727458
Short name	T60
Test name
Test status
Simulation time	10572927 ps
CPU time	0.74 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:37 PM PST 24
Peak memory	217256 kb
Host	smart-8389c778-f2f7-4215-aaa1-3d6258396094
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462727458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.462727458 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.860940312
Short name	T1238
Test name
Test status
Simulation time	481139390 ps
CPU time	2.63 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:14 PM PST 24
Peak memory	217604 kb
Host	smart-9a7ea8ca-9042-4fd8-b42b-8cca9accd61b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860940312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_ outstanding.860940312 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.796974447
Short name	T1159
Test name
Test status
Simulation time	50922855 ps
CPU time	1.22 seconds
Started	Jan 03 12:44:38 PM PST 24
Finished	Jan 03 12:46:00 PM PST 24
Peak memory	218028 kb
Host	smart-45110895-d37c-43a7-bb73-82bebcbd87ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796974447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e rrors.796974447 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2374364611
Short name	T1230
Test name
Test status
Simulation time	267011555 ps
CPU time	2 seconds
Started	Jan 03 12:45:02 PM PST 24
Finished	Jan 03 12:46:44 PM PST 24
Peak memory	220624 kb
Host	smart-8bb80af8-d71f-45ab-85f0-0b35b883459e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374364611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.2374364611 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2292141456
Short name	T1229
Test name
Test status
Simulation time	221748425 ps
CPU time	1.7 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:09 PM PST 24
Peak memory	217704 kb
Host	smart-9b77ed0b-1b58-4dd4-8648-1270504f74d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292141456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2292141456 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2875609528
Short name	T63
Test name
Test status
Simulation time	432126232 ps
CPU time	4.95 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	217556 kb
Host	smart-c1bf3138-f87d-44e2-a66e-692c4e54a421
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875609528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.28756 09528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.1275816636
Short name	T1192
Test name
Test status
Simulation time	38194884 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:38 PM PST 24
Finished	Jan 03 12:46:04 PM PST 24
Peak memory	216660 kb
Host	smart-f4964a96-72ca-4a38-8238-abc2761f3072
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275816636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1275816636 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.1923202844
Short name	T1187
Test name
Test status
Simulation time	17306338 ps
CPU time	0.82 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:36 PM PST 24
Peak memory	216432 kb
Host	smart-67ba92e5-8389-4eae-8a06-ca4abb84a70d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923202844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1923202844 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.2145845157
Short name	T106
Test name
Test status
Simulation time	34138766 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:57 PM PST 24
Finished	Jan 03 12:46:24 PM PST 24
Peak memory	216504 kb
Host	smart-976c7f68-c109-438e-bd24-326b707a396d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145845157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2145845157 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.24619769
Short name	T143
Test name
Test status
Simulation time	10856106 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	217368 kb
Host	smart-fa214c87-842f-4f18-80cf-2075a7c24186
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.24619769 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.78298767
Short name	T1175
Test name
Test status
Simulation time	15525508 ps
CPU time	0.81 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:11 PM PST 24
Peak memory	216632 kb
Host	smart-651faeb7-11f5-4e9a-9feb-d9a0ac301d67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78298767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.78298767 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.1390522497
Short name	T1216
Test name
Test status
Simulation time	20939820 ps
CPU time	0.79 seconds
Started	Jan 03 12:44:57 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	216580 kb
Host	smart-9a88ed37-074e-4461-8747-8d12a6e9e40e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390522497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1390522497 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1755897614
Short name	T174
Test name
Test status
Simulation time	19505795 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:24 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	216604 kb
Host	smart-b0be039d-7e6b-47a5-a835-8d6a94451e5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755897614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1755897614 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.4040810146
Short name	T154
Test name
Test status
Simulation time	16245172 ps
CPU time	0.82 seconds
Started	Jan 03 12:44:34 PM PST 24
Finished	Jan 03 12:45:55 PM PST 24
Peak memory	216652 kb
Host	smart-afebfb54-3964-4a06-954e-754a11a9957a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040810146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.4040810146 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.2984554076
Short name	T1155
Test name
Test status
Simulation time	31920126 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:40 PM PST 24
Finished	Jan 03 12:46:18 PM PST 24
Peak memory	217424 kb
Host	smart-611a7812-0756-4c9e-a16e-b816360a6876
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984554076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2984554076 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1206075914
Short name	T1185
Test name
Test status
Simulation time	323185300 ps
CPU time	9.07 seconds
Started	Jan 03 12:44:19 PM PST 24
Finished	Jan 03 12:45:43 PM PST 24
Peak memory	216888 kb
Host	smart-5c48b8f7-2386-40cb-a67a-e69807d71ac4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206075914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1206075 914 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2309986328
Short name	T1195
Test name
Test status
Simulation time	3980755624 ps
CPU time	21.53 seconds
Started	Jan 03 12:44:06 PM PST 24
Finished	Jan 03 12:46:08 PM PST 24
Peak memory	217708 kb
Host	smart-1a71592e-18c5-40e5-af6b-8e2d434f6ca3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309986328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2309986 328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.250815242
Short name	T1140
Test name
Test status
Simulation time	51020363 ps
CPU time	0.98 seconds
Started	Jan 03 12:44:16 PM PST 24
Finished	Jan 03 12:45:32 PM PST 24
Peak memory	217428 kb
Host	smart-2644ab13-9419-4f69-8f86-5bc1cfea2275
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250815242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.25081524 2 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3722791359
Short name	T72
Test name
Test status
Simulation time	37154441 ps
CPU time	1.54 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:49 PM PST 24
Peak memory	219428 kb
Host	smart-df8279b8-893e-4b4e-a2f0-146298c3e814
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722791359 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3722791359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.2958988499
Short name	T148
Test name
Test status
Simulation time	60516079 ps
CPU time	1.19 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:49 PM PST 24
Peak memory	217680 kb
Host	smart-7b13ada2-1ca5-4452-bb65-9d2ed2b0d973
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958988499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2958988499 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.231340771
Short name	T1231
Test name
Test status
Simulation time	89998600 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:24 PM PST 24
Finished	Jan 03 12:45:52 PM PST 24
Peak memory	217292 kb
Host	smart-87e28bf5-55d0-4f95-a33b-2da13466e693
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231340771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.231340771 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.340961831
Short name	T129
Test name
Test status
Simulation time	80041155 ps
CPU time	1.36 seconds
Started	Jan 03 12:44:30 PM PST 24
Finished	Jan 03 12:46:07 PM PST 24
Peak memory	217580 kb
Host	smart-8515a45b-d2a2-4c94-8d1d-96747a519ca6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340961831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial _access.340961831 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3805790412
Short name	T172
Test name
Test status
Simulation time	12650488 ps
CPU time	0.75 seconds
Started	Jan 03 12:44:46 PM PST 24
Finished	Jan 03 12:46:12 PM PST 24
Peak memory	217356 kb
Host	smart-0d2192bc-1d1a-4cc9-98a0-5de38f7faf35
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805790412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3805790412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2883462767
Short name	T1256
Test name
Test status
Simulation time	181796082 ps
CPU time	1.61 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:28 PM PST 24
Peak memory	217664 kb
Host	smart-855682c3-9799-4e73-ba54-5a9e21bb3476
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883462767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.2883462767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3366194273
Short name	T1222
Test name
Test status
Simulation time	148668466 ps
CPU time	1.09 seconds
Started	Jan 03 12:44:02 PM PST 24
Finished	Jan 03 12:45:35 PM PST 24
Peak memory	217864 kb
Host	smart-a1db469e-9a8d-491c-92c9-ca779980d2a9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366194273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.3366194273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2745590653
Short name	T1211
Test name
Test status
Simulation time	80571492 ps
CPU time	2.12 seconds
Started	Jan 03 12:44:26 PM PST 24
Finished	Jan 03 12:45:41 PM PST 24
Peak memory	221628 kb
Host	smart-807fb28c-1499-4027-85df-4154f174473e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745590653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.2745590653 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2624215869
Short name	T65
Test name
Test status
Simulation time	31909427 ps
CPU time	2.02 seconds
Started	Jan 03 12:44:20 PM PST 24
Finished	Jan 03 12:45:40 PM PST 24
Peak memory	217596 kb
Host	smart-02f76ea6-7b60-49f3-8d9d-7ec561ec5f98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624215869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2624215869 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.4024753298
Short name	T165
Test name
Test status
Simulation time	386845080 ps
CPU time	5.12 seconds
Started	Jan 03 12:44:27 PM PST 24
Finished	Jan 03 12:45:50 PM PST 24
Peak memory	217664 kb
Host	smart-4ecce032-e551-495d-977f-bbcd38fe10ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024753298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.40247 53298 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1895772528
Short name	T1157
Test name
Test status
Simulation time	50567109 ps
CPU time	0.8 seconds
Started	Jan 03 12:44:40 PM PST 24
Finished	Jan 03 12:46:08 PM PST 24
Peak memory	217372 kb
Host	smart-9b58f996-032b-4921-9953-98bc854cf47e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895772528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1895772528 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.3588752326
Short name	T1213
Test name
Test status
Simulation time	13852616 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:20 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	217280 kb
Host	smart-767dfbb8-ae09-4abc-ab6c-5daf7370aecf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588752326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3588752326 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2291818420
Short name	T1226
Test name
Test status
Simulation time	20864554 ps
CPU time	0.76 seconds
Started	Jan 03 12:44:39 PM PST 24
Finished	Jan 03 12:45:57 PM PST 24
Peak memory	217284 kb
Host	smart-c64d5fd8-7b85-4a2a-9e31-b950d36bee2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291818420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2291818420 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2820773899
Short name	T1228
Test name
Test status
Simulation time	17735430 ps
CPU time	0.75 seconds
Started	Jan 03 12:45:02 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	216576 kb
Host	smart-007aafb4-4f7c-4b2b-bd11-04ba87962ca7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820773899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2820773899 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.2509172813
Short name	T1237
Test name
Test status
Simulation time	49390059 ps
CPU time	0.76 seconds
Started	Jan 03 12:45:12 PM PST 24
Finished	Jan 03 12:46:42 PM PST 24
Peak memory	217432 kb
Host	smart-72d264d8-b306-4520-a8f7-7309d63f7a6b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509172813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2509172813 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.1267634101
Short name	T1146
Test name
Test status
Simulation time	16069209 ps
CPU time	0.82 seconds
Started	Jan 03 12:45:21 PM PST 24
Finished	Jan 03 12:46:50 PM PST 24
Peak memory	217344 kb
Host	smart-c98e6a76-d680-460a-86c0-61d9048bf9cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267634101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1267634101 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.3671358805
Short name	T152
Test name
Test status
Simulation time	45162484 ps
CPU time	0.81 seconds
Started	Jan 03 12:45:23 PM PST 24
Finished	Jan 03 12:46:56 PM PST 24
Peak memory	217416 kb
Host	smart-47e09544-0296-4792-9767-6934fd7d2ca5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671358805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3671358805 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1738792441
Short name	T1202
Test name
Test status
Simulation time	23559192 ps
CPU time	0.84 seconds
Started	Jan 03 12:44:42 PM PST 24
Finished	Jan 03 12:46:07 PM PST 24
Peak memory	217432 kb
Host	smart-2c148524-895a-405b-aa74-aa4b952ff76d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738792441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1738792441 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3407332693
Short name	T128
Test name
Test status
Simulation time	448738061 ps
CPU time	4.97 seconds
Started	Jan 03 12:44:06 PM PST 24
Finished	Jan 03 12:45:35 PM PST 24
Peak memory	217704 kb
Host	smart-65e84337-9863-426a-9b85-1b5637afa548
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407332693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3407332 693 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2820286973
Short name	T1166
Test name
Test status
Simulation time	2723734552 ps
CPU time	20.3 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:46:01 PM PST 24
Peak memory	216900 kb
Host	smart-d0d17009-c8f3-445f-82fe-a00a976598dd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820286973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2820286 973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1341943457
Short name	T1227
Test name
Test status
Simulation time	57709572 ps
CPU time	1.14 seconds
Started	Jan 03 12:44:26 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	217680 kb
Host	smart-a63799c6-f589-4a6a-b265-1bddb8a66447
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341943457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1341943 457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3902706696
Short name	T1244
Test name
Test status
Simulation time	34762797 ps
CPU time	1.47 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:10 PM PST 24
Peak memory	218976 kb
Host	smart-b7a92d3e-2e3f-4ecf-86cd-e0c532fa3f9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902706696 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3902706696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.2350076239
Short name	T131
Test name
Test status
Simulation time	27105667 ps
CPU time	1.14 seconds
Started	Jan 03 12:44:14 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	217544 kb
Host	smart-25088350-85f1-42b2-b0d0-f4d755d04c6f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350076239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2350076239 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3042456255
Short name	T173
Test name
Test status
Simulation time	32616534 ps
CPU time	0.81 seconds
Started	Jan 03 12:44:18 PM PST 24
Finished	Jan 03 12:45:58 PM PST 24
Peak memory	216592 kb
Host	smart-a7ea7319-7c13-4f7a-81ff-0fdbbbdf4ee2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042456255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3042456255 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3235613431
Short name	T138
Test name
Test status
Simulation time	22638543 ps
CPU time	1.16 seconds
Started	Jan 03 12:44:33 PM PST 24
Finished	Jan 03 12:46:04 PM PST 24
Peak memory	217520 kb
Host	smart-ad702071-d321-40cb-9988-776654ca3d11
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235613431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.3235613431 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3543881436
Short name	T1152
Test name
Test status
Simulation time	31210821 ps
CPU time	0.77 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:42 PM PST 24
Peak memory	216608 kb
Host	smart-fb9fec2a-c6f1-4f7f-88bc-79f942508d07
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543881436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3543881436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.119643859
Short name	T1204
Test name
Test status
Simulation time	100503419 ps
CPU time	2.6 seconds
Started	Jan 03 12:44:21 PM PST 24
Finished	Jan 03 12:45:49 PM PST 24
Peak memory	217536 kb
Host	smart-4212510a-7e31-4da7-a275-aa90c90695d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119643859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_ outstanding.119643859 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4058035766
Short name	T1190
Test name
Test status
Simulation time	30527392 ps
CPU time	1.22 seconds
Started	Jan 03 12:44:19 PM PST 24
Finished	Jan 03 12:45:55 PM PST 24
Peak memory	217884 kb
Host	smart-d164a6b4-5fdd-47b2-aece-4c7b8493e43c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058035766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.4058035766 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3356737403
Short name	T1252
Test name
Test status
Simulation time	59351959 ps
CPU time	2.3 seconds
Started	Jan 03 12:44:30 PM PST 24
Finished	Jan 03 12:45:52 PM PST 24
Peak memory	221416 kb
Host	smart-b190a88c-a0dc-4a16-b31e-a2926cc0207c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356737403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.3356737403 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.752486764
Short name	T1156
Test name
Test status
Simulation time	38074053 ps
CPU time	2.48 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	217712 kb
Host	smart-cd6648db-e59c-4180-8258-61ea94af7596
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752486764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.752486764 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3510659850
Short name	T121
Test name
Test status
Simulation time	861371402 ps
CPU time	4.96 seconds
Started	Jan 03 12:44:48 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	216884 kb
Host	smart-6d369af3-c519-437d-9e31-f053a22e1428
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510659850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.35106 59850 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.1390040017
Short name	T1158
Test name
Test status
Simulation time	92961845 ps
CPU time	0.8 seconds
Started	Jan 03 12:44:41 PM PST 24
Finished	Jan 03 12:46:01 PM PST 24
Peak memory	216524 kb
Host	smart-096317d9-5d3e-493a-8cad-c61f46806601
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390040017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1390040017 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.792247968
Short name	T1224
Test name
Test status
Simulation time	15742540 ps
CPU time	0.82 seconds
Started	Jan 03 12:44:58 PM PST 24
Finished	Jan 03 12:46:25 PM PST 24
Peak memory	216524 kb
Host	smart-eada33f4-386e-439b-b90c-d814c3573923
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792247968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.792247968 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.2255878980
Short name	T1203
Test name
Test status
Simulation time	23699427 ps
CPU time	0.78 seconds
Started	Jan 03 12:45:00 PM PST 24
Finished	Jan 03 12:46:35 PM PST 24
Peak memory	217456 kb
Host	smart-3d26e99e-347c-486a-a505-2755e089c195
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255878980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2255878980 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.1325574354
Short name	T1176
Test name
Test status
Simulation time	22691085 ps
CPU time	0.83 seconds
Started	Jan 03 12:44:57 PM PST 24
Finished	Jan 03 12:46:36 PM PST 24
Peak memory	216676 kb
Host	smart-89daf1aa-d3a7-4248-ae5c-a1097bba4fac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325574354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1325574354 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.2317069298
Short name	T1250
Test name
Test status
Simulation time	44573293 ps
CPU time	0.76 seconds
Started	Jan 03 12:45:02 PM PST 24
Finished	Jan 03 12:46:39 PM PST 24
Peak memory	217372 kb
Host	smart-721f5b46-4284-4e9b-8c0c-847f8fbb7cf3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317069298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2317069298 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2644886675
Short name	T1147
Test name
Test status
Simulation time	14772705 ps
CPU time	0.82 seconds
Started	Jan 03 12:44:39 PM PST 24
Finished	Jan 03 12:46:04 PM PST 24
Peak memory	217540 kb
Host	smart-a0a4e54f-6f9e-4943-9eaa-f61d940b3e05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644886675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2644886675 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3887895870
Short name	T1154
Test name
Test status
Simulation time	23773810 ps
CPU time	2.09 seconds
Started	Jan 03 12:44:14 PM PST 24
Finished	Jan 03 12:45:29 PM PST 24
Peak memory	222820 kb
Host	smart-4fc9a435-0cc2-481b-83e8-ba9834b1f5fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887895870 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3887895870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1136956236
Short name	T1142
Test name
Test status
Simulation time	22568949 ps
CPU time	0.99 seconds
Started	Jan 03 12:44:47 PM PST 24
Finished	Jan 03 12:46:16 PM PST 24
Peak memory	217572 kb
Host	smart-c8cd9250-675a-46aa-a750-f381f3632102
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136956236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1136956236 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3020481234
Short name	T140
Test name
Test status
Simulation time	26062382 ps
CPU time	0.78 seconds
Started	Jan 03 12:44:12 PM PST 24
Finished	Jan 03 12:45:42 PM PST 24
Peak memory	216500 kb
Host	smart-5d8a609e-c752-43f3-ad99-84187c523c6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020481234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3020481234 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3647222351
Short name	T1225
Test name
Test status
Simulation time	292055424 ps
CPU time	1.85 seconds
Started	Jan 03 12:44:27 PM PST 24
Finished	Jan 03 12:45:56 PM PST 24
Peak memory	217640 kb
Host	smart-a96d5d2d-1b03-4c78-b6a3-94e7d52e5341
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647222351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.3647222351 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3931446941
Short name	T3
Test name
Test status
Simulation time	125280485 ps
CPU time	1.65 seconds
Started	Jan 03 12:44:14 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	221796 kb
Host	smart-678befb5-c611-48f0-9ed3-0d83a64806d0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931446941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.3931446941 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.662920643
Short name	T141
Test name
Test status
Simulation time	39289476 ps
CPU time	2.22 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:20 PM PST 24
Peak memory	216996 kb
Host	smart-b476b1be-776f-4c26-891f-0afc23987be0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662920643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.662920643 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3214718637
Short name	T1255
Test name
Test status
Simulation time	27814528 ps
CPU time	1.41 seconds
Started	Jan 03 12:44:21 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	218544 kb
Host	smart-17db4693-0994-4d5e-ac14-00208cc19d95
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214718637 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3214718637 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.2674921809
Short name	T146
Test name
Test status
Simulation time	62119698 ps
CPU time	0.94 seconds
Started	Jan 03 12:44:37 PM PST 24
Finished	Jan 03 12:46:00 PM PST 24
Peak memory	217216 kb
Host	smart-205b0844-ddcb-4e0a-8bbd-43c4f53ed6b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674921809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2674921809 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2491254982
Short name	T1234
Test name
Test status
Simulation time	39562503 ps
CPU time	0.76 seconds
Started	Jan 03 12:44:43 PM PST 24
Finished	Jan 03 12:46:15 PM PST 24
Peak memory	217352 kb
Host	smart-cff967b3-ef87-4dfd-9aa0-65afdbc91b2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491254982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2491254982 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.780284032
Short name	T147
Test name
Test status
Simulation time	144642289 ps
CPU time	2.22 seconds
Started	Jan 03 12:44:20 PM PST 24
Finished	Jan 03 12:45:36 PM PST 24
Peak memory	217540 kb
Host	smart-83e637b7-2e5e-4394-a9f3-f47b5cd7073e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780284032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_ outstanding.780284032 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2265309500
Short name	T95
Test name
Test status
Simulation time	138932339 ps
CPU time	2.89 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:45:44 PM PST 24
Peak memory	221288 kb
Host	smart-cd3fc683-c9ef-4ae9-b6a6-54626c62e91a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265309500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.2265309500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2072344722
Short name	T1199
Test name
Test status
Simulation time	115540414 ps
CPU time	1.98 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:38 PM PST 24
Peak memory	216924 kb
Host	smart-87020a9c-880e-4025-90a7-5c72d81ebffc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072344722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2072344722 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1837096427
Short name	T118
Test name
Test status
Simulation time	202486548 ps
CPU time	2.82 seconds
Started	Jan 03 12:44:28 PM PST 24
Finished	Jan 03 12:45:46 PM PST 24
Peak memory	217672 kb
Host	smart-1a809cd4-f2cb-47c8-b112-95089db01eab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837096427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.18370 96427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3573325972
Short name	T142
Test name
Test status
Simulation time	43326706 ps
CPU time	1.91 seconds
Started	Jan 03 12:44:25 PM PST 24
Finished	Jan 03 12:45:41 PM PST 24
Peak memory	223456 kb
Host	smart-18e99124-b096-47f0-af79-7038eb4564c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573325972 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3573325972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2098000761
Short name	T64
Test name
Test status
Simulation time	18192440 ps
CPU time	1.1 seconds
Started	Jan 03 12:45:01 PM PST 24
Finished	Jan 03 12:46:30 PM PST 24
Peak memory	217532 kb
Host	smart-a0682561-eed0-49e2-aeb9-39c40231aba1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098000761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2098000761 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.2495060833
Short name	T133
Test name
Test status
Simulation time	16993939 ps
CPU time	0.74 seconds
Started	Jan 03 12:44:37 PM PST 24
Finished	Jan 03 12:46:06 PM PST 24
Peak memory	217416 kb
Host	smart-e130d37f-b0b5-4bd6-b306-60ce4cde9194
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495060833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2495060833 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2257105932
Short name	T1177
Test name
Test status
Simulation time	341630725 ps
CPU time	1.8 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:37 PM PST 24
Peak memory	217688 kb
Host	smart-29fee2e9-fd70-4290-8fd2-b18327fc23c5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257105932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.2257105932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3266708132
Short name	T75
Test name
Test status
Simulation time	120865443 ps
CPU time	1.03 seconds
Started	Jan 03 12:44:23 PM PST 24
Finished	Jan 03 12:45:48 PM PST 24
Peak memory	217948 kb
Host	smart-b046e0d8-373d-47c1-a438-5fff375f7df9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266708132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.3266708132 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2956972728
Short name	T1173
Test name
Test status
Simulation time	399379273 ps
CPU time	3 seconds
Started	Jan 03 12:44:22 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	221960 kb
Host	smart-0480a84f-0d67-49da-8e99-9b7499979852
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956972728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.2956972728 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2934635291
Short name	T1236
Test name
Test status
Simulation time	257116759 ps
CPU time	1.83 seconds
Started	Jan 03 12:44:32 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	217020 kb
Host	smart-480480df-c1da-41a4-8260-0059f998fe01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934635291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2934635291 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1692722335
Short name	T163
Test name
Test status
Simulation time	263384718 ps
CPU time	2.57 seconds
Started	Jan 03 12:44:55 PM PST 24
Finished	Jan 03 12:46:27 PM PST 24
Peak memory	217640 kb
Host	smart-7a5bf6f0-bd31-4823-bee4-2e170daa487d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692722335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.16927 22335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2795321984
Short name	T78
Test name
Test status
Simulation time	205058593 ps
CPU time	1.89 seconds
Started	Jan 03 12:44:15 PM PST 24
Finished	Jan 03 12:45:41 PM PST 24
Peak memory	221228 kb
Host	smart-f508acd4-122c-41c3-b12a-73faee6a4dfd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795321984 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2795321984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3384650707
Short name	T1232
Test name
Test status
Simulation time	29456110 ps
CPU time	1.17 seconds
Started	Jan 03 12:44:52 PM PST 24
Finished	Jan 03 12:46:18 PM PST 24
Peak memory	217552 kb
Host	smart-77de1aab-6153-4869-ab81-08fb3ee3059e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384650707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3384650707 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.2493964209
Short name	T58
Test name
Test status
Simulation time	37950774 ps
CPU time	0.79 seconds
Started	Jan 03 12:44:21 PM PST 24
Finished	Jan 03 12:45:53 PM PST 24
Peak memory	217312 kb
Host	smart-bf323036-29d7-4ee1-ac9c-4c471f679fb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493964209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2493964209 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1238086663
Short name	T124
Test name
Test status
Simulation time	156628996 ps
CPU time	2.29 seconds
Started	Jan 03 12:43:58 PM PST 24
Finished	Jan 03 12:45:25 PM PST 24
Peak memory	217544 kb
Host	smart-981fb914-4278-40b2-91c3-e410c204b62b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238086663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.1238086663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1697783920
Short name	T1243
Test name
Test status
Simulation time	182141419 ps
CPU time	1.38 seconds
Started	Jan 03 12:44:18 PM PST 24
Finished	Jan 03 12:45:38 PM PST 24
Peak memory	218900 kb
Host	smart-3d7d047e-f155-4d67-bd4f-8fdd30a57b4d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697783920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.1697783920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1543510136
Short name	T1258
Test name
Test status
Simulation time	144271159 ps
CPU time	2.96 seconds
Started	Jan 03 12:44:17 PM PST 24
Finished	Jan 03 12:45:44 PM PST 24
Peak memory	224928 kb
Host	smart-f01fe780-e451-4482-a820-9770c3e910eb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543510136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.1543510136 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3574961836
Short name	T1153
Test name
Test status
Simulation time	115938341 ps
CPU time	2.06 seconds
Started	Jan 03 12:44:13 PM PST 24
Finished	Jan 03 12:45:39 PM PST 24
Peak memory	218064 kb
Host	smart-721b62e3-bca7-41ae-87a0-5bd8ed767bbd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574961836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3574961836 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.459094275
Short name	T122
Test name
Test status
Simulation time	1104948700 ps
CPU time	5.23 seconds
Started	Jan 03 12:44:32 PM PST 24
Finished	Jan 03 12:46:01 PM PST 24
Peak memory	217528 kb
Host	smart-9e4bfc30-5a2b-48cf-b315-9b6feee4e07e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459094275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.459094 275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2537110175
Short name	T1201
Test name
Test status
Simulation time	49950005 ps
CPU time	2.04 seconds
Started	Jan 03 12:44:18 PM PST 24
Finished	Jan 03 12:45:50 PM PST 24
Peak memory	223692 kb
Host	smart-1f021ed2-92ae-4e73-885a-84837c023a25
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537110175 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2537110175 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.399500086
Short name	T1145
Test name
Test status
Simulation time	60154080 ps
CPU time	0.96 seconds
Started	Jan 03 12:44:34 PM PST 24
Finished	Jan 03 12:45:56 PM PST 24
Peak memory	216744 kb
Host	smart-37448dae-6b44-48e4-a836-27dc8873fdd8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399500086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.399500086 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1999849345
Short name	T104
Test name
Test status
Simulation time	73347912 ps
CPU time	0.75 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:32 PM PST 24
Peak memory	217380 kb
Host	smart-a252029a-b79e-4e5e-8d03-b965d7f30465
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999849345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1999849345 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3977373449
Short name	T1208
Test name
Test status
Simulation time	84275668 ps
CPU time	0.94 seconds
Started	Jan 03 12:44:36 PM PST 24
Finished	Jan 03 12:45:54 PM PST 24
Peak memory	216572 kb
Host	smart-9ce7f339-e3e8-4f02-832e-f2a9a68aee6f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977373449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.3977373449 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3381448278
Short name	T1171
Test name
Test status
Simulation time	475166085 ps
CPU time	3.12 seconds
Started	Jan 03 12:44:56 PM PST 24
Finished	Jan 03 12:46:37 PM PST 24
Peak memory	221944 kb
Host	smart-3de135ab-f878-4fd1-ab3d-89868707475d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381448278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.3381448278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1294629729
Short name	T1196
Test name
Test status
Simulation time	130718511 ps
CPU time	2.53 seconds
Started	Jan 03 12:44:35 PM PST 24
Finished	Jan 03 12:46:03 PM PST 24
Peak memory	217600 kb
Host	smart-48819ec9-f405-4d95-898a-6b8f4cbe5b24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294629729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1294629729 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2976840263
Short name	T144
Test name
Test status
Simulation time	102721125 ps
CPU time	2.98 seconds
Started	Jan 03 12:44:49 PM PST 24
Finished	Jan 03 12:46:46 PM PST 24
Peak memory	217632 kb
Host	smart-f6a8118b-81e9-44e0-bda6-8baafd9e5bb0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976840263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.29768 40263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.3195974963
Short name	T429
Test name
Test status
Simulation time	45753541 ps
CPU time	0.9 seconds
Started	Jan 03 01:19:09 PM PST 24
Finished	Jan 03 01:19:19 PM PST 24
Peak memory	218596 kb
Host	smart-b3c66640-a0cb-404e-a4a8-5af41fbadc71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195974963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3195974963 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.1356629876
Short name	T1100
Test name
Test status
Simulation time	4206922837 ps
CPU time	102.24 seconds
Started	Jan 03 01:19:54 PM PST 24
Finished	Jan 03 01:21:43 PM PST 24
Peak memory	234552 kb
Host	smart-d4f72c2c-f796-4656-b9e1-42faa53683cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356629876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1356629876 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.2027611241
Short name	T372
Test name
Test status
Simulation time	54460047165 ps
CPU time	661.48 seconds
Started	Jan 03 01:19:27 PM PST 24
Finished	Jan 03 01:30:34 PM PST 24
Peak memory	236140 kb
Host	smart-18c44eef-baf6-4903-a3fb-a130c9b5fbd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027611241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2027611241 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.2139370163
Short name	T869
Test name
Test status
Simulation time	70211362 ps
CPU time	0.89 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:19:13 PM PST 24
Peak memory	218548 kb
Host	smart-a238f7e7-1b8c-41e3-9efa-cfdc21c3e5d8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2139370163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2139370163 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.3797462687
Short name	T455
Test name
Test status
Simulation time	5701493301 ps
CPU time	17.59 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:19:39 PM PST 24
Peak memory	219388 kb
Host	smart-7edd49fa-6cfd-466e-89e4-5c7cd0dbcb06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797462687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3797462687 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.4140927554
Short name	T833
Test name
Test status
Simulation time	9126098398 ps
CPU time	147.11 seconds
Started	Jan 03 01:19:34 PM PST 24
Finished	Jan 03 01:22:05 PM PST 24
Peak memory	239724 kb
Host	smart-8cdc5322-132c-42cd-aab8-897b88ae99c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140927554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4140927554 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_key_error.163595340
Short name	T474
Test name
Test status
Simulation time	1540059782 ps
CPU time	2.36 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:19:18 PM PST 24
Peak memory	218700 kb
Host	smart-32062539-5f0b-4692-ac2e-e27e45ae33ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163595340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.163595340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.751794023
Short name	T808
Test name
Test status
Simulation time	666186398 ps
CPU time	2.22 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:19:18 PM PST 24
Peak memory	221476 kb
Host	smart-b2e8f7a8-b571-4237-b1a1-70d892599604
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751794023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.751794023 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.2772055712
Short name	T234
Test name
Test status
Simulation time	108438831521 ps
CPU time	2823.47 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 02:06:14 PM PST 24
Peak memory	466244 kb
Host	smart-a98a96f6-6d70-4950-8d0a-b0e9225e699c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772055712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.2772055712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.923921372
Short name	T379
Test name
Test status
Simulation time	7633193973 ps
CPU time	209.77 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:23:44 PM PST 24
Peak memory	244180 kb
Host	smart-194d91f7-275f-412a-bd83-55a12c5c2242
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923921372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.923921372 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.683720804
Short name	T9
Test name
Test status
Simulation time	10401615648 ps
CPU time	92.6 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:20:48 PM PST 24
Peak memory	290524 kb
Host	smart-4efb0b66-5dcf-4451-8c8c-ce358b42279e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683720804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.683720804 +enable_masking =1 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.905416663
Short name	T629
Test name
Test status
Simulation time	2591859294 ps
CPU time	182.93 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:22:35 PM PST 24
Peak memory	241272 kb
Host	smart-459a01c3-2ff4-4bfe-887a-2d51becd6e95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905416663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.905416663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.3843609432
Short name	T884
Test name
Test status
Simulation time	459957704 ps
CPU time	5.81 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:19:16 PM PST 24
Peak memory	225668 kb
Host	smart-e5e4c5f5-7ebb-4bb1-b71d-da23f1057cdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843609432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3843609432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.1705642028
Short name	T509
Test name
Test status
Simulation time	50373254981 ps
CPU time	467.16 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:27:09 PM PST 24
Peak memory	277300 kb
Host	smart-648b6c19-542d-4737-b3de-ae529dd0ed83
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1705642028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1705642028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.4111888030
Short name	T916
Test name
Test status
Simulation time	311179077 ps
CPU time	6.2 seconds
Started	Jan 03 01:19:43 PM PST 24
Finished	Jan 03 01:19:56 PM PST 24
Peak memory	220016 kb
Host	smart-63bb41bf-ac78-40c9-800e-a4d1b96e0954
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111888030 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.kmac_test_vectors_kmac.4111888030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.979285368
Short name	T480
Test name
Test status
Simulation time	191232923 ps
CPU time	6.15 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:19:58 PM PST 24
Peak memory	218836 kb
Host	smart-01365af4-948a-4ec8-9549-dcd0fa670060
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979285368 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.kmac_test_vectors_kmac_xof.979285368 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.28669411
Short name	T301
Test name
Test status
Simulation time	25754608725 ps
CPU time	1863.9 seconds
Started	Jan 03 01:19:47 PM PST 24
Finished	Jan 03 01:50:58 PM PST 24
Peak memory	381860 kb
Host	smart-08924615-71e9-4049-81b2-1ad74835c886
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=28669411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.28669411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.3422187125
Short name	T221
Test name
Test status
Simulation time	39970251999 ps
CPU time	1818.45 seconds
Started	Jan 03 01:19:41 PM PST 24
Finished	Jan 03 01:50:04 PM PST 24
Peak memory	387512 kb
Host	smart-8ded69ab-f708-41c3-b636-7f380311e60c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3422187125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3422187125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.227949981
Short name	T537
Test name
Test status
Simulation time	23677474965 ps
CPU time	1506.79 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:44:58 PM PST 24
Peak memory	339300 kb
Host	smart-66da298e-9305-4aaa-a175-dfbc7b6438e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=227949981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.227949981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.1526041161
Short name	T1032
Test name
Test status
Simulation time	99504684557 ps
CPU time	1332.15 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 01:42:06 PM PST 24
Peak memory	300180 kb
Host	smart-29b4e639-4934-4c44-a2dd-6d8f09258b3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1526041161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1526041161 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.167868375
Short name	T850
Test name
Test status
Simulation time	277685698219 ps
CPU time	5819.75 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 02:56:55 PM PST 24
Peak memory	661528 kb
Host	smart-4a0fd9d5-3931-4e6e-987d-484a935a170e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=167868375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.167868375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.1088172525
Short name	T927
Test name
Test status
Simulation time	634674220126 ps
CPU time	4698.69 seconds
Started	Jan 03 01:20:08 PM PST 24
Finished	Jan 03 02:38:31 PM PST 24
Peak memory	580672 kb
Host	smart-eba820b1-b096-4da6-ae7e-d105ce5eec3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1088172525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1088172525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.679322191
Short name	T812
Test name
Test status
Simulation time	13476122 ps
CPU time	0.82 seconds
Started	Jan 03 01:19:43 PM PST 24
Finished	Jan 03 01:19:49 PM PST 24
Peak memory	219736 kb
Host	smart-5b691fe8-8ac4-4ccc-9060-a3d681ad7ec4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679322191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.679322191 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.3233462030
Short name	T1073
Test name
Test status
Simulation time	22377092701 ps
CPU time	120.99 seconds
Started	Jan 03 01:19:20 PM PST 24
Finished	Jan 03 01:21:24 PM PST 24
Peak memory	236616 kb
Host	smart-d6f6ff73-a4fd-496e-8517-60223b94d4a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233462030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3233462030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.159834963
Short name	T1056
Test name
Test status
Simulation time	18890558746 ps
CPU time	403.13 seconds
Started	Jan 03 01:19:30 PM PST 24
Finished	Jan 03 01:26:18 PM PST 24
Peak memory	254216 kb
Host	smart-6f991508-3a1c-4213-ae82-a76ad99722ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159834963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.159834963 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.2865332325
Short name	T815
Test name
Test status
Simulation time	3662088712 ps
CPU time	67.77 seconds
Started	Jan 03 01:19:11 PM PST 24
Finished	Jan 03 01:20:26 PM PST 24
Peak memory	225124 kb
Host	smart-613234c1-bf3c-41ae-aaaa-b43a137fceef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865332325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2865332325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.3757935279
Short name	T930
Test name
Test status
Simulation time	20766953 ps
CPU time	0.8 seconds
Started	Jan 03 01:19:57 PM PST 24
Finished	Jan 03 01:20:04 PM PST 24
Peak memory	218440 kb
Host	smart-9fc8854e-f9c6-4070-9139-ad2174e95c07
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3757935279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3757935279 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.1283019500
Short name	T108
Test name
Test status
Simulation time	95970700 ps
CPU time	0.99 seconds
Started	Jan 03 01:19:29 PM PST 24
Finished	Jan 03 01:19:35 PM PST 24
Peak memory	218540 kb
Host	smart-ca10ca3a-5458-4ea7-9fdc-a1b928618d2b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1283019500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1283019500 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.1805146296
Short name	T414
Test name
Test status
Simulation time	1604437593 ps
CPU time	9.95 seconds
Started	Jan 03 01:19:29 PM PST 24
Finished	Jan 03 01:19:44 PM PST 24
Peak memory	218788 kb
Host	smart-be47370b-7895-413f-bebc-7ad9095164c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805146296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1805146296 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.308711841
Short name	T230
Test name
Test status
Simulation time	19306596852 ps
CPU time	199.63 seconds
Started	Jan 03 01:19:19 PM PST 24
Finished	Jan 03 01:22:42 PM PST 24
Peak memory	241708 kb
Host	smart-01c8d46c-5031-4dde-b72b-a8a26c2801b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308711841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.308711841 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.1164490079
Short name	T989
Test name
Test status
Simulation time	9698374798 ps
CPU time	234.16 seconds
Started	Jan 03 01:19:29 PM PST 24
Finished	Jan 03 01:23:28 PM PST 24
Peak memory	253928 kb
Host	smart-dfb9c8d3-7825-4384-9495-95232e7b9f4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164490079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1164490079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.3996656822
Short name	T428
Test name
Test status
Simulation time	658207698 ps
CPU time	4.48 seconds
Started	Jan 03 01:19:51 PM PST 24
Finished	Jan 03 01:20:02 PM PST 24
Peak memory	218748 kb
Host	smart-303a583c-4361-4886-ad2a-adb268b23338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996656822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3996656822 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.3033169235
Short name	T1088
Test name
Test status
Simulation time	593756708 ps
CPU time	29.58 seconds
Started	Jan 03 01:20:00 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	237872 kb
Host	smart-c0190f01-eed3-4e5d-b318-5f8135e1d0fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033169235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3033169235 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.1692238920
Short name	T466
Test name
Test status
Simulation time	51994503962 ps
CPU time	662.77 seconds
Started	Jan 03 01:19:23 PM PST 24
Finished	Jan 03 01:30:30 PM PST 24
Peak memory	282236 kb
Host	smart-a8f95bd8-3081-404d-9fb2-15a0d9ae4dc9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692238920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.1692238920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.2519316049
Short name	T17
Test name
Test status
Simulation time	11635045011 ps
CPU time	146.97 seconds
Started	Jan 03 01:19:51 PM PST 24
Finished	Jan 03 01:22:25 PM PST 24
Peak memory	239300 kb
Host	smart-48d5584d-f961-47da-9eb8-97ea4a284e79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519316049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2519316049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sideload.1616856628
Short name	T1096
Test name
Test status
Simulation time	1695887165 ps
CPU time	63.37 seconds
Started	Jan 03 01:19:11 PM PST 24
Finished	Jan 03 01:20:21 PM PST 24
Peak memory	236736 kb
Host	smart-35903593-ac17-4ae4-add8-ed511666216c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616856628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1616856628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.2629980349
Short name	T256
Test name
Test status
Simulation time	1410126285 ps
CPU time	56.02 seconds
Started	Jan 03 01:19:08 PM PST 24
Finished	Jan 03 01:20:15 PM PST 24
Peak memory	224640 kb
Host	smart-c4ed5484-f027-4201-9b98-26130b93aa86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629980349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2629980349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.3411979396
Short name	T1089
Test name
Test status
Simulation time	34878000258 ps
CPU time	425.77 seconds
Started	Jan 03 01:19:33 PM PST 24
Finished	Jan 03 01:26:43 PM PST 24
Peak memory	242696 kb
Host	smart-e6b91e95-ff32-4e79-a290-97f58d7ef1a6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3411979396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3411979396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_stress_all_with_rand_reset.3589626336
Short name	T149
Test name
Test status
Simulation time	265304654517 ps
CPU time	1022.6 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:36:35 PM PST 24
Peak memory	276848 kb
Host	smart-3f3bf601-c07d-4b78-8f7b-8f404ac3d80c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3589626336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.3589626336 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.898882889
Short name	T323
Test name
Test status
Simulation time	652307169 ps
CPU time	5.84 seconds
Started	Jan 03 01:19:29 PM PST 24
Finished	Jan 03 01:19:40 PM PST 24
Peak memory	218780 kb
Host	smart-e6f1fa38-9618-498a-bb00-11884f90361b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898882889 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.kmac_test_vectors_kmac.898882889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3604207912
Short name	T354
Test name
Test status
Simulation time	247048096 ps
CPU time	5.93 seconds
Started	Jan 03 01:19:27 PM PST 24
Finished	Jan 03 01:19:38 PM PST 24
Peak memory	218696 kb
Host	smart-fa762c87-9b1e-4a36-90cd-cd0ed55cf45f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604207912 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3604207912 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.3154871596
Short name	T468
Test name
Test status
Simulation time	99752658094 ps
CPU time	2361.37 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:58:44 PM PST 24
Peak memory	393552 kb
Host	smart-d797b073-1f02-426e-8979-250a25e50463
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3154871596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3154871596 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.1712862046
Short name	T192
Test name
Test status
Simulation time	201017378007 ps
CPU time	2389.42 seconds
Started	Jan 03 01:19:16 PM PST 24
Finished	Jan 03 01:59:10 PM PST 24
Peak memory	399940 kb
Host	smart-bad53ecf-f81c-4cdc-93fe-4ed766011fa1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1712862046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1712862046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.3523415316
Short name	T982
Test name
Test status
Simulation time	258260620999 ps
CPU time	1629.12 seconds
Started	Jan 03 01:19:11 PM PST 24
Finished	Jan 03 01:46:27 PM PST 24
Peak memory	336480 kb
Host	smart-a12b702c-30c9-457c-b21e-e38f38982ca1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3523415316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3523415316 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.3904127676
Short name	T245
Test name
Test status
Simulation time	330351249213 ps
CPU time	1299.4 seconds
Started	Jan 03 01:19:21 PM PST 24
Finished	Jan 03 01:41:04 PM PST 24
Peak memory	300636 kb
Host	smart-04f35e5b-0a73-42cc-a270-0844943acfbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3904127676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3904127676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.1912928475
Short name	T1115
Test name
Test status
Simulation time	749699942408 ps
CPU time	5561.99 seconds
Started	Jan 03 01:19:17 PM PST 24
Finished	Jan 03 02:52:04 PM PST 24
Peak memory	676656 kb
Host	smart-4bf94ab5-3e03-4153-84a1-30552fb3f8b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1912928475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1912928475 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.2606793072
Short name	T220
Test name
Test status
Simulation time	471204697439 ps
CPU time	5145.13 seconds
Started	Jan 03 01:19:30 PM PST 24
Finished	Jan 03 02:45:21 PM PST 24
Peak memory	566592 kb
Host	smart-e209baeb-4590-482e-8018-fea96df4a66f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2606793072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2606793072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.1356626459
Short name	T521
Test name
Test status
Simulation time	17226435 ps
CPU time	0.85 seconds
Started	Jan 03 01:21:01 PM PST 24
Finished	Jan 03 01:21:08 PM PST 24
Peak memory	219736 kb
Host	smart-9e02717c-59b4-40e5-b593-95b2e1917045
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356626459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1356626459 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_app.129802815
Short name	T258
Test name
Test status
Simulation time	26343910260 ps
CPU time	317.41 seconds
Started	Jan 03 01:21:07 PM PST 24
Finished	Jan 03 01:26:28 PM PST 24
Peak memory	250676 kb
Host	smart-7e44ccbd-f265-47a7-924b-8939f2cf74d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=129802815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.129802815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.4096053605
Short name	T233
Test name
Test status
Simulation time	14150730224 ps
CPU time	889.81 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 01:35:38 PM PST 24
Peak memory	243312 kb
Host	smart-cb8c4fb7-3703-4d83-9b5f-bf22a5a79aa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096053605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.4096053605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.3074155147
Short name	T1085
Test name
Test status
Simulation time	11235757183 ps
CPU time	31.96 seconds
Started	Jan 03 01:21:07 PM PST 24
Finished	Jan 03 01:21:43 PM PST 24
Peak memory	243148 kb
Host	smart-5ec83234-256d-4822-8063-2b4143436437
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3074155147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3074155147 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.1445674925
Short name	T923
Test name
Test status
Simulation time	47138329 ps
CPU time	1.23 seconds
Started	Jan 03 01:21:03 PM PST 24
Finished	Jan 03 01:21:09 PM PST 24
Peak memory	218772 kb
Host	smart-ff2ff430-ea09-4338-bf0a-62dda1a0fd87
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1445674925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1445674925 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.3264000130
Short name	T950
Test name
Test status
Simulation time	16148221557 ps
CPU time	413.78 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 01:27:56 PM PST 24
Peak memory	254164 kb
Host	smart-f918e47e-3a73-495a-87a2-6ed63be03f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264000130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3264000130 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.3880736909
Short name	T156
Test name
Test status
Simulation time	3599213396 ps
CPU time	31.35 seconds
Started	Jan 03 01:21:01 PM PST 24
Finished	Jan 03 01:21:39 PM PST 24
Peak memory	235624 kb
Host	smart-6403b147-071b-470f-bfcf-7a27b968d8a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880736909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3880736909 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.3831918222
Short name	T693
Test name
Test status
Simulation time	1222134725 ps
CPU time	2.86 seconds
Started	Jan 03 01:21:02 PM PST 24
Finished	Jan 03 01:21:11 PM PST 24
Peak memory	218624 kb
Host	smart-79e42209-258c-44b2-89ca-cdf515cd6c2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831918222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3831918222 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.465817408
Short name	T350
Test name
Test status
Simulation time	36761375 ps
CPU time	1.4 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 01:21:01 PM PST 24
Peak memory	219732 kb
Host	smart-845c8fa5-6428-4c61-8e35-0e3eed69aaa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465817408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.465817408 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.2617993250
Short name	T893
Test name
Test status
Simulation time	18520778402 ps
CPU time	371.39 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:26:55 PM PST 24
Peak memory	254356 kb
Host	smart-cdb4bd35-6077-4879-951f-e1e6878509f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617993250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a nd_output.2617993250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.1698054363
Short name	T448
Test name
Test status
Simulation time	1039604254 ps
CPU time	29.44 seconds
Started	Jan 03 01:20:45 PM PST 24
Finished	Jan 03 01:21:23 PM PST 24
Peak memory	227364 kb
Host	smart-f588a261-7883-4976-a286-5dff719ecd3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698054363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1698054363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.3217910889
Short name	T865
Test name
Test status
Simulation time	3275939374 ps
CPU time	62.98 seconds
Started	Jan 03 01:20:39 PM PST 24
Finished	Jan 03 01:21:45 PM PST 24
Peak memory	226824 kb
Host	smart-32ec8c54-85b6-40c5-8eaf-7334117de55d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217910889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3217910889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.2092877597
Short name	T591
Test name
Test status
Simulation time	15932709399 ps
CPU time	104.34 seconds
Started	Jan 03 01:20:45 PM PST 24
Finished	Jan 03 01:22:38 PM PST 24
Peak memory	246176 kb
Host	smart-94882817-e0da-43a8-a102-852847751dd7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2092877597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2092877597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.3063110342
Short name	T360
Test name
Test status
Simulation time	566165941 ps
CPU time	5.16 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 01:21:05 PM PST 24
Peak memory	218700 kb
Host	smart-5197d43b-3c35-4413-8db8-e02da4e307d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063110342 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.3063110342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3333416553
Short name	T882
Test name
Test status
Simulation time	846741687 ps
CPU time	5.91 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 01:21:07 PM PST 24
Peak memory	218744 kb
Host	smart-c77d8aba-cb87-4aa6-b7ea-eba2b1908fdf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333416553 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3333416553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.347345189
Short name	T838
Test name
Test status
Simulation time	221688011074 ps
CPU time	2462.47 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 02:01:55 PM PST 24
Peak memory	400104 kb
Host	smart-20f7f658-b2d1-48dd-8ea4-2a353092cdab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=347345189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.347345189 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.123938667
Short name	T182
Test name
Test status
Simulation time	91656494602 ps
CPU time	1679.44 seconds
Started	Jan 03 01:20:47 PM PST 24
Finished	Jan 03 01:48:56 PM PST 24
Peak memory	388560 kb
Host	smart-a47d9687-9b4e-441c-878c-423481268754
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=123938667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.123938667 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.906954874
Short name	T526
Test name
Test status
Simulation time	48721997631 ps
CPU time	1674.21 seconds
Started	Jan 03 01:20:48 PM PST 24
Finished	Jan 03 01:48:53 PM PST 24
Peak memory	342908 kb
Host	smart-05a18580-73de-4973-97f5-434b67f57b72
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=906954874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.906954874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.922349561
Short name	T547
Test name
Test status
Simulation time	205620953887 ps
CPU time	1362.26 seconds
Started	Jan 03 01:20:57 PM PST 24
Finished	Jan 03 01:43:48 PM PST 24
Peak memory	303096 kb
Host	smart-4f5da712-2377-4b53-b0a6-84965e7f72a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=922349561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.922349561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.776807747
Short name	T1038
Test name
Test status
Simulation time	78362265075 ps
CPU time	4896.9 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 02:42:38 PM PST 24
Peak memory	653480 kb
Host	smart-3ddcc3f1-f10f-4936-b2d0-d778fd0a11b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=776807747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.776807747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.4283472318
Short name	T996
Test name
Test status
Simulation time	215800986847 ps
CPU time	4409.91 seconds
Started	Jan 03 01:20:46 PM PST 24
Finished	Jan 03 02:34:25 PM PST 24
Peak memory	563644 kb
Host	smart-9111b6f7-c81a-45f7-ae12-0fbe4622d018
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4283472318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.4283472318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.3886987487
Short name	T935
Test name
Test status
Simulation time	52858911 ps
CPU time	0.86 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:21:43 PM PST 24
Peak memory	218456 kb
Host	smart-a9fab5f6-b281-415d-b528-b2cf168bdef9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886987487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3886987487 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/11.kmac_app.3636595487
Short name	T1098
Test name
Test status
Simulation time	22179922699 ps
CPU time	233.96 seconds
Started	Jan 03 01:21:32 PM PST 24
Finished	Jan 03 01:25:31 PM PST 24
Peak memory	245784 kb
Host	smart-5bfe444a-5cc0-4083-9554-67c1f1a61741
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636595487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3636595487 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.3759512783
Short name	T176
Test name
Test status
Simulation time	3047770194 ps
CPU time	137.58 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 01:23:19 PM PST 24
Peak memory	227876 kb
Host	smart-6884072d-f0d4-4536-b5a6-bbe5d25687a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759512783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3759512783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.2322178504
Short name	T775
Test name
Test status
Simulation time	33059490 ps
CPU time	1.03 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:21:46 PM PST 24
Peak memory	218548 kb
Host	smart-52116e1e-6a44-4c3a-9ea2-f4e6c07901af
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2322178504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2322178504 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.43747427
Short name	T109
Test name
Test status
Simulation time	126843491 ps
CPU time	1.16 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:21:42 PM PST 24
Peak memory	218692 kb
Host	smart-7421cee6-d9f3-4d27-8471-439c3fffb29c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=43747427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.43747427 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.1698943002
Short name	T188
Test name
Test status
Simulation time	60922606091 ps
CPU time	232.78 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:25:35 PM PST 24
Peak memory	243436 kb
Host	smart-b50735b7-13b9-4b90-851a-ce0a3eddc320
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698943002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1698943002 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.2862073105
Short name	T329
Test name
Test status
Simulation time	16073659421 ps
CPU time	195.41 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:25:03 PM PST 24
Peak memory	259808 kb
Host	smart-ac964ab6-70b0-4e7a-9606-2b90987637c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862073105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2862073105 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.2331749106
Short name	T799
Test name
Test status
Simulation time	71883146 ps
CPU time	1.15 seconds
Started	Jan 03 01:21:32 PM PST 24
Finished	Jan 03 01:21:38 PM PST 24
Peak memory	218472 kb
Host	smart-fb0195c1-3fba-4ade-8fa7-2dccc2111b2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331749106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2331749106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.2623559869
Short name	T756
Test name
Test status
Simulation time	624534565 ps
CPU time	13.29 seconds
Started	Jan 03 01:21:32 PM PST 24
Finished	Jan 03 01:21:50 PM PST 24
Peak memory	231040 kb
Host	smart-63705177-e794-424c-b2c1-d915eb21171e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623559869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2623559869 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.1882057227
Short name	T1034
Test name
Test status
Simulation time	73404134192 ps
CPU time	2074.97 seconds
Started	Jan 03 01:21:00 PM PST 24
Finished	Jan 03 01:55:42 PM PST 24
Peak memory	414512 kb
Host	smart-edf43c68-71d6-4fcb-a7c8-08806b080e18
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882057227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.1882057227 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.1623230210
Short name	T587
Test name
Test status
Simulation time	18586177005 ps
CPU time	286.81 seconds
Started	Jan 03 01:21:01 PM PST 24
Finished	Jan 03 01:25:54 PM PST 24
Peak memory	248500 kb
Host	smart-35e267ba-0200-4c57-81b2-9112c5af564a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623230210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1623230210 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.1290754788
Short name	T614
Test name
Test status
Simulation time	9741160823 ps
CPU time	48.06 seconds
Started	Jan 03 01:21:18 PM PST 24
Finished	Jan 03 01:22:08 PM PST 24
Peak memory	224764 kb
Host	smart-e031f078-4fd0-4f8e-8a7d-c9354321ec27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290754788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1290754788 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.1281537650
Short name	T375
Test name
Test status
Simulation time	1594041302 ps
CPU time	78.82 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 01:23:08 PM PST 24
Peak memory	243492 kb
Host	smart-778a4bb2-e53f-4cbe-b375-6a27d332cb96
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1281537650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1281537650 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_stress_all_with_rand_reset.2451521553
Short name	T523
Test name
Test status
Simulation time	42657083441 ps
CPU time	688.24 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 01:33:18 PM PST 24
Peak memory	291760 kb
Host	smart-e6423898-f66b-4d29-9495-575d1239b15f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2451521553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all_with_rand_reset.2451521553 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.2255054519
Short name	T302
Test name
Test status
Simulation time	841252746 ps
CPU time	6.49 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:21:47 PM PST 24
Peak memory	218872 kb
Host	smart-561cc25a-ffd4-4d08-a0f7-f03219760472
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255054519 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.2255054519 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1533314395
Short name	T788
Test name
Test status
Simulation time	1127293392 ps
CPU time	6.89 seconds
Started	Jan 03 01:21:18 PM PST 24
Finished	Jan 03 01:21:26 PM PST 24
Peak memory	218676 kb
Host	smart-7a09c770-c280-4244-ad76-24bccccb0558
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533314395 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1533314395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.768668786
Short name	T369
Test name
Test status
Simulation time	88225471666 ps
CPU time	2103.75 seconds
Started	Jan 03 01:20:47 PM PST 24
Finished	Jan 03 01:56:01 PM PST 24
Peak memory	398456 kb
Host	smart-12a26c81-6c91-4d34-b1a0-a3e4feb86729
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=768668786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.768668786 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.3744667943
Short name	T477
Test name
Test status
Simulation time	62669904939 ps
CPU time	2084.88 seconds
Started	Jan 03 01:21:15 PM PST 24
Finished	Jan 03 01:56:02 PM PST 24
Peak memory	386832 kb
Host	smart-e8f969b5-0830-4209-98db-ebc578f42303
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3744667943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3744667943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.3621491387
Short name	T1003
Test name
Test status
Simulation time	49861653467 ps
CPU time	1667.39 seconds
Started	Jan 03 01:21:08 PM PST 24
Finished	Jan 03 01:48:59 PM PST 24
Peak memory	343720 kb
Host	smart-11de6520-a520-47d4-9552-c5261b36cd62
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3621491387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3621491387 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.4026882820
Short name	T1134
Test name
Test status
Simulation time	33658476874 ps
CPU time	1294.06 seconds
Started	Jan 03 01:20:52 PM PST 24
Finished	Jan 03 01:42:37 PM PST 24
Peak memory	301540 kb
Host	smart-ba15e7a3-6a33-430c-8027-dfe83ba194b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4026882820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.4026882820 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.3150597797
Short name	T310
Test name
Test status
Simulation time	1982012635113 ps
CPU time	5242.1 seconds
Started	Jan 03 01:21:33 PM PST 24
Finished	Jan 03 02:49:01 PM PST 24
Peak memory	659712 kb
Host	smart-ae1097b0-0608-494f-9bb9-f7b63b3d1664
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3150597797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.3150597797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.2615366815
Short name	T386
Test name
Test status
Simulation time	368016465440 ps
CPU time	4671.17 seconds
Started	Jan 03 01:21:17 PM PST 24
Finished	Jan 03 02:39:10 PM PST 24
Peak memory	574196 kb
Host	smart-d4ffeb22-3986-45ee-824f-7d6fb198eeac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2615366815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2615366815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.376712581
Short name	T817
Test name
Test status
Simulation time	45514987 ps
CPU time	0.86 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:21:52 PM PST 24
Peak memory	219748 kb
Host	smart-5df4bc7c-8aa3-42a1-ae82-19eb21232a01
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376712581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.376712581 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.238706770
Short name	T251
Test name
Test status
Simulation time	7964379605 ps
CPU time	58.92 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:22:45 PM PST 24
Peak memory	230892 kb
Host	smart-207fd5d9-4362-4472-ad83-b81635240df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238706770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.238706770 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.1008257652
Short name	T384
Test name
Test status
Simulation time	105393502646 ps
CPU time	1204.9 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:41:53 PM PST 24
Peak memory	243260 kb
Host	smart-3704c2d8-639a-4cd3-a0e0-db19d42c56c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008257652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1008257652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.3212632413
Short name	T312
Test name
Test status
Simulation time	12655976693 ps
CPU time	46.97 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:22:33 PM PST 24
Peak memory	243240 kb
Host	smart-770709a9-1622-4c75-a4c2-3310a478e650
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3212632413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3212632413 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.4277218863
Short name	T569
Test name
Test status
Simulation time	1537466986 ps
CPU time	43.36 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:22:23 PM PST 24
Peak memory	236624 kb
Host	smart-8c856361-d621-445e-ab31-2735ae46bc75
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4277218863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4277218863 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_error.3676289553
Short name	T358
Test name
Test status
Simulation time	76129358296 ps
CPU time	514.39 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:30:15 PM PST 24
Peak memory	275768 kb
Host	smart-5ecaafc1-ee9b-468c-9297-581c72e023a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676289553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3676289553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.2462933275
Short name	T378
Test name
Test status
Simulation time	3432920013 ps
CPU time	7.21 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:21:54 PM PST 24
Peak memory	218816 kb
Host	smart-756d8318-21c1-4092-8124-c2aaaa01e574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462933275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2462933275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.4091827285
Short name	T616
Test name
Test status
Simulation time	89945232 ps
CPU time	1.45 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:21:49 PM PST 24
Peak memory	219900 kb
Host	smart-58fc94bf-090c-4305-98b5-562d2c5dc469
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091827285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.4091827285 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.4186546102
Short name	T868
Test name
Test status
Simulation time	199449179073 ps
CPU time	1839.08 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:52:22 PM PST 24
Peak memory	359772 kb
Host	smart-5a80aa8e-4bfc-4a71-8374-53286e221c04
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186546102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.4186546102 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.1781305229
Short name	T212
Test name
Test status
Simulation time	1420142278 ps
CPU time	10.06 seconds
Started	Jan 03 01:21:34 PM PST 24
Finished	Jan 03 01:21:50 PM PST 24
Peak memory	224312 kb
Host	smart-df2845ef-b68f-4ddc-8179-da94f27a093c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781305229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1781305229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.4029329300
Short name	T387
Test name
Test status
Simulation time	3777867311 ps
CPU time	76.72 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 01:23:06 PM PST 24
Peak memory	227064 kb
Host	smart-c2b4a725-d5a8-4db3-8f5a-bbd859869be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029329300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.4029329300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.544560816
Short name	T816
Test name
Test status
Simulation time	42806792005 ps
CPU time	774.72 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:34:46 PM PST 24
Peak memory	306964 kb
Host	smart-6dcdfb8a-20f5-47a4-b184-460c5a92e67d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=544560816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.544560816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_stress_all_with_rand_reset.1861855063
Short name	T1080
Test name
Test status
Simulation time	492492865218 ps
CPU time	2960.5 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 02:11:04 PM PST 24
Peak memory	373748 kb
Host	smart-519c7a74-82a5-4177-a37c-445b6cfaff11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1861855063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.1861855063 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.3382686195
Short name	T1021
Test name
Test status
Simulation time	264646366 ps
CPU time	6.27 seconds
Started	Jan 03 01:21:21 PM PST 24
Finished	Jan 03 01:21:29 PM PST 24
Peak memory	218820 kb
Host	smart-e28d61a6-4548-4bfe-8e5b-d8b6450547f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382686195 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.3382686195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1155825703
Short name	T702
Test name
Test status
Simulation time	643364420 ps
CPU time	6.07 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:21:46 PM PST 24
Peak memory	218924 kb
Host	smart-ffdb431b-cf36-499d-b1ef-73f14317e6f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155825703 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1155825703 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.1842317486
Short name	T841
Test name
Test status
Simulation time	40893913552 ps
CPU time	2115.96 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:56:57 PM PST 24
Peak memory	396276 kb
Host	smart-add0a0a0-fae6-41a1-aafb-dd81ae3217a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1842317486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1842317486 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.3040275109
Short name	T991
Test name
Test status
Simulation time	774769152287 ps
CPU time	2263.09 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:59:32 PM PST 24
Peak memory	390064 kb
Host	smart-2b98abb7-9cb4-426b-8923-8d5ccc6051b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3040275109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3040275109 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.2324741196
Short name	T1099
Test name
Test status
Simulation time	204086677859 ps
CPU time	1703.08 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:50:11 PM PST 24
Peak memory	338288 kb
Host	smart-f3907d4d-f946-423f-80bf-e663c992ba21
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2324741196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2324741196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.2998478123
Short name	T645
Test name
Test status
Simulation time	10821237101 ps
CPU time	1191.61 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:40:42 PM PST 24
Peak memory	303300 kb
Host	smart-648f711e-27bf-408c-891b-dc049f1addaa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2998478123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2998478123 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.805541927
Short name	T861
Test name
Test status
Simulation time	185376912145 ps
CPU time	5362.54 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 02:50:11 PM PST 24
Peak memory	663020 kb
Host	smart-fc0513c4-4714-42f0-8963-f37bd9223454
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=805541927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.805541927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.2475840276
Short name	T958
Test name
Test status
Simulation time	2188291896683 ps
CPU time	4925.04 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 02:42:55 PM PST 24
Peak memory	584136 kb
Host	smart-5bba70da-ae2a-4873-b2a8-7b8f32516d99
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2475840276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2475840276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.2611676973
Short name	T1024
Test name
Test status
Simulation time	24424665 ps
CPU time	0.84 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:21:41 PM PST 24
Peak memory	218476 kb
Host	smart-1b3fbf3f-39d5-4cfd-b403-55d977b5edb7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611676973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2611676973 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.4072969541
Short name	T1133
Test name
Test status
Simulation time	21830104004 ps
CPU time	212.61 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:25:21 PM PST 24
Peak memory	245332 kb
Host	smart-dfe0899d-9051-42db-8dbd-3a9b33fde83c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072969541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.4072969541 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.1104997125
Short name	T272
Test name
Test status
Simulation time	11460812324 ps
CPU time	570.71 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:31:22 PM PST 24
Peak memory	243056 kb
Host	smart-a3fb2770-5b19-48e6-8212-4aeb7a2742a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104997125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1104997125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.3783041890
Short name	T542
Test name
Test status
Simulation time	2601425553 ps
CPU time	56.08 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:22:49 PM PST 24
Peak memory	230544 kb
Host	smart-4cc97012-c4b5-4189-9d0b-ab08dee39aa0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3783041890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3783041890 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.246147837
Short name	T266
Test name
Test status
Simulation time	23525922 ps
CPU time	1.15 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:21:53 PM PST 24
Peak memory	218900 kb
Host	smart-96f2f81a-908b-4c8a-ba56-a92fe425776d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=246147837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.246147837 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.3815457350
Short name	T85
Test name
Test status
Simulation time	15646505306 ps
CPU time	255.26 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:26:08 PM PST 24
Peak memory	246208 kb
Host	smart-c0842d58-e22a-4621-817e-8ee7b40486d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815457350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3815457350 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.2227621032
Short name	T889
Test name
Test status
Simulation time	5132136218 ps
CPU time	202.88 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:25:15 PM PST 24
Peak memory	253764 kb
Host	smart-56a9aaed-cabf-4e7c-8479-02c92a7289d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227621032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2227621032 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.1481461299
Short name	T620
Test name
Test status
Simulation time	1945836520 ps
CPU time	5.32 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	218632 kb
Host	smart-11d00c08-852d-4f62-ba9a-4490a26b5ba5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481461299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1481461299 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.3458980708
Short name	T423
Test name
Test status
Simulation time	35331206 ps
CPU time	1.37 seconds
Started	Jan 03 01:21:20 PM PST 24
Finished	Jan 03 01:21:23 PM PST 24
Peak memory	220496 kb
Host	smart-6534872b-019a-4a92-8111-4b69457bb185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458980708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3458980708 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.1901694891
Short name	T878
Test name
Test status
Simulation time	1351548929554 ps
CPU time	2623.5 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 02:05:34 PM PST 24
Peak memory	422328 kb
Host	smart-23b58f0b-b992-4591-aa08-b4506f1b66a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901694891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.1901694891 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.2218800488
Short name	T305
Test name
Test status
Simulation time	1037338806 ps
CPU time	37.58 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 01:22:27 PM PST 24
Peak memory	226636 kb
Host	smart-41c39a56-b97e-4a60-9a69-53721b06fd53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218800488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2218800488 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.3810095656
Short name	T773
Test name
Test status
Simulation time	2778871076 ps
CPU time	27.95 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:22:15 PM PST 24
Peak memory	223724 kb
Host	smart-7839df55-126a-43be-a234-c3a899abe2cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810095656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3810095656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.816742902
Short name	T504
Test name
Test status
Simulation time	211291995836 ps
CPU time	2100.88 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:56:42 PM PST 24
Peak memory	398592 kb
Host	smart-df882e0e-0265-4295-846f-e12ff3f30d6c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=816742902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.816742902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_stress_all_with_rand_reset.1183394866
Short name	T981
Test name
Test status
Simulation time	139639052137 ps
CPU time	832.77 seconds
Started	Jan 03 01:21:31 PM PST 24
Finished	Jan 03 01:35:29 PM PST 24
Peak memory	309188 kb
Host	smart-4e4aa1c4-ca50-4b33-9f52-b93804366466
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1183394866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.1183394866 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.2739325435
Short name	T1010
Test name
Test status
Simulation time	259468001 ps
CPU time	6.24 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:21:57 PM PST 24
Peak memory	218872 kb
Host	smart-85a810aa-4f2a-47e9-9671-01c54ea4bb10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739325435 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.kmac_test_vectors_kmac.2739325435 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2361626046
Short name	T872
Test name
Test status
Simulation time	721003165 ps
CPU time	6.18 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:21:58 PM PST 24
Peak memory	218692 kb
Host	smart-5ea0919e-38b1-457f-a81d-735799bbcf08
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361626046 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2361626046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.1640692750
Short name	T667
Test name
Test status
Simulation time	82113145574 ps
CPU time	1927.4 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:53:56 PM PST 24
Peak memory	398420 kb
Host	smart-5686a3d9-1898-4549-9050-986bbde6c3be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1640692750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1640692750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.2984484770
Short name	T980
Test name
Test status
Simulation time	78359871620 ps
CPU time	1896.02 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:53:27 PM PST 24
Peak memory	381920 kb
Host	smart-cba7c057-8646-484c-8ff1-d42213d35a48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2984484770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2984484770 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.2155509036
Short name	T490
Test name
Test status
Simulation time	686496371720 ps
CPU time	1835.13 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:52:27 PM PST 24
Peak memory	346104 kb
Host	smart-d0dfe1e8-1b5d-4e9d-a1bf-a7c543b14117
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2155509036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2155509036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.2208342759
Short name	T185
Test name
Test status
Simulation time	195804438976 ps
CPU time	1347.04 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:44:19 PM PST 24
Peak memory	301148 kb
Host	smart-06075b8c-65f9-4b8a-b178-e9bf22657afa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2208342759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2208342759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.3321688922
Short name	T373
Test name
Test status
Simulation time	122064533461 ps
CPU time	4828.92 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 02:42:19 PM PST 24
Peak memory	645484 kb
Host	smart-ab9a6804-5641-4ddd-9ab3-ab7a6b89f6fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3321688922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3321688922 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.3195202029
Short name	T904
Test name
Test status
Simulation time	433797600108 ps
CPU time	4939.06 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 02:44:10 PM PST 24
Peak memory	570540 kb
Host	smart-5a91025d-0c3e-4195-99a7-80584a958a60
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3195202029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3195202029 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.1960964147
Short name	T1135
Test name
Test status
Simulation time	14394109 ps
CPU time	0.81 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:21:54 PM PST 24
Peak memory	218492 kb
Host	smart-b0e6da6a-b9aa-437d-b6e9-61a7281bc1e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960964147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1960964147 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.2760729892
Short name	T335
Test name
Test status
Simulation time	1680162077 ps
CPU time	69.29 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:23:02 PM PST 24
Peak memory	232320 kb
Host	smart-1a5d0b47-055d-4c4f-8c1e-522bbe98d94f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760729892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2760729892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.2006468317
Short name	T1125
Test name
Test status
Simulation time	13952538944 ps
CPU time	1387.15 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:44:50 PM PST 24
Peak memory	243372 kb
Host	smart-289f805c-3257-4a61-815a-399e1f0bbfe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006468317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2006468317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.4216167415
Short name	T972
Test name
Test status
Simulation time	3906031574 ps
CPU time	47.35 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:22:39 PM PST 24
Peak memory	229436 kb
Host	smart-45b7181e-8af3-4d14-b107-ad98b1e746b7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4216167415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.4216167415 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.1471006680
Short name	T361
Test name
Test status
Simulation time	41334968 ps
CPU time	0.83 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:21:52 PM PST 24
Peak memory	218444 kb
Host	smart-e1498765-45dd-4bca-ae0c-407d8fae9d58
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1471006680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1471006680 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.2789660184
Short name	T905
Test name
Test status
Simulation time	25008161653 ps
CPU time	255.51 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:26:04 PM PST 24
Peak memory	246688 kb
Host	smart-fc47ccac-1768-4b19-8627-b46be1fcfdfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789660184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2789660184 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.3939865486
Short name	T567
Test name
Test status
Simulation time	21960049514 ps
CPU time	335.42 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:27:27 PM PST 24
Peak memory	267960 kb
Host	smart-ccb2fe15-f48e-48c5-ba9c-c6724b651430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939865486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3939865486 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.3280635366
Short name	T581
Test name
Test status
Simulation time	3912284123 ps
CPU time	6.86 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:21:53 PM PST 24
Peak memory	218792 kb
Host	smart-fb261c59-ba34-41d9-abd7-a1bec5ab6810
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280635366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3280635366 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.4045681019
Short name	T871
Test name
Test status
Simulation time	148737388 ps
CPU time	1.33 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 01:21:51 PM PST 24
Peak memory	219952 kb
Host	smart-7cce1fad-4d44-4459-97b4-68a6c3973b32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045681019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.4045681019 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.77242457
Short name	T979
Test name
Test status
Simulation time	355370192730 ps
CPU time	1941.17 seconds
Started	Jan 03 01:21:34 PM PST 24
Finished	Jan 03 01:54:00 PM PST 24
Peak memory	374248 kb
Host	smart-7f6bf7e2-f070-4226-afa7-738f696f4fdf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77242457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and _output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and _output.77242457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.1507538909
Short name	T38
Test name
Test status
Simulation time	15005967575 ps
CPU time	471.11 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:29:31 PM PST 24
Peak memory	256868 kb
Host	smart-8c817652-0835-47d0-83d2-ad091d0744ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507538909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1507538909 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.1225257222
Short name	T315
Test name
Test status
Simulation time	8305264108 ps
CPU time	93.64 seconds
Started	Jan 03 01:21:31 PM PST 24
Finished	Jan 03 01:23:09 PM PST 24
Peak memory	226816 kb
Host	smart-532dd73c-5ee4-4f39-8125-9aa469b0877e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225257222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1225257222 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.1646891683
Short name	T533
Test name
Test status
Simulation time	36991252782 ps
CPU time	669.71 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:33:01 PM PST 24
Peak memory	254028 kb
Host	smart-23534a25-db10-417f-869c-fe0714a8618a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1646891683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1646891683 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_stress_all_with_rand_reset.1519441771
Short name	T853
Test name
Test status
Simulation time	99755446113 ps
CPU time	415.99 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:28:48 PM PST 24
Peak memory	270400 kb
Host	smart-d180d262-f955-444e-9699-3a893159509a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1519441771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.1519441771 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.1960672479
Short name	T834
Test name
Test status
Simulation time	262262981 ps
CPU time	5.91 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:21:53 PM PST 24
Peak memory	220336 kb
Host	smart-e56f75d2-0280-47fd-895f-5dab44b301f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960672479 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.1960672479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3602841898
Short name	T240
Test name
Test status
Simulation time	126704413 ps
CPU time	5.59 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	220288 kb
Host	smart-f38b9274-d7ca-4eae-b997-ccad6ca9cfb2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602841898 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3602841898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.1417404358
Short name	T774
Test name
Test status
Simulation time	198153432502 ps
CPU time	2209.21 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:58:36 PM PST 24
Peak memory	399460 kb
Host	smart-fa91bd9d-40ec-4d1c-ab81-969215994375
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1417404358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.1417404358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.1602011972
Short name	T341
Test name
Test status
Simulation time	103549360528 ps
CPU time	2368.43 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 02:01:12 PM PST 24
Peak memory	389292 kb
Host	smart-aa851118-95d2-4be3-b3a8-c28182f9439d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1602011972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1602011972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.4235553354
Short name	T945
Test name
Test status
Simulation time	156278538981 ps
CPU time	1831.8 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:52:14 PM PST 24
Peak memory	339104 kb
Host	smart-6997819e-70c6-4a23-8df6-59b770ba2dbb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4235553354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.4235553354 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.3511485459
Short name	T536
Test name
Test status
Simulation time	12137937404 ps
CPU time	1219.12 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:42:01 PM PST 24
Peak memory	304372 kb
Host	smart-9087e5f4-a586-43c0-91b5-3fdcefa27779
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3511485459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3511485459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.1817667942
Short name	T1036
Test name
Test status
Simulation time	910285380652 ps
CPU time	5523.8 seconds
Started	Jan 03 01:21:33 PM PST 24
Finished	Jan 03 02:53:42 PM PST 24
Peak memory	658760 kb
Host	smart-08f898d0-65e9-4455-ad52-25cdd2ac3b32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1817667942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.1817667942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.4244082269
Short name	T978
Test name
Test status
Simulation time	218086598337 ps
CPU time	4689.88 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 02:39:52 PM PST 24
Peak memory	568792 kb
Host	smart-73715026-be36-4a92-8688-4a63b10e3980
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4244082269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.4244082269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.3482767889
Short name	T956
Test name
Test status
Simulation time	39256635 ps
CPU time	0.91 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 01:21:50 PM PST 24
Peak memory	219716 kb
Host	smart-994ff4e0-b996-4064-bcc0-b9ad4a8181c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482767889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3482767889 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.2592672749
Short name	T863
Test name
Test status
Simulation time	3975735204 ps
CPU time	255.69 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:26:09 PM PST 24
Peak memory	248308 kb
Host	smart-273d33a6-5a2f-43df-b6b3-e4c0ca287a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592672749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2592672749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.2439553500
Short name	T892
Test name
Test status
Simulation time	15736147549 ps
CPU time	716.03 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:33:48 PM PST 24
Peak memory	243464 kb
Host	smart-5e300912-50f0-4dbd-9f01-38cc1325ded6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439553500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2439553500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.2591044987
Short name	T971
Test name
Test status
Simulation time	8454014043 ps
CPU time	54.95 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:22:49 PM PST 24
Peak memory	238116 kb
Host	smart-89ef834b-eca0-47c8-8448-46dd948d7da1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2591044987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2591044987 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.175349388
Short name	T261
Test name
Test status
Simulation time	37718175 ps
CPU time	1.1 seconds
Started	Jan 03 01:21:57 PM PST 24
Finished	Jan 03 01:22:03 PM PST 24
Peak memory	218560 kb
Host	smart-b3bcc81d-3980-4ddf-9c12-36a8cfed877d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=175349388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.175349388 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.942607941
Short name	T496
Test name
Test status
Simulation time	1517489785 ps
CPU time	21.08 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:22:15 PM PST 24
Peak memory	228064 kb
Host	smart-9a662f61-188b-4dc5-9f83-b375c19af450
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942607941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.942607941 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.247045695
Short name	T1097
Test name
Test status
Simulation time	24025665624 ps
CPU time	397.17 seconds
Started	Jan 03 01:21:59 PM PST 24
Finished	Jan 03 01:28:40 PM PST 24
Peak memory	259400 kb
Host	smart-bce28f16-91aa-4c0f-879c-77f4415a17fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=247045695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.247045695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.1703356992
Short name	T416
Test name
Test status
Simulation time	1454762514 ps
CPU time	4.86 seconds
Started	Jan 03 01:21:48 PM PST 24
Finished	Jan 03 01:22:00 PM PST 24
Peak memory	218600 kb
Host	smart-167b77cb-120b-406a-973b-ae0da47daaf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703356992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1703356992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.3552020456
Short name	T998
Test name
Test status
Simulation time	57684545 ps
CPU time	1.35 seconds
Started	Jan 03 01:21:54 PM PST 24
Finished	Jan 03 01:22:01 PM PST 24
Peak memory	219956 kb
Host	smart-24087be5-37f7-4292-a932-8c6b4e8a1b7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552020456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3552020456 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.1560848031
Short name	T986
Test name
Test status
Simulation time	71406236395 ps
CPU time	1799.8 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:51:51 PM PST 24
Peak memory	394196 kb
Host	smart-bc207d35-4b19-4e2d-a619-cc2e08a5eee2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560848031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a nd_output.1560848031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.1402800120
Short name	T778
Test name
Test status
Simulation time	2852197789 ps
CPU time	239.85 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:25:52 PM PST 24
Peak memory	243188 kb
Host	smart-a0434361-3972-489d-885c-b6e3d7ed6451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402800120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1402800120 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.2841761052
Short name	T763
Test name
Test status
Simulation time	700096797 ps
CPU time	14.21 seconds
Started	Jan 03 01:21:41 PM PST 24
Finished	Jan 03 01:22:04 PM PST 24
Peak memory	226880 kb
Host	smart-0e8c6a59-0ec1-4227-8d2e-4c050f4b9916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841761052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2841761052 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.1509925522
Short name	T931
Test name
Test status
Simulation time	174276871592 ps
CPU time	916.35 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:37:08 PM PST 24
Peak memory	283592 kb
Host	smart-fa021fda-7054-493e-8d3e-7f90168d10c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1509925522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.1509925522 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.1571421087
Short name	T926
Test name
Test status
Simulation time	369492966 ps
CPU time	5.5 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:21:59 PM PST 24
Peak memory	218640 kb
Host	smart-a7470318-bd86-481a-bcad-69250366efad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571421087 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.1571421087 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3522834295
Short name	T566
Test name
Test status
Simulation time	455466028 ps
CPU time	5.38 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:21:58 PM PST 24
Peak memory	218804 kb
Host	smart-0ef30404-f4e4-43e8-b0aa-70cb1389e27f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522834295 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3522834295 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.1624394322
Short name	T1117
Test name
Test status
Simulation time	401254846727 ps
CPU time	2301.52 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 02:00:13 PM PST 24
Peak memory	395972 kb
Host	smart-df119148-e2d0-4747-bbdc-9c466980684a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1624394322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1624394322 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.174304846
Short name	T634
Test name
Test status
Simulation time	469054076097 ps
CPU time	2195.86 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:58:28 PM PST 24
Peak memory	387232 kb
Host	smart-52c24e24-f204-43b6-afd6-60aff4d50e32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=174304846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.174304846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.959041987
Short name	T434
Test name
Test status
Simulation time	16455759181 ps
CPU time	1613.53 seconds
Started	Jan 03 01:21:47 PM PST 24
Finished	Jan 03 01:48:48 PM PST 24
Peak memory	337620 kb
Host	smart-95b32097-ff66-465b-a2fb-b3c0b8f6ddfa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=959041987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.959041987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.3904811514
Short name	T1008
Test name
Test status
Simulation time	88525538043 ps
CPU time	1329.69 seconds
Started	Jan 03 01:21:47 PM PST 24
Finished	Jan 03 01:44:04 PM PST 24
Peak memory	306040 kb
Host	smart-82320cd2-e354-4eb4-98d2-be67e1d918b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3904811514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.3904811514 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.3238033430
Short name	T887
Test name
Test status
Simulation time	60305139928 ps
CPU time	4617.76 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 02:38:52 PM PST 24
Peak memory	662828 kb
Host	smart-e67423b5-da67-4157-aa51-0a038cc2c859
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3238033430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3238033430 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.630537182
Short name	T36
Test name
Test status
Simulation time	218064046451 ps
CPU time	4403.92 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 02:35:16 PM PST 24
Peak memory	569072 kb
Host	smart-ef356f30-4145-4c14-b654-13339ed8e30d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=630537182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.630537182 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.912906970
Short name	T914
Test name
Test status
Simulation time	60936649 ps
CPU time	0.81 seconds
Started	Jan 03 01:21:59 PM PST 24
Finished	Jan 03 01:22:04 PM PST 24
Peak memory	219740 kb
Host	smart-5dc311ea-cfc1-422f-a306-da4bc32bff86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912906970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.912906970 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.1356722221
Short name	T278
Test name
Test status
Simulation time	5393516166 ps
CPU time	317.06 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:27:11 PM PST 24
Peak memory	253268 kb
Host	smart-a02c8ba2-1ff9-474f-ab41-8efd15407c67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356722221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1356722221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.2970698376
Short name	T907
Test name
Test status
Simulation time	40520335567 ps
CPU time	744.88 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:34:18 PM PST 24
Peak memory	238152 kb
Host	smart-1e528778-b350-47ff-81ff-7327bd855362
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970698376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2970698376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.2456776763
Short name	T484
Test name
Test status
Simulation time	640260851 ps
CPU time	27.38 seconds
Started	Jan 03 01:21:47 PM PST 24
Finished	Jan 03 01:22:22 PM PST 24
Peak memory	226728 kb
Host	smart-20306900-66e7-44c5-bf42-9cd6f784b93e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2456776763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2456776763 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.2323386255
Short name	T107
Test name
Test status
Simulation time	81192628 ps
CPU time	1.04 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	218808 kb
Host	smart-455e938a-a1dc-47eb-8057-9e123730cac7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2323386255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2323386255 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.1014647851
Short name	T701
Test name
Test status
Simulation time	23822986504 ps
CPU time	309.93 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:27:03 PM PST 24
Peak memory	249764 kb
Host	smart-cc8609c1-1e3d-4d88-afe1-c9934b60ed50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014647851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1014647851 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.2732689162
Short name	T734
Test name
Test status
Simulation time	16847096881 ps
CPU time	471.21 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:29:45 PM PST 24
Peak memory	267820 kb
Host	smart-3c7241e0-af7c-4780-9e0d-33dceb9adb6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732689162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2732689162 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.824105448
Short name	T839
Test name
Test status
Simulation time	665129614 ps
CPU time	2.59 seconds
Started	Jan 03 01:21:59 PM PST 24
Finished	Jan 03 01:22:06 PM PST 24
Peak memory	218656 kb
Host	smart-96fe315b-20f8-4588-afa1-974cbb0afd07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824105448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.824105448 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.3808703440
Short name	T281
Test name
Test status
Simulation time	82733756 ps
CPU time	1.42 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	219944 kb
Host	smart-83685230-4c90-43a1-8234-81c5c1f30a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808703440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3808703440 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.2998862261
Short name	T818
Test name
Test status
Simulation time	20479607659 ps
CPU time	1857.74 seconds
Started	Jan 03 01:21:42 PM PST 24
Finished	Jan 03 01:52:49 PM PST 24
Peak memory	401712 kb
Host	smart-4289a96d-1f83-4fab-9611-4f10be3f77c7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998862261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.2998862261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.975106257
Short name	T227
Test name
Test status
Simulation time	13064982318 ps
CPU time	336.21 seconds
Started	Jan 03 01:21:47 PM PST 24
Finished	Jan 03 01:27:31 PM PST 24
Peak memory	250296 kb
Host	smart-886c5ccb-f12b-4930-81d5-72cdf186a306
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975106257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.975106257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.1153522798
Short name	T767
Test name
Test status
Simulation time	78839998 ps
CPU time	3.95 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	226892 kb
Host	smart-03a30099-6c97-4753-8a70-bca5927e89df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153522798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1153522798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.2363391304
Short name	T921
Test name
Test status
Simulation time	70001738782 ps
CPU time	516.08 seconds
Started	Jan 03 01:21:47 PM PST 24
Finished	Jan 03 01:30:31 PM PST 24
Peak memory	271944 kb
Host	smart-c4bd4c9b-28b5-467c-85a5-03731b3a9802
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2363391304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2363391304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_stress_all_with_rand_reset.2260695285
Short name	T331
Test name
Test status
Simulation time	224360433574 ps
CPU time	3626.77 seconds
Started	Jan 03 01:21:49 PM PST 24
Finished	Jan 03 02:22:24 PM PST 24
Peak memory	435748 kb
Host	smart-06fe00b0-25a0-44e8-9145-2ce55303e119
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2260695285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.2260695285 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.113266442
Short name	T186
Test name
Test status
Simulation time	563001137 ps
CPU time	6.58 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:22:00 PM PST 24
Peak memory	220108 kb
Host	smart-e2939a29-257e-468b-a824-e7d2e7964e24
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113266442 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.kmac_test_vectors_kmac.113266442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.942157848
Short name	T458
Test name
Test status
Simulation time	232877842 ps
CPU time	5.48 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:21:59 PM PST 24
Peak memory	220012 kb
Host	smart-3655fb1b-99f1-4cc5-bbc6-197adfbf74c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942157848 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.kmac_test_vectors_kmac_xof.942157848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.3758538285
Short name	T729
Test name
Test status
Simulation time	40920682518 ps
CPU time	2002.97 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:55:11 PM PST 24
Peak memory	401272 kb
Host	smart-aa044e65-b886-4af9-aa8f-9748518376c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3758538285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3758538285 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.2154143142
Short name	T590
Test name
Test status
Simulation time	80013334985 ps
CPU time	2229.24 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:59:03 PM PST 24
Peak memory	392152 kb
Host	smart-b9eda277-6f57-46ba-9cdf-df829b5104ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2154143142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.2154143142 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.476422755
Short name	T712
Test name
Test status
Simulation time	61506027995 ps
CPU time	1603.49 seconds
Started	Jan 03 01:21:40 PM PST 24
Finished	Jan 03 01:48:32 PM PST 24
Peak memory	344300 kb
Host	smart-571e7fb1-6a75-461e-912c-339ccfccdc88
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=476422755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.476422755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.3824900852
Short name	T985
Test name
Test status
Simulation time	11860827313 ps
CPU time	1169.59 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:41:23 PM PST 24
Peak memory	302120 kb
Host	smart-33c15bd3-2e90-42fa-a401-a9d4a848f3c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3824900852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3824900852 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.2149116586
Short name	T1106
Test name
Test status
Simulation time	791244097954 ps
CPU time	5575.54 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 02:54:50 PM PST 24
Peak memory	654536 kb
Host	smart-d9a7636d-262f-4670-abd1-597d10b86b67
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2149116586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.2149116586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.1643271812
Short name	T685
Test name
Test status
Simulation time	455275202548 ps
CPU time	4964.75 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 02:44:38 PM PST 24
Peak memory	557228 kb
Host	smart-61ccf7db-0fd4-4b2e-9363-d1d9064fb8d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1643271812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1643271812 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.2424844663
Short name	T666
Test name
Test status
Simulation time	14257888 ps
CPU time	0.82 seconds
Started	Jan 03 01:22:47 PM PST 24
Finished	Jan 03 01:22:50 PM PST 24
Peak memory	219716 kb
Host	smart-e49e73ec-76e8-40a2-90f3-cd07fdb6a43a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424844663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2424844663 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.2535049531
Short name	T705
Test name
Test status
Simulation time	3882498148 ps
CPU time	243.57 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:25:49 PM PST 24
Peak memory	247416 kb
Host	smart-e50ce5c5-f617-438d-a9c1-47f14d79a113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535049531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2535049531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.930254109
Short name	T550
Test name
Test status
Simulation time	8647806074 ps
CPU time	421.94 seconds
Started	Jan 03 01:21:49 PM PST 24
Finished	Jan 03 01:28:58 PM PST 24
Peak memory	243276 kb
Host	smart-b500609d-ca17-4c1e-94cd-87cdd0adc426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930254109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.930254109 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.916228375
Short name	T454
Test name
Test status
Simulation time	9606624926 ps
CPU time	31.75 seconds
Started	Jan 03 01:22:30 PM PST 24
Finished	Jan 03 01:23:03 PM PST 24
Peak memory	243104 kb
Host	smart-df3eaad8-8857-42ab-b584-48aa5efb9af2
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=916228375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.916228375 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.3716657548
Short name	T296
Test name
Test status
Simulation time	413361849 ps
CPU time	29.05 seconds
Started	Jan 03 01:22:28 PM PST 24
Finished	Jan 03 01:22:59 PM PST 24
Peak memory	226948 kb
Host	smart-dd97c743-e96d-4f1a-8ed7-6403c4c00456
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3716657548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3716657548 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.2468936227
Short name	T1058
Test name
Test status
Simulation time	1982244863 ps
CPU time	78.94 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 01:25:25 PM PST 24
Peak memory	231080 kb
Host	smart-ef1dfc83-d946-413b-bf5d-4f79818ad7d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468936227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2468936227 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.1129147130
Short name	T304
Test name
Test status
Simulation time	1845640148 ps
CPU time	36.23 seconds
Started	Jan 03 01:22:28 PM PST 24
Finished	Jan 03 01:23:05 PM PST 24
Peak memory	243300 kb
Host	smart-fd66d8d5-c6ee-4b31-81fe-9b3ac674f939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129147130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1129147130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.1583430055
Short name	T265
Test name
Test status
Simulation time	189485676 ps
CPU time	1.03 seconds
Started	Jan 03 01:23:06 PM PST 24
Finished	Jan 03 01:23:21 PM PST 24
Peak memory	218560 kb
Host	smart-7015e2d8-6dd8-45ae-ae9d-b2cdbad9434b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583430055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1583430055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.3083262076
Short name	T314
Test name
Test status
Simulation time	73664379 ps
CPU time	1.39 seconds
Started	Jan 03 01:22:23 PM PST 24
Finished	Jan 03 01:22:26 PM PST 24
Peak memory	219872 kb
Host	smart-fa44ad8c-e00b-459b-8872-af0eae6af16b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083262076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3083262076 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.3367123892
Short name	T643
Test name
Test status
Simulation time	51613964196 ps
CPU time	2882.19 seconds
Started	Jan 03 01:21:51 PM PST 24
Finished	Jan 03 02:10:01 PM PST 24
Peak memory	487436 kb
Host	smart-4dfcdcf3-c01c-4951-b9a8-538ce325cf56
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367123892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.3367123892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.2861448579
Short name	T686
Test name
Test status
Simulation time	2842835149 ps
CPU time	201.89 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:25:15 PM PST 24
Peak memory	243384 kb
Host	smart-ad1d889c-a683-4f81-95e7-7f2ce8bf5fe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861448579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2861448579 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.2649656459
Short name	T344
Test name
Test status
Simulation time	8702054753 ps
CPU time	84.46 seconds
Started	Jan 03 01:21:49 PM PST 24
Finished	Jan 03 01:23:21 PM PST 24
Peak memory	220984 kb
Host	smart-cacc048a-8994-41ea-97e8-1942314adfd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649656459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2649656459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.1509938590
Short name	T600
Test name
Test status
Simulation time	36865069681 ps
CPU time	1580.76 seconds
Started	Jan 03 01:22:30 PM PST 24
Finished	Jan 03 01:48:52 PM PST 24
Peak memory	407128 kb
Host	smart-edbe22c0-ed44-4efd-a173-4b971225b9e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1509938590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1509938590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_stress_all_with_rand_reset.2635984440
Short name	T37
Test name
Test status
Simulation time	49598364994 ps
CPU time	1703.91 seconds
Started	Jan 03 01:23:04 PM PST 24
Finished	Jan 03 01:51:44 PM PST 24
Peak memory	349864 kb
Host	smart-6c9f3754-c270-45e9-b0dc-dfa22e5b7332
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2635984440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.2635984440 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.3056275130
Short name	T200
Test name
Test status
Simulation time	225470503 ps
CPU time	5.92 seconds
Started	Jan 03 01:21:45 PM PST 24
Finished	Jan 03 01:21:59 PM PST 24
Peak memory	218908 kb
Host	smart-35d4a161-9211-4fb8-a19b-35d6f72b1738
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056275130 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.3056275130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.278756079
Short name	T1074
Test name
Test status
Simulation time	191583404 ps
CPU time	5.6 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:21:52 PM PST 24
Peak memory	220152 kb
Host	smart-f47bbd31-7cf4-4776-95b6-831d09cbf663
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278756079 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.kmac_test_vectors_kmac_xof.278756079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.831970954
Short name	T822
Test name
Test status
Simulation time	1305175807944 ps
CPU time	2750.03 seconds
Started	Jan 03 01:21:49 PM PST 24
Finished	Jan 03 02:07:47 PM PST 24
Peak memory	398024 kb
Host	smart-58d20855-9a0f-48b6-ac7f-2f66e58d2804
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=831970954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.831970954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.2023404515
Short name	T657
Test name
Test status
Simulation time	469983902621 ps
CPU time	2139.12 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 01:57:32 PM PST 24
Peak memory	384932 kb
Host	smart-fa7d31a5-e2dd-4df0-9a8a-ee3e2b9da606
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2023404515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.2023404515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.2645631463
Short name	T955
Test name
Test status
Simulation time	97728408441 ps
CPU time	1723.37 seconds
Started	Jan 03 01:21:46 PM PST 24
Finished	Jan 03 01:50:37 PM PST 24
Peak memory	338456 kb
Host	smart-f30ab810-cb12-49f8-97a2-fa2c290f6ba4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2645631463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2645631463 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.3830587089
Short name	T903
Test name
Test status
Simulation time	11637507565 ps
CPU time	1140.97 seconds
Started	Jan 03 01:21:43 PM PST 24
Finished	Jan 03 01:40:53 PM PST 24
Peak memory	306260 kb
Host	smart-248d53d5-731c-423c-a538-83eb92e3eaea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3830587089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3830587089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.240160534
Short name	T995
Test name
Test status
Simulation time	714722608316 ps
CPU time	6106.99 seconds
Started	Jan 03 01:21:44 PM PST 24
Finished	Jan 03 03:03:41 PM PST 24
Peak memory	652088 kb
Host	smart-c6459a1f-b8aa-4b6f-ab85-42a17e463307
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=240160534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.240160534 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.3262535997
Short name	T438
Test name
Test status
Simulation time	52987614024 ps
CPU time	4200.07 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 02:31:48 PM PST 24
Peak memory	574040 kb
Host	smart-6bc44990-0b3c-4ddc-bae4-579523346544
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3262535997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3262535997 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.3144838804
Short name	T613
Test name
Test status
Simulation time	21517539 ps
CPU time	0.88 seconds
Started	Jan 03 01:23:35 PM PST 24
Finished	Jan 03 01:23:40 PM PST 24
Peak memory	218424 kb
Host	smart-bad7b0d1-ce55-4a38-85a5-244d26eb1df0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144838804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3144838804 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.3747583716
Short name	T672
Test name
Test status
Simulation time	12423432005 ps
CPU time	297.06 seconds
Started	Jan 03 01:23:35 PM PST 24
Finished	Jan 03 01:28:36 PM PST 24
Peak memory	248816 kb
Host	smart-71b7860f-740b-47c8-8c8a-0681777c7ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747583716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3747583716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.1121272322
Short name	T487
Test name
Test status
Simulation time	28428392852 ps
CPU time	512.96 seconds
Started	Jan 03 01:22:31 PM PST 24
Finished	Jan 03 01:31:05 PM PST 24
Peak memory	235476 kb
Host	smart-56723f46-5103-4764-8a6b-7607b9a3d1bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121272322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1121272322 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.3170378978
Short name	T4
Test name
Test status
Simulation time	28443611 ps
CPU time	0.88 seconds
Started	Jan 03 01:23:33 PM PST 24
Finished	Jan 03 01:23:38 PM PST 24
Peak memory	218432 kb
Host	smart-3f66c626-9caf-4105-83d6-f9e00f1261ab
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3170378978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3170378978 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.3585561045
Short name	T601
Test name
Test status
Simulation time	24475485 ps
CPU time	1.13 seconds
Started	Jan 03 01:22:52 PM PST 24
Finished	Jan 03 01:22:55 PM PST 24
Peak memory	218712 kb
Host	smart-04b1cfeb-5084-423f-b6b6-e251d5ffbfdc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3585561045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3585561045 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.2079942269
Short name	T708
Test name
Test status
Simulation time	1850849842 ps
CPU time	19.79 seconds
Started	Jan 03 01:22:49 PM PST 24
Finished	Jan 03 01:23:10 PM PST 24
Peak memory	226468 kb
Host	smart-5929bfb9-78e8-4898-9ea1-16e35136b6a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079942269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2079942269 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_error.339922292
Short name	T544
Test name
Test status
Simulation time	9626653430 ps
CPU time	370.53 seconds
Started	Jan 03 01:23:35 PM PST 24
Finished	Jan 03 01:29:49 PM PST 24
Peak memory	267840 kb
Host	smart-45484715-ec1f-4154-946b-74332626c04a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339922292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.339922292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_key_error.498388083
Short name	T976
Test name
Test status
Simulation time	828699468 ps
CPU time	3.38 seconds
Started	Jan 03 01:22:48 PM PST 24
Finished	Jan 03 01:22:53 PM PST 24
Peak memory	218744 kb
Host	smart-931f6ad9-ac57-4bf2-9574-829a438754fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498388083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.498388083 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.3418632804
Short name	T1124
Test name
Test status
Simulation time	64500092 ps
CPU time	1.42 seconds
Started	Jan 03 01:22:52 PM PST 24
Finished	Jan 03 01:22:55 PM PST 24
Peak memory	219764 kb
Host	smart-8559c0a7-93ae-4173-909a-47ad898b3f8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418632804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3418632804 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.3746815427
Short name	T584
Test name
Test status
Simulation time	107764104239 ps
CPU time	747.79 seconds
Started	Jan 03 01:22:42 PM PST 24
Finished	Jan 03 01:35:12 PM PST 24
Peak memory	277904 kb
Host	smart-0cca552f-4a1b-4f5c-9394-5c140adbac6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746815427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.3746815427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.3070439024
Short name	T1132
Test name
Test status
Simulation time	1195842126 ps
CPU time	17.44 seconds
Started	Jan 03 01:22:29 PM PST 24
Finished	Jan 03 01:22:48 PM PST 24
Peak memory	226912 kb
Host	smart-5c4d5f92-2765-4ee6-b161-3c8a19ccb157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070439024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3070439024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.445310225
Short name	T553
Test name
Test status
Simulation time	1074369458 ps
CPU time	26.6 seconds
Started	Jan 03 01:22:23 PM PST 24
Finished	Jan 03 01:22:51 PM PST 24
Peak memory	226820 kb
Host	smart-bce95619-3730-4edb-9d02-a52454981b32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445310225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.445310225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.1314954246
Short name	T565
Test name
Test status
Simulation time	41200412863 ps
CPU time	1049.27 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 01:41:06 PM PST 24
Peak memory	337008 kb
Host	smart-dc350068-75d8-486a-8b33-83444836c23c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1314954246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1314954246 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_stress_all_with_rand_reset.2964988307
Short name	T325
Test name
Test status
Simulation time	25139021774 ps
CPU time	937.87 seconds
Started	Jan 03 01:23:11 PM PST 24
Finished	Jan 03 01:39:03 PM PST 24
Peak memory	303688 kb
Host	smart-720b3cf2-ea4a-4509-8e87-1cea9ac96e34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2964988307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.2964988307 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.2544694084
Short name	T431
Test name
Test status
Simulation time	280663223 ps
CPU time	6.77 seconds
Started	Jan 03 01:22:45 PM PST 24
Finished	Jan 03 01:22:54 PM PST 24
Peak memory	220156 kb
Host	smart-8ed11887-e811-4372-a942-09d166ff8039
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544694084 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.2544694084 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2345588031
Short name	T189
Test name
Test status
Simulation time	98392844 ps
CPU time	5.67 seconds
Started	Jan 03 01:22:48 PM PST 24
Finished	Jan 03 01:22:55 PM PST 24
Peak memory	218912 kb
Host	smart-2cc742dc-12ce-4574-be3f-cfaca2ee1d8e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345588031 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2345588031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.3473734844
Short name	T603
Test name
Test status
Simulation time	85940408054 ps
CPU time	2062.68 seconds
Started	Jan 03 01:22:42 PM PST 24
Finished	Jan 03 01:57:06 PM PST 24
Peak memory	406136 kb
Host	smart-796a837b-31bc-462d-aac3-57150bd138c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3473734844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3473734844 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.3765767564
Short name	T713
Test name
Test status
Simulation time	21967081207 ps
CPU time	1921.79 seconds
Started	Jan 03 01:23:13 PM PST 24
Finished	Jan 03 01:55:29 PM PST 24
Peak memory	390548 kb
Host	smart-1fbdc2ec-1c48-4ddc-a8c0-8591ba5248b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3765767564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3765767564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.3398923736
Short name	T609
Test name
Test status
Simulation time	72642114472 ps
CPU time	1762.2 seconds
Started	Jan 03 01:22:42 PM PST 24
Finished	Jan 03 01:52:06 PM PST 24
Peak memory	336848 kb
Host	smart-42263b60-2f92-49f2-852d-541efe204b8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3398923736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3398923736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.1892137398
Short name	T698
Test name
Test status
Simulation time	189207269612 ps
CPU time	1288.45 seconds
Started	Jan 03 01:22:47 PM PST 24
Finished	Jan 03 01:44:17 PM PST 24
Peak memory	302672 kb
Host	smart-13e81f12-d8f4-4fc1-b733-f553c404cbce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1892137398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1892137398 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.4269923237
Short name	T291
Test name
Test status
Simulation time	260299517104 ps
CPU time	5049.6 seconds
Started	Jan 03 01:22:45 PM PST 24
Finished	Jan 03 02:46:57 PM PST 24
Peak memory	657312 kb
Host	smart-8eb5d9e5-6558-4bba-a04b-dcad6d636d6f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4269923237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.4269923237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.2956905199
Short name	T852
Test name
Test status
Simulation time	117937613345 ps
CPU time	4059.63 seconds
Started	Jan 03 01:23:06 PM PST 24
Finished	Jan 03 02:31:00 PM PST 24
Peak memory	568216 kb
Host	smart-d26cdefa-4ddb-4576-ba15-03d8abe269cb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2956905199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2956905199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.3299533039
Short name	T583
Test name
Test status
Simulation time	16044574 ps
CPU time	0.83 seconds
Started	Jan 03 01:24:07 PM PST 24
Finished	Jan 03 01:24:13 PM PST 24
Peak memory	218496 kb
Host	smart-376116b3-acd2-407d-978d-171ff89df5a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299533039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3299533039 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.4290854196
Short name	T637
Test name
Test status
Simulation time	7120554190 ps
CPU time	199.14 seconds
Started	Jan 03 01:23:46 PM PST 24
Finished	Jan 03 01:27:10 PM PST 24
Peak memory	243680 kb
Host	smart-47e9a7e6-cfa7-48c4-a043-e2818e3e9288
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290854196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.4290854196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.1993263475
Short name	T238
Test name
Test status
Simulation time	24179209216 ps
CPU time	521.94 seconds
Started	Jan 03 01:23:41 PM PST 24
Finished	Jan 03 01:32:25 PM PST 24
Peak memory	243208 kb
Host	smart-d62556e1-9675-4a83-9141-f821913715a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993263475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1993263475 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.1987808781
Short name	T82
Test name
Test status
Simulation time	63067677 ps
CPU time	1 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	218556 kb
Host	smart-b6b45b77-4e00-4fcd-b78b-d2aa44b82021
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1987808781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1987808781 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.312370931
Short name	T776
Test name
Test status
Simulation time	99391963 ps
CPU time	1.36 seconds
Started	Jan 03 01:24:13 PM PST 24
Finished	Jan 03 01:24:19 PM PST 24
Peak memory	218768 kb
Host	smart-e565f520-814e-4fd9-8c44-3af2961eace4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=312370931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.312370931 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.2393684054
Short name	T40
Test name
Test status
Simulation time	774537689 ps
CPU time	37.36 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:36 PM PST 24
Peak memory	228276 kb
Host	smart-a81d81eb-67ce-4537-a940-648f6f377c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393684054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2393684054 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.2336094688
Short name	T211
Test name
Test status
Simulation time	2022814226 ps
CPU time	153.26 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:26:32 PM PST 24
Peak memory	251504 kb
Host	smart-c43a6c39-73aa-4808-865b-9f3c2336b382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336094688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2336094688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.3970515105
Short name	T519
Test name
Test status
Simulation time	2713509813 ps
CPU time	4.9 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:24:13 PM PST 24
Peak memory	218796 kb
Host	smart-fddf7d13-2ff5-46c0-8e60-e94bbbfdba02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970515105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3970515105 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.3899832424
Short name	T912
Test name
Test status
Simulation time	26046583 ps
CPU time	1.31 seconds
Started	Jan 03 01:23:46 PM PST 24
Finished	Jan 03 01:23:52 PM PST 24
Peak memory	219896 kb
Host	smart-815d8e4c-308a-4283-9526-190e83814a93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899832424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3899832424 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.3592120347
Short name	T395
Test name
Test status
Simulation time	14032058802 ps
CPU time	787.96 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:36:49 PM PST 24
Peak memory	294364 kb
Host	smart-66c4f27e-7298-4075-ba1b-84022be214b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592120347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.3592120347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.3015590857
Short name	T948
Test name
Test status
Simulation time	1678899279 ps
CPU time	33.45 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	227108 kb
Host	smart-3383e031-4db3-4234-be88-391c558dea6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015590857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3015590857 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.2362945937
Short name	T1029
Test name
Test status
Simulation time	3266216859 ps
CPU time	20.25 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:24:01 PM PST 24
Peak memory	226972 kb
Host	smart-aae08aa0-bfc8-473f-abef-fa5265285a86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362945937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2362945937 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.1159397920
Short name	T16
Test name
Test status
Simulation time	25340217617 ps
CPU time	504.28 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:32:39 PM PST 24
Peak memory	266640 kb
Host	smart-ed534f07-5d06-48e1-b7e0-8b0254394469
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1159397920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1159397920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.2886402888
Short name	T1009
Test name
Test status
Simulation time	128298864120 ps
CPU time	313.24 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:29:23 PM PST 24
Peak memory	257700 kb
Host	smart-3c0ae7f0-b80e-4bb5-9b6e-c91035f70030
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2886402888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.2886402888 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.3178226437
Short name	T1044
Test name
Test status
Simulation time	164499158 ps
CPU time	5.98 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:24:05 PM PST 24
Peak memory	218776 kb
Host	smart-e50596f2-653a-4ba0-acd2-0f401fca1393
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178226437 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.3178226437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.448298632
Short name	T851
Test name
Test status
Simulation time	180589603 ps
CPU time	5.98 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:24:14 PM PST 24
Peak memory	218800 kb
Host	smart-5622154b-f562-4c03-9159-126cf6c8832a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448298632 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.kmac_test_vectors_kmac_xof.448298632 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.1472093774
Short name	T470
Test name
Test status
Simulation time	238305799786 ps
CPU time	2155.56 seconds
Started	Jan 03 01:23:16 PM PST 24
Finished	Jan 03 01:59:24 PM PST 24
Peak memory	392952 kb
Host	smart-ee0accdb-9bca-4ccd-b40b-7fc6693a5dc0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1472093774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1472093774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.1559649392
Short name	T338
Test name
Test status
Simulation time	21197695012 ps
CPU time	1797.01 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:53:46 PM PST 24
Peak memory	392360 kb
Host	smart-b8e3e7ab-37e2-4337-bef0-27b12539644e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1559649392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1559649392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.392173633
Short name	T330
Test name
Test status
Simulation time	55871091698 ps
CPU time	1666.42 seconds
Started	Jan 03 01:23:18 PM PST 24
Finished	Jan 03 01:51:18 PM PST 24
Peak memory	345592 kb
Host	smart-b12f6c47-6cb1-4800-8d20-7e33116f72d0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=392173633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.392173633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.4244742257
Short name	T252
Test name
Test status
Simulation time	69497657161 ps
CPU time	1279.02 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:45:08 PM PST 24
Peak memory	301984 kb
Host	smart-1b73cd34-de84-418f-976b-8ef6e278542a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4244742257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4244742257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.4249305252
Short name	T901
Test name
Test status
Simulation time	180926078801 ps
CPU time	5180.59 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 02:50:11 PM PST 24
Peak memory	657560 kb
Host	smart-66c5d8b6-6823-40e6-92b9-44f45daf3275
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4249305252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.4249305252 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.1213815023
Short name	T437
Test name
Test status
Simulation time	105702215 ps
CPU time	0.86 seconds
Started	Jan 03 01:19:22 PM PST 24
Finished	Jan 03 01:19:26 PM PST 24
Peak memory	218604 kb
Host	smart-be876c50-50aa-4353-877b-00960fad9321
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213815023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1213815023 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.316972632
Short name	T459
Test name
Test status
Simulation time	1259080622 ps
CPU time	71.58 seconds
Started	Jan 03 01:19:49 PM PST 24
Finished	Jan 03 01:21:06 PM PST 24
Peak memory	232808 kb
Host	smart-da10e178-7ed1-4454-88b1-c8e7ff7b5147
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316972632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.316972632 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.2332349940
Short name	T580
Test name
Test status
Simulation time	19083268567 ps
CPU time	144.64 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 01:22:18 PM PST 24
Peak memory	238248 kb
Host	smart-92552892-2a3c-40cb-8b66-b1cd8d66ba2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332349940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2332349940 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.3298462048
Short name	T582
Test name
Test status
Simulation time	42805590716 ps
CPU time	976.48 seconds
Started	Jan 03 01:19:36 PM PST 24
Finished	Jan 03 01:35:56 PM PST 24
Peak memory	240152 kb
Host	smart-5adf0fd5-c239-44fa-b80b-bd52d3546f5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298462048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3298462048 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.3800992835
Short name	T641
Test name
Test status
Simulation time	32761669 ps
CPU time	1.11 seconds
Started	Jan 03 01:19:17 PM PST 24
Finished	Jan 03 01:19:22 PM PST 24
Peak memory	218640 kb
Host	smart-c32d901b-e75a-47ea-bb4b-7ef84e336da4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3800992835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3800992835 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.180325216
Short name	T25
Test name
Test status
Simulation time	26217106 ps
CPU time	1.05 seconds
Started	Jan 03 01:19:06 PM PST 24
Finished	Jan 03 01:19:16 PM PST 24
Peak memory	218584 kb
Host	smart-4043ed80-a6eb-4eb6-acac-d8663582bbda
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=180325216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.180325216 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3599996065
Short name	T1045
Test name
Test status
Simulation time	10661808351 ps
CPU time	35.82 seconds
Started	Jan 03 01:19:23 PM PST 24
Finished	Jan 03 01:20:03 PM PST 24
Peak memory	226852 kb
Host	smart-a01e8b94-70f5-4f29-a635-b10d12e316fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599996065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3599996065 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.3568036083
Short name	T348
Test name
Test status
Simulation time	13214387581 ps
CPU time	245.24 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:23:21 PM PST 24
Peak memory	245432 kb
Host	smart-0f8ac4bc-f2ae-4c91-8da6-40a1a82d7fb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568036083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3568036083 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.4280091560
Short name	T962
Test name
Test status
Simulation time	38306141027 ps
CPU time	458.22 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:26:54 PM PST 24
Peak memory	259792 kb
Host	smart-929b50ec-9216-4b8f-9ac1-0e736ec1ea43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280091560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.4280091560 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.806229525
Short name	T1121
Test name
Test status
Simulation time	2119598184 ps
CPU time	3.53 seconds
Started	Jan 03 01:19:23 PM PST 24
Finished	Jan 03 01:19:31 PM PST 24
Peak memory	218612 kb
Host	smart-0a4edb80-b204-4089-828f-148dbc3916b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806229525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.806229525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.2574869834
Short name	T573
Test name
Test status
Simulation time	98105749 ps
CPU time	1.55 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:19:23 PM PST 24
Peak memory	219912 kb
Host	smart-ed9e45b2-eb26-4364-b863-41f2ba3b5b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574869834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2574869834 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.1950981896
Short name	T299
Test name
Test status
Simulation time	31886082474 ps
CPU time	163.88 seconds
Started	Jan 03 01:19:40 PM PST 24
Finished	Jan 03 01:22:28 PM PST 24
Peak memory	242640 kb
Host	smart-cd3b85a3-eacc-4972-a0b8-254a9f63129c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950981896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.1950981896 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.1964884281
Short name	T1078
Test name
Test status
Simulation time	9505511136 ps
CPU time	223.73 seconds
Started	Jan 03 01:19:20 PM PST 24
Finished	Jan 03 01:23:08 PM PST 24
Peak memory	245636 kb
Host	smart-2c9f4ed9-818b-48e0-8d1a-2a405dc215cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964884281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1964884281 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.3802643213
Short name	T8
Test name
Test status
Simulation time	29054868204 ps
CPU time	117.52 seconds
Started	Jan 03 01:19:19 PM PST 24
Finished	Jan 03 01:21:20 PM PST 24
Peak memory	293892 kb
Host	smart-3ed90851-bc37-4592-b405-29e6b9662d21
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802643213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3802643213 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.961497534
Short name	T960
Test name
Test status
Simulation time	17895502001 ps
CPU time	143.59 seconds
Started	Jan 03 01:19:46 PM PST 24
Finished	Jan 03 01:22:16 PM PST 24
Peak memory	242824 kb
Host	smart-86f70330-a6b4-4dc6-be2f-3ac44b4ca99a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961497534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.961497534 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.976263969
Short name	T915
Test name
Test status
Simulation time	1935358583 ps
CPU time	25.56 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:19:56 PM PST 24
Peak memory	223436 kb
Host	smart-96c63ea3-4e11-4929-a706-6ebf031bac17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976263969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.976263969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.30049190
Short name	T787
Test name
Test status
Simulation time	622177791288 ps
CPU time	1760.76 seconds
Started	Jan 03 01:19:07 PM PST 24
Finished	Jan 03 01:48:36 PM PST 24
Peak memory	356356 kb
Host	smart-8c44006f-83c0-4f6c-aea1-5ea43dabc7cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=30049190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.30049190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_stress_all_with_rand_reset.2880967226
Short name	T612
Test name
Test status
Simulation time	212057432950 ps
CPU time	1389.79 seconds
Started	Jan 03 01:19:23 PM PST 24
Finished	Jan 03 01:42:37 PM PST 24
Peak memory	319656 kb
Host	smart-f8e3bd82-ac71-4a54-9767-59579a98eb59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2880967226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.2880967226 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.94249449
Short name	T397
Test name
Test status
Simulation time	91911657 ps
CPU time	5.19 seconds
Started	Jan 03 01:19:37 PM PST 24
Finished	Jan 03 01:19:45 PM PST 24
Peak memory	218808 kb
Host	smart-64bbce6e-df64-4663-89e1-32fbf4475444
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94249449 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.kmac_test_vectors_kmac.94249449 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2040235875
Short name	T647
Test name
Test status
Simulation time	460215784 ps
CPU time	6.04 seconds
Started	Jan 03 01:19:52 PM PST 24
Finished	Jan 03 01:20:05 PM PST 24
Peak memory	220212 kb
Host	smart-a3bb01c6-6cbc-44a3-8e19-4ff893d0646f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040235875 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2040235875 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.216962987
Short name	T259
Test name
Test status
Simulation time	288584629200 ps
CPU time	2237.54 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:57:09 PM PST 24
Peak memory	403384 kb
Host	smart-38f7eaa6-f36a-44bc-9118-53f4d40362b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=216962987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.216962987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.1288967771
Short name	T593
Test name
Test status
Simulation time	426716672357 ps
CPU time	2263.53 seconds
Started	Jan 03 01:19:32 PM PST 24
Finished	Jan 03 01:57:20 PM PST 24
Peak memory	393504 kb
Host	smart-220f7d9c-08d4-4d29-9caf-07bab115443a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1288967771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1288967771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.1562234476
Short name	T213
Test name
Test status
Simulation time	35504693643 ps
CPU time	1468 seconds
Started	Jan 03 01:19:38 PM PST 24
Finished	Jan 03 01:44:10 PM PST 24
Peak memory	340312 kb
Host	smart-6966fb2c-e1a2-444c-af78-66fb61be6d10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1562234476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1562234476 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.2147625004
Short name	T392
Test name
Test status
Simulation time	43784584927 ps
CPU time	1095.5 seconds
Started	Jan 03 01:19:46 PM PST 24
Finished	Jan 03 01:38:08 PM PST 24
Peak memory	301648 kb
Host	smart-29d732f9-74e4-4ad2-8a78-1b6c1fb9c0ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2147625004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2147625004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.2579429075
Short name	T804
Test name
Test status
Simulation time	180185132830 ps
CPU time	5564.49 seconds
Started	Jan 03 01:19:35 PM PST 24
Finished	Jan 03 02:52:24 PM PST 24
Peak memory	657200 kb
Host	smart-56e6401d-4711-417b-bb92-3313926dd9cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2579429075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2579429075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.63357750
Short name	T1110
Test name
Test status
Simulation time	113830666083 ps
CPU time	4349.77 seconds
Started	Jan 03 01:20:05 PM PST 24
Finished	Jan 03 02:32:40 PM PST 24
Peak memory	578680 kb
Host	smart-c3b9893b-8f3e-42de-9146-7a07096e63cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=63357750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.63357750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.2100001061
Short name	T368
Test name
Test status
Simulation time	33937118 ps
CPU time	0.82 seconds
Started	Jan 03 01:23:34 PM PST 24
Finished	Jan 03 01:23:39 PM PST 24
Peak memory	219756 kb
Host	smart-1c66158d-5432-4a39-ace9-6db74af3c582
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100001061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2100001061 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.1891571612
Short name	T342
Test name
Test status
Simulation time	71943577559 ps
CPU time	399.65 seconds
Started	Jan 03 01:23:35 PM PST 24
Finished	Jan 03 01:30:19 PM PST 24
Peak memory	252668 kb
Host	smart-4989b0bf-fc82-45af-a8d1-68670a6eaada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891571612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1891571612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.2863047466
Short name	T1083
Test name
Test status
Simulation time	74259972074 ps
CPU time	1386.08 seconds
Started	Jan 03 01:23:13 PM PST 24
Finished	Jan 03 01:46:33 PM PST 24
Peak memory	243280 kb
Host	smart-25ffbd39-0d8d-4736-8280-f756e8d5168c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863047466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2863047466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.444209307
Short name	T764
Test name
Test status
Simulation time	56973193330 ps
CPU time	370.88 seconds
Started	Jan 03 01:22:46 PM PST 24
Finished	Jan 03 01:28:59 PM PST 24
Peak memory	252188 kb
Host	smart-02e172d1-ffaa-4996-bf52-fe739ae9fce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444209307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.444209307 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_error.1884529225
Short name	T400
Test name
Test status
Simulation time	1911885289 ps
CPU time	15.94 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 01:23:43 PM PST 24
Peak memory	238532 kb
Host	smart-86087f81-d035-4745-ada9-7605e6fbfc4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884529225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1884529225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/20.kmac_key_error.3651090835
Short name	T586
Test name
Test status
Simulation time	3785371706 ps
CPU time	5.89 seconds
Started	Jan 03 01:23:31 PM PST 24
Finished	Jan 03 01:23:42 PM PST 24
Peak memory	218740 kb
Host	smart-f2cf3b36-f670-4ec0-a5a3-a3de05f6caa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651090835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3651090835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.2870702605
Short name	T1025
Test name
Test status
Simulation time	40523136 ps
CPU time	1.37 seconds
Started	Jan 03 01:23:34 PM PST 24
Finished	Jan 03 01:23:39 PM PST 24
Peak memory	219884 kb
Host	smart-e1836fca-d808-424d-a3a6-d589bfce4755
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870702605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2870702605 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.1570032849
Short name	T864
Test name
Test status
Simulation time	294646279211 ps
CPU time	1667.83 seconds
Started	Jan 03 01:22:41 PM PST 24
Finished	Jan 03 01:50:30 PM PST 24
Peak memory	347080 kb
Host	smart-56902cc8-7390-4759-bc88-e76b38363760
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570032849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.1570032849 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.4270833428
Short name	T235
Test name
Test status
Simulation time	3029810992 ps
CPU time	229.57 seconds
Started	Jan 03 01:22:43 PM PST 24
Finished	Jan 03 01:26:36 PM PST 24
Peak memory	245040 kb
Host	smart-5f8dd728-16c9-4ca2-9885-080a7766a1bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270833428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.4270833428 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.1668623396
Short name	T112
Test name
Test status
Simulation time	1924990527 ps
CPU time	30.12 seconds
Started	Jan 03 01:24:07 PM PST 24
Finished	Jan 03 01:24:43 PM PST 24
Peak memory	226868 kb
Host	smart-b8a03c75-9c03-4786-b1c3-be4bf65a1725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668623396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1668623396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.1472790888
Short name	T56
Test name
Test status
Simulation time	540645360939 ps
CPU time	3734.61 seconds
Started	Jan 03 01:22:49 PM PST 24
Finished	Jan 03 02:25:06 PM PST 24
Peak memory	489108 kb
Host	smart-6f4aea65-b314-4784-af04-d7f191807935
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1472790888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1472790888 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_stress_all_with_rand_reset.2117278554
Short name	T719
Test name
Test status
Simulation time	25518958217 ps
CPU time	713.77 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 01:35:31 PM PST 24
Peak memory	285612 kb
Host	smart-6e1b7ac5-27f1-444c-9d27-8bb54de9e35a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2117278554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all_with_rand_reset.2117278554 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.3958984609
Short name	T627
Test name
Test status
Simulation time	420534943 ps
CPU time	5.77 seconds
Started	Jan 03 01:22:43 PM PST 24
Finished	Jan 03 01:22:51 PM PST 24
Peak memory	218860 kb
Host	smart-9629691c-7b3f-410a-aed7-5d36398aa092
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958984609 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.kmac_test_vectors_kmac.3958984609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.2416173485
Short name	T300
Test name
Test status
Simulation time	124730041438 ps
CPU time	2063.41 seconds
Started	Jan 03 01:22:45 PM PST 24
Finished	Jan 03 01:57:11 PM PST 24
Peak memory	390628 kb
Host	smart-b3566677-5cf6-4fda-b5bf-a11bffe93636
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2416173485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2416173485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.1497724154
Short name	T942
Test name
Test status
Simulation time	95327681294 ps
CPU time	2233.72 seconds
Started	Jan 03 01:22:45 PM PST 24
Finished	Jan 03 02:00:01 PM PST 24
Peak memory	390104 kb
Host	smart-d4c238db-ce06-434c-8b43-cfc0357d2278
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1497724154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1497724154 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.2568515681
Short name	T376
Test name
Test status
Simulation time	214406152657 ps
CPU time	1902.88 seconds
Started	Jan 03 01:22:48 PM PST 24
Finished	Jan 03 01:54:33 PM PST 24
Peak memory	343948 kb
Host	smart-afa445b8-c347-4fb3-a9f2-daffd2a1a5fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2568515681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2568515681 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.3631083696
Short name	T1062
Test name
Test status
Simulation time	88485957397 ps
CPU time	1395.42 seconds
Started	Jan 03 01:23:10 PM PST 24
Finished	Jan 03 01:46:38 PM PST 24
Peak memory	303216 kb
Host	smart-9c59a6ee-4760-4811-b591-f7e704b28faa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3631083696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3631083696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.3210528993
Short name	T782
Test name
Test status
Simulation time	1068923384882 ps
CPU time	6015.52 seconds
Started	Jan 03 01:22:44 PM PST 24
Finished	Jan 03 03:03:03 PM PST 24
Peak memory	646248 kb
Host	smart-1d29858c-429e-413e-9c53-fad913127383
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3210528993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3210528993 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.3937766712
Short name	T831
Test name
Test status
Simulation time	157953485254 ps
CPU time	4516.66 seconds
Started	Jan 03 01:22:49 PM PST 24
Finished	Jan 03 02:38:08 PM PST 24
Peak memory	567432 kb
Host	smart-9bfd7d7b-e9cc-46bd-aa53-713bc07055f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3937766712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3937766712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.2620859664
Short name	T964
Test name
Test status
Simulation time	38368553 ps
CPU time	0.9 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:10 PM PST 24
Peak memory	219724 kb
Host	smart-0ce167e8-4e81-43ed-9d1a-9fa3911e8b99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620859664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2620859664 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.3786303431
Short name	T514
Test name
Test status
Simulation time	1474525295 ps
CPU time	34.4 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:24:44 PM PST 24
Peak memory	227904 kb
Host	smart-7fd201c7-2ece-4c7c-a967-e1b56a535545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786303431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3786303431 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.3912049193
Short name	T535
Test name
Test status
Simulation time	8572708511 ps
CPU time	417.3 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:30:45 PM PST 24
Peak memory	232720 kb
Host	smart-40008276-066b-4e86-a2bc-195a9eceaefe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912049193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3912049193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.795359802
Short name	T298
Test name
Test status
Simulation time	11536264395 ps
CPU time	54.93 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:53 PM PST 24
Peak memory	230012 kb
Host	smart-08103280-c6f9-4aac-b63a-93b9dd7e4d3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795359802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.795359802 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_error.2943289492
Short name	T33
Test name
Test status
Simulation time	10924299568 ps
CPU time	395.63 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:30:44 PM PST 24
Peak memory	268076 kb
Host	smart-7c1a3c89-9651-4bce-9a5b-d14218cc4ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943289492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2943289492 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.3771460910
Short name	T1111
Test name
Test status
Simulation time	720060898 ps
CPU time	4.72 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	218736 kb
Host	smart-a2dc0d40-f5e3-468d-ac47-f3170facf867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771460910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3771460910 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.4074044606
Short name	T1094
Test name
Test status
Simulation time	95441900 ps
CPU time	1.35 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:23:55 PM PST 24
Peak memory	219912 kb
Host	smart-e92adb92-2242-475c-9395-3faf47ec8e64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074044606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.4074044606 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.3544051776
Short name	T936
Test name
Test status
Simulation time	53940333566 ps
CPU time	2905.75 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 02:12:15 PM PST 24
Peak memory	472976 kb
Host	smart-953c3bf8-63de-49a6-99a2-41a85a593923
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544051776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.3544051776 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.1154315318
Short name	T494
Test name
Test status
Simulation time	12337499079 ps
CPU time	403.73 seconds
Started	Jan 03 01:22:49 PM PST 24
Finished	Jan 03 01:29:35 PM PST 24
Peak memory	252912 kb
Host	smart-b677bfb5-3090-4744-9063-901baa6103fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154315318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1154315318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.2452266763
Short name	T442
Test name
Test status
Simulation time	1139558448 ps
CPU time	38.83 seconds
Started	Jan 03 01:23:36 PM PST 24
Finished	Jan 03 01:24:18 PM PST 24
Peak memory	226920 kb
Host	smart-0491610c-2e4f-4827-b00a-e4d3faa38b1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452266763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2452266763 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.3182275987
Short name	T843
Test name
Test status
Simulation time	109854368480 ps
CPU time	1499.1 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 01:48:57 PM PST 24
Peak memory	388532 kb
Host	smart-c3b6b407-2a85-4e49-a7e5-233aa86b7231
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3182275987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3182275987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.3442927438
Short name	T324
Test name
Test status
Simulation time	343741690 ps
CPU time	6.15 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	218928 kb
Host	smart-afee7390-b0fb-4faa-a60c-af92b90328f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442927438 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.3442927438 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.605524794
Short name	T563
Test name
Test status
Simulation time	253628582 ps
CPU time	6.66 seconds
Started	Jan 03 01:23:45 PM PST 24
Finished	Jan 03 01:23:57 PM PST 24
Peak memory	220316 kb
Host	smart-a9e5e730-821f-4708-80ae-0ffe3330176a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605524794 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 21.kmac_test_vectors_kmac_xof.605524794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.2843857543
Short name	T674
Test name
Test status
Simulation time	566436882234 ps
CPU time	2494.91 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 02:05:02 PM PST 24
Peak memory	393376 kb
Host	smart-a7adce93-b6f6-4cb5-8b68-2d30c2647aa6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2843857543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2843857543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.1120580556
Short name	T202
Test name
Test status
Simulation time	290231634896 ps
CPU time	2157.85 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:59:46 PM PST 24
Peak memory	400396 kb
Host	smart-f1663241-89d2-4eb9-aaf7-a37a32fbd554
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1120580556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.1120580556 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.4069211455
Short name	T345
Test name
Test status
Simulation time	48069181574 ps
CPU time	1718.97 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:52:32 PM PST 24
Peak memory	340172 kb
Host	smart-b9ff4959-4490-4684-b799-859171609089
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4069211455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.4069211455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.3379048288
Short name	T837
Test name
Test status
Simulation time	50506267125 ps
CPU time	1220.38 seconds
Started	Jan 03 01:23:41 PM PST 24
Finished	Jan 03 01:44:07 PM PST 24
Peak memory	301832 kb
Host	smart-d4279cd0-1475-4f67-9a54-471a88559b99
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3379048288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3379048288 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.1871909503
Short name	T374
Test name
Test status
Simulation time	242930933617 ps
CPU time	4854.33 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 02:44:46 PM PST 24
Peak memory	669676 kb
Host	smart-19b1ce3a-a6e8-4db8-8956-6137c14433b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1871909503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.1871909503 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.2314779057
Short name	T237
Test name
Test status
Simulation time	600835412787 ps
CPU time	4844.22 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 02:44:37 PM PST 24
Peak memory	575836 kb
Host	smart-51e84e22-17d1-4ede-874e-554aca6edd26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2314779057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2314779057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.927863789
Short name	T576
Test name
Test status
Simulation time	17960874 ps
CPU time	0.86 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:23:42 PM PST 24
Peak memory	218492 kb
Host	smart-5a4fb6b1-2501-4fdb-a1f4-d5cb47189d1b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927863789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.927863789 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.2284419017
Short name	T1014
Test name
Test status
Simulation time	24122028904 ps
CPU time	193.53 seconds
Started	Jan 03 01:22:45 PM PST 24
Finished	Jan 03 01:26:01 PM PST 24
Peak memory	243832 kb
Host	smart-25b88f69-8b29-4ac2-9e3c-8b2762dfc4ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284419017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2284419017 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.1560454861
Short name	T447
Test name
Test status
Simulation time	13017029379 ps
CPU time	447.04 seconds
Started	Jan 03 01:24:10 PM PST 24
Finished	Jan 03 01:31:43 PM PST 24
Peak memory	233760 kb
Host	smart-fcf676b5-e4e5-41e1-9ea5-1cbbbc242777
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560454861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1560454861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.3359512885
Short name	T116
Test name
Test status
Simulation time	2150306942 ps
CPU time	49.6 seconds
Started	Jan 03 01:22:43 PM PST 24
Finished	Jan 03 01:23:34 PM PST 24
Peak memory	229796 kb
Host	smart-0e3f6799-4bc9-4d15-8f1a-57f0777ae330
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359512885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3359512885 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.1289862259
Short name	T55
Test name
Test status
Simulation time	20595019589 ps
CPU time	343.16 seconds
Started	Jan 03 01:23:08 PM PST 24
Finished	Jan 03 01:29:05 PM PST 24
Peak memory	267872 kb
Host	smart-2b7f1e99-b7b7-4566-962a-7a7c32e32afd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289862259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1289862259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.1382469549
Short name	T557
Test name
Test status
Simulation time	1321265865 ps
CPU time	4.3 seconds
Started	Jan 03 01:22:47 PM PST 24
Finished	Jan 03 01:22:53 PM PST 24
Peak memory	218584 kb
Host	smart-5dce9913-0444-40f9-a78e-4b3be2e1bf7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382469549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1382469549 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.3245680536
Short name	T724
Test name
Test status
Simulation time	168750692 ps
CPU time	1.6 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 01:23:29 PM PST 24
Peak memory	219820 kb
Host	smart-03d719ed-7b7d-48cf-b7f0-e48ac4e84aa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245680536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3245680536 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.2517895080
Short name	T700
Test name
Test status
Simulation time	70500978060 ps
CPU time	774.95 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:36:57 PM PST 24
Peak memory	287100 kb
Host	smart-b6af9558-8bd7-4239-9e1b-2d71a98fe264
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517895080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.2517895080 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.4092544249
Short name	T783
Test name
Test status
Simulation time	66505164175 ps
CPU time	144.28 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:26:26 PM PST 24
Peak memory	243184 kb
Host	smart-9ff937a2-8ff1-41e6-a5e1-44f34e418783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092544249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.4092544249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.2828590508
Short name	T321
Test name
Test status
Simulation time	4659796807 ps
CPU time	33.55 seconds
Started	Jan 03 01:24:07 PM PST 24
Finished	Jan 03 01:24:46 PM PST 24
Peak memory	227004 kb
Host	smart-c4582f78-0fa6-4e4c-a6ff-a4eac0c7dfc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828590508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2828590508 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.156387143
Short name	T621
Test name
Test status
Simulation time	34442711491 ps
CPU time	399.54 seconds
Started	Jan 03 01:22:42 PM PST 24
Finished	Jan 03 01:29:23 PM PST 24
Peak memory	285524 kb
Host	smart-51c6a765-16bc-49b8-8a2c-0f989b01a095
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=156387143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.156387143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_stress_all_with_rand_reset.2112014175
Short name	T150
Test name
Test status
Simulation time	205795195981 ps
CPU time	1344.69 seconds
Started	Jan 03 01:23:12 PM PST 24
Finished	Jan 03 01:45:52 PM PST 24
Peak memory	317460 kb
Host	smart-89b55e0a-13cf-4307-b4e8-6aed21882db2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2112014175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all_with_rand_reset.2112014175 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.1908393828
Short name	T628
Test name
Test status
Simulation time	902686455 ps
CPU time	8.98 seconds
Started	Jan 03 01:23:05 PM PST 24
Finished	Jan 03 01:23:29 PM PST 24
Peak memory	220396 kb
Host	smart-3b1b5f16-d537-49d7-99f8-d80ad8a5b58c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908393828 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.1908393828 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.10584041
Short name	T532
Test name
Test status
Simulation time	108923973 ps
CPU time	5.93 seconds
Started	Jan 03 01:24:20 PM PST 24
Finished	Jan 03 01:24:28 PM PST 24
Peak memory	220328 kb
Host	smart-05f421c7-c684-443e-8b43-c3829f0bafe6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10584041 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.kmac_test_vectors_kmac_xof.10584041 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.2530817936
Short name	T208
Test name
Test status
Simulation time	69183778106 ps
CPU time	2238.21 seconds
Started	Jan 03 01:24:43 PM PST 24
Finished	Jan 03 02:02:06 PM PST 24
Peak memory	406688 kb
Host	smart-4319eb21-8051-49d7-92c6-3b6b311c1f8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2530817936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2530817936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.2100175729
Short name	T1118
Test name
Test status
Simulation time	19950144893 ps
CPU time	1825.9 seconds
Started	Jan 03 01:24:12 PM PST 24
Finished	Jan 03 01:54:43 PM PST 24
Peak memory	388012 kb
Host	smart-0a8f4f95-ee5d-4a14-b0c2-598928d7af49
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2100175729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2100175729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.913621390
Short name	T888
Test name
Test status
Simulation time	47168306039 ps
CPU time	1707.97 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:52:35 PM PST 24
Peak memory	339356 kb
Host	smart-5184c05a-dfe2-46e1-a2bb-0e8d0c4759be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=913621390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.913621390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.1969182376
Short name	T1104
Test name
Test status
Simulation time	138579253514 ps
CPU time	1259.75 seconds
Started	Jan 03 01:24:25 PM PST 24
Finished	Jan 03 01:45:27 PM PST 24
Peak memory	301956 kb
Host	smart-d307ccf0-7309-444f-b6d0-2c17c0e21ddc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1969182376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1969182376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.322757230
Short name	T826
Test name
Test status
Simulation time	258722617289 ps
CPU time	6164.86 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 03:06:47 PM PST 24
Peak memory	658116 kb
Host	smart-57f70977-ba01-4f28-a47a-f517ab1446b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=322757230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.322757230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.3060683257
Short name	T465
Test name
Test status
Simulation time	359938009188 ps
CPU time	5334.86 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 02:53:09 PM PST 24
Peak memory	585364 kb
Host	smart-c721bd55-9ea8-43a7-b327-9f1debf1cabf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3060683257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3060683257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.23861341
Short name	T598
Test name
Test status
Simulation time	15103225 ps
CPU time	0.84 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:10 PM PST 24
Peak memory	218660 kb
Host	smart-6bc6ea31-88fe-421f-b9c1-d3a8419b43a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.23861341 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.806100071
Short name	T649
Test name
Test status
Simulation time	5634780168 ps
CPU time	153 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 01:26:23 PM PST 24
Peak memory	239604 kb
Host	smart-282bd6e4-83b1-430a-9183-28656e26ef9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806100071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.806100071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.620516193
Short name	T687
Test name
Test status
Simulation time	14009261720 ps
CPU time	115.26 seconds
Started	Jan 03 01:23:41 PM PST 24
Finished	Jan 03 01:25:38 PM PST 24
Peak memory	227120 kb
Host	smart-08dee52b-e1d1-409b-b0c1-363afb539ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620516193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.620516193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.3113686124
Short name	T295
Test name
Test status
Simulation time	251794681 ps
CPU time	6.72 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	221700 kb
Host	smart-958931fd-7708-4e64-823c-4e0f67c94c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113686124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3113686124 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.850557763
Short name	T902
Test name
Test status
Simulation time	21087899983 ps
CPU time	125.86 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:25:53 PM PST 24
Peak memory	251504 kb
Host	smart-ce4448ef-6cd6-4e46-852e-8e62007d2df3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850557763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.850557763 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.1558744089
Short name	T574
Test name
Test status
Simulation time	135800496 ps
CPU time	1.42 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:24:09 PM PST 24
Peak memory	220236 kb
Host	smart-58de9a7e-50af-4d80-9825-de9808a795e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558744089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1558744089 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2613184488
Short name	T766
Test name
Test status
Simulation time	55119076432 ps
CPU time	2770.54 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 02:09:57 PM PST 24
Peak memory	452736 kb
Host	smart-cde46531-4b04-41e8-a894-32f2d2f2b6ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613184488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2613184488 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.3760606687
Short name	T663
Test name
Test status
Simulation time	26236026467 ps
CPU time	325.06 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:28:52 PM PST 24
Peak memory	249380 kb
Host	smart-5a5956c2-e6dd-4122-b654-8c6c107b4857
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760606687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3760606687 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.2911987354
Short name	T229
Test name
Test status
Simulation time	121199216 ps
CPU time	3.15 seconds
Started	Jan 03 01:23:38 PM PST 24
Finished	Jan 03 01:23:44 PM PST 24
Peak memory	226612 kb
Host	smart-ff5e3767-df0c-4b71-bb5a-0c1bbb8f6bbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911987354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2911987354 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.1988380373
Short name	T507
Test name
Test status
Simulation time	11184957076 ps
CPU time	792.68 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:37:12 PM PST 24
Peak memory	321452 kb
Host	smart-72363060-e37c-45e4-b426-db8b687a8d70
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1988380373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1988380373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_stress_all_with_rand_reset.1437280169
Short name	T682
Test name
Test status
Simulation time	68700725765 ps
CPU time	1862.13 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:55:01 PM PST 24
Peak memory	325420 kb
Host	smart-9ef6bd60-a497-48eb-b112-8082fd7f4a3e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1437280169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.1437280169 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.168766787
Short name	T199
Test name
Test status
Simulation time	221226209 ps
CPU time	6.33 seconds
Started	Jan 03 01:23:13 PM PST 24
Finished	Jan 03 01:23:33 PM PST 24
Peak memory	220304 kb
Host	smart-9b86a13f-4655-4e50-b25a-0f24fc5f0447
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168766787 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.kmac_test_vectors_kmac.168766787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1036978005
Short name	T308
Test name
Test status
Simulation time	795766376 ps
CPU time	5.91 seconds
Started	Jan 03 01:23:18 PM PST 24
Finished	Jan 03 01:23:38 PM PST 24
Peak memory	218688 kb
Host	smart-0dafac32-4063-4b56-b4aa-c7283697e1ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036978005 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1036978005 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.191888138
Short name	T407
Test name
Test status
Simulation time	34911528069 ps
CPU time	2034.86 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 01:57:22 PM PST 24
Peak memory	410764 kb
Host	smart-4f656065-3199-480d-8802-5d9f6f6256d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=191888138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.191888138 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.293278233
Short name	T263
Test name
Test status
Simulation time	64574403957 ps
CPU time	2069.07 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:58:17 PM PST 24
Peak memory	389364 kb
Host	smart-da68f7b3-e256-4d5c-8b09-a7a93d902083
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=293278233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.293278233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.3104958338
Short name	T651
Test name
Test status
Simulation time	99619856774 ps
CPU time	1677.63 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 01:51:48 PM PST 24
Peak memory	342872 kb
Host	smart-108d2895-26e2-4d97-af92-acecf1f21f53
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3104958338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3104958338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.1617486075
Short name	T718
Test name
Test status
Simulation time	49214279484 ps
CPU time	1315.62 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:45:22 PM PST 24
Peak memory	297760 kb
Host	smart-b1948ead-8bb0-4b5a-93bb-701e0e294626
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1617486075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1617486075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.3192644263
Short name	T762
Test name
Test status
Simulation time	81282107072 ps
CPU time	4892.39 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 02:45:00 PM PST 24
Peak memory	654792 kb
Host	smart-2f666008-a82e-450f-a92a-b6c96941dc76
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3192644263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3192644263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.1467298862
Short name	T854
Test name
Test status
Simulation time	55752263112 ps
CPU time	3958.14 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 02:29:47 PM PST 24
Peak memory	561824 kb
Host	smart-cff14df9-af98-4863-88c0-48055802634e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1467298862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.1467298862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.3137940960
Short name	T694
Test name
Test status
Simulation time	16748791 ps
CPU time	0.85 seconds
Started	Jan 03 01:24:01 PM PST 24
Finished	Jan 03 01:24:08 PM PST 24
Peak memory	219704 kb
Host	smart-9b8bf22a-ec37-4bf0-b2de-fdbca3090b75
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137940960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3137940960 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.2884193390
Short name	T690
Test name
Test status
Simulation time	15036272264 ps
CPU time	343.08 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:29:49 PM PST 24
Peak memory	252072 kb
Host	smart-fd101cbd-97dd-4f47-95ea-beba6148e861
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884193390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2884193390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.935363032
Short name	T768
Test name
Test status
Simulation time	12297701996 ps
CPU time	1125.11 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:42:54 PM PST 24
Peak memory	239280 kb
Host	smart-e401aef4-867f-46b3-98b7-bed3176e0020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935363032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.935363032 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.334860535
Short name	T606
Test name
Test status
Simulation time	12813051961 ps
CPU time	359.05 seconds
Started	Jan 03 01:23:58 PM PST 24
Finished	Jan 03 01:30:04 PM PST 24
Peak memory	251872 kb
Host	smart-d7f6f20e-916a-4804-8b4f-7f107e023faa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334860535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.334860535 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.2963794683
Short name	T489
Test name
Test status
Simulation time	2067562089 ps
CPU time	165.22 seconds
Started	Jan 03 01:24:01 PM PST 24
Finished	Jan 03 01:26:53 PM PST 24
Peak memory	251508 kb
Host	smart-0fdc7adc-8c27-46f0-b9ee-f48362c8b7ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963794683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2963794683 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.3740198432
Short name	T743
Test name
Test status
Simulation time	598717472 ps
CPU time	3.82 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	218752 kb
Host	smart-dcde0c47-563e-42ad-b059-c9db0de3ca27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740198432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3740198432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.3926426892
Short name	T483
Test name
Test status
Simulation time	59658765 ps
CPU time	1.57 seconds
Started	Jan 03 01:24:12 PM PST 24
Finished	Jan 03 01:24:19 PM PST 24
Peak memory	220128 kb
Host	smart-3bc6b699-a631-4359-b746-70fd8c058f21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926426892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3926426892 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.3390539308
Short name	T359
Test name
Test status
Simulation time	8500397931 ps
CPU time	230.79 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:27:43 PM PST 24
Peak memory	243300 kb
Host	smart-ffed50f6-6542-4aa2-923b-8d726329cc11
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390539308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.3390539308 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.4008866893
Short name	T836
Test name
Test status
Simulation time	36667048775 ps
CPU time	248.92 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 01:28:00 PM PST 24
Peak memory	242200 kb
Host	smart-dee5be3a-4fd1-4ec7-a7ac-21841aa27245
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008866893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.4008866893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.4241378354
Short name	T515
Test name
Test status
Simulation time	434044663 ps
CPU time	11.92 seconds
Started	Jan 03 01:23:48 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	224752 kb
Host	smart-61fa6127-c6e6-4606-81c2-e9fe1a51e2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241378354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.4241378354 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.3942586773
Short name	T571
Test name
Test status
Simulation time	3395045306 ps
CPU time	72.94 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:25:22 PM PST 24
Peak memory	243516 kb
Host	smart-c6880e1f-a097-4701-aa75-dc5633278ba9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3942586773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3942586773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.1258538922
Short name	T970
Test name
Test status
Simulation time	273578386 ps
CPU time	6.7 seconds
Started	Jan 03 01:24:11 PM PST 24
Finished	Jan 03 01:24:23 PM PST 24
Peak memory	220188 kb
Host	smart-372a2c25-18d8-481c-a52a-f41f84a8d8a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258538922 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.1258538922 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.2112442511
Short name	T549
Test name
Test status
Simulation time	539642910 ps
CPU time	5.95 seconds
Started	Jan 03 01:24:12 PM PST 24
Finished	Jan 03 01:24:23 PM PST 24
Peak memory	220244 kb
Host	smart-113277e2-254f-4caa-aabb-682fb6012500
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112442511 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.2112442511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.2733724717
Short name	T618
Test name
Test status
Simulation time	67485769988 ps
CPU time	2090.39 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:58:59 PM PST 24
Peak memory	398376 kb
Host	smart-a3bf0b85-5345-4191-9aa5-06f17f9cbe7a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2733724717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2733724717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.272366885
Short name	T1107
Test name
Test status
Simulation time	185754442907 ps
CPU time	2267.33 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 02:01:48 PM PST 24
Peak memory	386220 kb
Host	smart-0ccd6b14-3647-4f70-8c5c-fc0a6df286dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=272366885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.272366885 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.4113027633
Short name	T881
Test name
Test status
Simulation time	142937645578 ps
CPU time	1820.97 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:54:30 PM PST 24
Peak memory	338592 kb
Host	smart-ad834052-46c5-4c01-ba7a-c5e0eed252a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4113027633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.4113027633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.2054938695
Short name	T579
Test name
Test status
Simulation time	44456293457 ps
CPU time	1256.86 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 01:45:03 PM PST 24
Peak memory	301608 kb
Host	smart-a13f3d43-a067-4fb3-8e6f-86008664d749
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2054938695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2054938695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.2094527427
Short name	T469
Test name
Test status
Simulation time	63603180316 ps
CPU time	4697.65 seconds
Started	Jan 03 01:23:58 PM PST 24
Finished	Jan 03 02:42:23 PM PST 24
Peak memory	661860 kb
Host	smart-e401e3f3-b7f6-43f2-a557-974a182a6209
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2094527427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.2094527427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_app.2147839176
Short name	T625
Test name
Test status
Simulation time	9176511703 ps
CPU time	168.82 seconds
Started	Jan 03 01:23:17 PM PST 24
Finished	Jan 03 01:26:18 PM PST 24
Peak memory	242096 kb
Host	smart-ab7215ce-507a-492d-8d0f-14cef077321a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147839176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2147839176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.1911910803
Short name	T876
Test name
Test status
Simulation time	25772808880 ps
CPU time	572.67 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 01:32:59 PM PST 24
Peak memory	236164 kb
Host	smart-26a7f3d9-0f78-4109-83b5-d3e9e8debd1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911910803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1911910803 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.1543557943
Short name	T84
Test name
Test status
Simulation time	10347639016 ps
CPU time	182.39 seconds
Started	Jan 03 01:23:41 PM PST 24
Finished	Jan 03 01:26:46 PM PST 24
Peak memory	243420 kb
Host	smart-0c90bec2-bf42-4454-b882-d7a25170a941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543557943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1543557943 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.1685560467
Short name	T828
Test name
Test status
Simulation time	76770364375 ps
CPU time	423.53 seconds
Started	Jan 03 01:23:37 PM PST 24
Finished	Jan 03 01:30:44 PM PST 24
Peak memory	265948 kb
Host	smart-d5baaa6f-aa6b-47fe-a670-f8c95f1b6213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685560467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1685560467 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.2541344829
Short name	T267
Test name
Test status
Simulation time	1438609982 ps
CPU time	2.04 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:23:50 PM PST 24
Peak memory	218668 kb
Host	smart-744c6a88-66bc-4bfa-8b07-6172d2c45b21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541344829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2541344829 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.2528017897
Short name	T292
Test name
Test status
Simulation time	1697360917 ps
CPU time	38.93 seconds
Started	Jan 03 01:23:13 PM PST 24
Finished	Jan 03 01:24:06 PM PST 24
Peak memory	238460 kb
Host	smart-c163228b-7e01-4c21-a373-2de144d36ee1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528017897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2528017897 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.218548902
Short name	T472
Test name
Test status
Simulation time	15405412558 ps
CPU time	554.31 seconds
Started	Jan 03 01:24:48 PM PST 24
Finished	Jan 03 01:34:09 PM PST 24
Peak memory	268772 kb
Host	smart-83a5ba35-9b7e-4a85-9b67-d2d2768b570e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218548902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an d_output.218548902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.876319444
Short name	T747
Test name
Test status
Simulation time	4951715917 ps
CPU time	414.13 seconds
Started	Jan 03 01:24:06 PM PST 24
Finished	Jan 03 01:31:06 PM PST 24
Peak memory	255016 kb
Host	smart-078f05a7-e9ae-406b-a65f-ccb84345816e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876319444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.876319444 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.2749682548
Short name	T405
Test name
Test status
Simulation time	4917167489 ps
CPU time	30.62 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:24:45 PM PST 24
Peak memory	226988 kb
Host	smart-9975f0c4-a964-4cfc-82b4-cd1d72214623
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749682548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.2749682548 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all.4226618898
Short name	T688
Test name
Test status
Simulation time	23136518614 ps
CPU time	586.96 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:33:35 PM PST 24
Peak memory	251576 kb
Host	smart-3a251adc-1ba7-4ea7-81e0-6b43acbc46f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4226618898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.4226618898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/25.kmac_stress_all_with_rand_reset.4206847341
Short name	T24
Test name
Test status
Simulation time	260041408215 ps
CPU time	1760.41 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:53:07 PM PST 24
Peak memory	335932 kb
Host	smart-22b7f15b-90e6-47a6-a2fb-f903246beb9d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4206847341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.4206847341 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.3435994811
Short name	T1072
Test name
Test status
Simulation time	1075464720 ps
CPU time	6.88 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:23:34 PM PST 24
Peak memory	220208 kb
Host	smart-a3a50102-7c2c-4542-8f40-2026cf1f1a06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435994811 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.3435994811 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.2193467284
Short name	T910
Test name
Test status
Simulation time	191188023 ps
CPU time	6.2 seconds
Started	Jan 03 01:23:12 PM PST 24
Finished	Jan 03 01:23:33 PM PST 24
Peak memory	218812 kb
Host	smart-2eb67674-12b2-49c8-b12a-a2da22aecd21
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193467284 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.2193467284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.971479103
Short name	T1027
Test name
Test status
Simulation time	20472667073 ps
CPU time	2035.33 seconds
Started	Jan 03 01:23:12 PM PST 24
Finished	Jan 03 01:57:22 PM PST 24
Peak memory	401508 kb
Host	smart-88aa9d1f-ba80-44a2-aec6-9ed28c017747
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=971479103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.971479103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.1206921269
Short name	T485
Test name
Test status
Simulation time	19452562461 ps
CPU time	1886.44 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:54:53 PM PST 24
Peak memory	395520 kb
Host	smart-da97eccb-da3d-48c3-ae96-e9426f0c51db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1206921269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1206921269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.69297696
Short name	T633
Test name
Test status
Simulation time	16036751075 ps
CPU time	1522.28 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:49:04 PM PST 24
Peak memory	344184 kb
Host	smart-8ba10ec4-a387-4c73-b6c2-0fe53276bf14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=69297696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.69297696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.2430520535
Short name	T832
Test name
Test status
Simulation time	142525299719 ps
CPU time	1311.29 seconds
Started	Jan 03 01:23:10 PM PST 24
Finished	Jan 03 01:45:14 PM PST 24
Peak memory	306948 kb
Host	smart-adc249ef-2b1c-410f-b977-a446d0bc5683
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2430520535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2430520535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.1281258132
Short name	T181
Test name
Test status
Simulation time	443631283895 ps
CPU time	4684.77 seconds
Started	Jan 03 01:23:12 PM PST 24
Finished	Jan 03 02:41:32 PM PST 24
Peak memory	671752 kb
Host	smart-dc8be905-fa84-4360-a9af-83fb61f5f579
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1281258132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.1281258132 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.2110503490
Short name	T802
Test name
Test status
Simulation time	995141415641 ps
CPU time	5107.81 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 02:48:35 PM PST 24
Peak memory	575068 kb
Host	smart-f489bc1c-a93a-4186-abdf-f97df723a144
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2110503490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2110503490 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.582334016
Short name	T943
Test name
Test status
Simulation time	14173218 ps
CPU time	0.84 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:24:11 PM PST 24
Peak memory	218480 kb
Host	smart-793a3b6d-3a74-409f-9088-160791e0605c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582334016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.582334016 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.2543586739
Short name	T254
Test name
Test status
Simulation time	22702537516 ps
CPU time	338.73 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:29:38 PM PST 24
Peak memory	251616 kb
Host	smart-9f833360-9dd4-46d3-bf53-5ccf8f222c78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543586739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2543586739 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.3508729981
Short name	T218
Test name
Test status
Simulation time	26216954804 ps
CPU time	392.45 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:30:21 PM PST 24
Peak memory	242756 kb
Host	smart-96bf9b10-991e-4ba6-965e-c5c580798ebd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508729981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3508729981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.371324346
Short name	T86
Test name
Test status
Simulation time	8869818788 ps
CPU time	235.56 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 01:28:21 PM PST 24
Peak memory	247072 kb
Host	smart-89630f2a-3c92-46a8-a4e9-37ef4c7ea91e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371324346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.371324346 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.2584162779
Short name	T1077
Test name
Test status
Simulation time	1400162568 ps
CPU time	98.06 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:25:47 PM PST 24
Peak memory	243552 kb
Host	smart-ad665995-5fd5-471d-a576-9975f2a548a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584162779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2584162779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.1846190824
Short name	T444
Test name
Test status
Simulation time	2844184765 ps
CPU time	4.1 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:24:14 PM PST 24
Peak memory	218636 kb
Host	smart-d47b1bf1-3ac1-44fe-a4f9-fec3a038ca4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846190824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1846190824 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.980589857
Short name	T177
Test name
Test status
Simulation time	41499051 ps
CPU time	1.44 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	219932 kb
Host	smart-ae6a716f-cc43-47bd-8a4f-c1c2f554e2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980589857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.980589857 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.3241344220
Short name	T197
Test name
Test status
Simulation time	25165305400 ps
CPU time	2548.97 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 02:06:18 PM PST 24
Peak memory	456868 kb
Host	smart-6f75eca3-544f-4ad2-b1ef-00db0bc34672
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241344220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.3241344220 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.1177914068
Short name	T538
Test name
Test status
Simulation time	6217057570 ps
CPU time	192.78 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:26:59 PM PST 24
Peak memory	240684 kb
Host	smart-4c6cb024-9668-47f6-b361-6961cb81afde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177914068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1177914068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.1043665620
Short name	T529
Test name
Test status
Simulation time	6774668614 ps
CPU time	90.82 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:24:58 PM PST 24
Peak memory	225596 kb
Host	smart-8007085c-d9fd-4ef3-9e5f-cbfb906650bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043665620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1043665620 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.504485995
Short name	T703
Test name
Test status
Simulation time	1141757677698 ps
CPU time	1582.81 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:50:22 PM PST 24
Peak memory	286260 kb
Host	smart-74a25ab7-4cbe-4039-9793-3ccbda8ef798
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=504485995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.504485995 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.2986983871
Short name	T810
Test name
Test status
Simulation time	692212754 ps
CPU time	5.92 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:23:59 PM PST 24
Peak memory	218832 kb
Host	smart-bef35689-9fe9-4de1-af41-366f17a576e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986983871 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.2986983871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2177498906
Short name	T271
Test name
Test status
Simulation time	229632909 ps
CPU time	6.51 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	218808 kb
Host	smart-d10f599e-4611-473b-ba47-81f643a6b411
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177498906 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2177498906 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.2332626051
Short name	T624
Test name
Test status
Simulation time	267782032963 ps
CPU time	2382.65 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 02:03:41 PM PST 24
Peak memory	406496 kb
Host	smart-ceee837a-4cc8-4254-bfea-8d945ea22bb5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2332626051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2332626051 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.1461520599
Short name	T673
Test name
Test status
Simulation time	314385790246 ps
CPU time	1951.71 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:56:24 PM PST 24
Peak memory	384820 kb
Host	smart-4976e331-5b82-422a-bd50-acce5c9ebee9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1461520599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1461520599 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.1132237183
Short name	T6
Test name
Test status
Simulation time	20156949482 ps
CPU time	1365.28 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:46:48 PM PST 24
Peak memory	339676 kb
Host	smart-6db2ac91-1a75-422c-a3c7-ce3063c27078
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1132237183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1132237183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.1974327492
Short name	T505
Test name
Test status
Simulation time	29741919123 ps
CPU time	1116.88 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:42:46 PM PST 24
Peak memory	300548 kb
Host	smart-6f254807-2830-4de4-a7fa-529407d224ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1974327492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1974327492 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.3631534791
Short name	T1122
Test name
Test status
Simulation time	260783127839 ps
CPU time	6174.04 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 03:07:00 PM PST 24
Peak memory	653752 kb
Host	smart-4f177f7e-93b5-4c64-8462-9dec45313581
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3631534791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3631534791 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.3981361181
Short name	T440
Test name
Test status
Simulation time	296614862427 ps
CPU time	4410.6 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 02:37:28 PM PST 24
Peak memory	563724 kb
Host	smart-2668da93-854f-4905-93f2-349325b15e5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3981361181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3981361181 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.1586491668
Short name	T759
Test name
Test status
Simulation time	17522479 ps
CPU time	0.88 seconds
Started	Jan 03 01:23:17 PM PST 24
Finished	Jan 03 01:23:30 PM PST 24
Peak memory	218544 kb
Host	smart-d6983201-cec1-436c-8d5c-2779ac1987c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586491668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1586491668 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.2355419943
Short name	T473
Test name
Test status
Simulation time	5865021392 ps
CPU time	88.25 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:25:09 PM PST 24
Peak memory	235148 kb
Host	smart-86d56643-187e-4738-b58f-206593ca3922
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355419943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2355419943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.4033817427
Short name	T740
Test name
Test status
Simulation time	43546458598 ps
CPU time	1003.06 seconds
Started	Jan 03 01:24:12 PM PST 24
Finished	Jan 03 01:41:00 PM PST 24
Peak memory	240064 kb
Host	smart-bd2ffe81-38fa-462e-8ebf-35091ec4f871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033817427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.4033817427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.380999419
Short name	T840
Test name
Test status
Simulation time	4237542687 ps
CPU time	92.6 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:25:46 PM PST 24
Peak memory	233956 kb
Host	smart-d892fc13-2cfd-4c36-8951-9da68712ea1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380999419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.380999419 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.1275641848
Short name	T922
Test name
Test status
Simulation time	48811724318 ps
CPU time	334.48 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:30:35 PM PST 24
Peak memory	259820 kb
Host	smart-d534ca81-4afc-41d8-9479-259a2cc787d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275641848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1275641848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.3643312533
Short name	T890
Test name
Test status
Simulation time	4516740235 ps
CPU time	2.53 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:23:29 PM PST 24
Peak memory	218816 kb
Host	smart-81e5fd3a-8d7b-4f3a-8eda-3dc7234c2ab7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643312533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3643312533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.1858264042
Short name	T1022
Test name
Test status
Simulation time	196120278723 ps
CPU time	3045.18 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 02:14:56 PM PST 24
Peak memory	474568 kb
Host	smart-f0b35f04-177a-4a55-8910-02c0e5d0f37e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858264042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.1858264042 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.2781277585
Short name	T615
Test name
Test status
Simulation time	818793093 ps
CPU time	27.59 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:24:35 PM PST 24
Peak memory	227852 kb
Host	smart-ccb39afb-bb0f-4bec-a704-6bcf5925dd8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781277585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2781277585 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.3252510669
Short name	T451
Test name
Test status
Simulation time	1658524540 ps
CPU time	21.4 seconds
Started	Jan 03 01:24:13 PM PST 24
Finished	Jan 03 01:24:39 PM PST 24
Peak memory	226760 kb
Host	smart-d8f884dd-3702-44b7-8997-ec5b69677686
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252510669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3252510669 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all.1950512767
Short name	T1054
Test name
Test status
Simulation time	712301776003 ps
CPU time	1500.17 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:48:48 PM PST 24
Peak memory	343304 kb
Host	smart-3fff97da-2407-48a6-9924-a4ff5159d7f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1950512767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1950512767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all/latest

Test location	/workspace/coverage/default/27.kmac_stress_all_with_rand_reset.1382264490
Short name	T745
Test name
Test status
Simulation time	171349882153 ps
CPU time	733.44 seconds
Started	Jan 03 01:23:39 PM PST 24
Finished	Jan 03 01:35:55 PM PST 24
Peak memory	276156 kb
Host	smart-869b55da-f54f-445b-a2ef-fa16ab2472b9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1382264490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.1382264490 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.3870727814
Short name	T540
Test name
Test status
Simulation time	428143721 ps
CPU time	6.33 seconds
Started	Jan 03 01:24:06 PM PST 24
Finished	Jan 03 01:24:18 PM PST 24
Peak memory	220344 kb
Host	smart-f74af7b9-d776-4767-8a95-9b552cb3f2c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870727814 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.3870727814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2291622751
Short name	T1041
Test name
Test status
Simulation time	403410155 ps
CPU time	6.14 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:37 PM PST 24
Peak memory	220092 kb
Host	smart-57908b55-075f-4e6f-b02d-ba0ed07d9717
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291622751 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2291622751 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.162766055
Short name	T1031
Test name
Test status
Simulation time	67187921398 ps
CPU time	2158.73 seconds
Started	Jan 03 01:24:11 PM PST 24
Finished	Jan 03 02:00:15 PM PST 24
Peak memory	394208 kb
Host	smart-424209f3-3ced-4d06-bd73-d0cc06545b7f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=162766055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.162766055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.3444432324
Short name	T1076
Test name
Test status
Simulation time	20226561520 ps
CPU time	1877.07 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:55:30 PM PST 24
Peak memory	390196 kb
Host	smart-bbc9f7c3-805c-414e-bf17-d6dd2a020a5c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3444432324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3444432324 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.3950969800
Short name	T562
Test name
Test status
Simulation time	1169061382755 ps
CPU time	2104.84 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:59:20 PM PST 24
Peak memory	341084 kb
Host	smart-1a736168-d571-4b68-a925-c3084ebc5a1a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3950969800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3950969800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.3251298213
Short name	T983
Test name
Test status
Simulation time	13018803090 ps
CPU time	1110.76 seconds
Started	Jan 03 01:24:31 PM PST 24
Finished	Jan 03 01:43:06 PM PST 24
Peak memory	301960 kb
Host	smart-5ddf4f41-b98f-4048-8367-ad6963731c25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3251298213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.3251298213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.4078094140
Short name	T992
Test name
Test status
Simulation time	714732964269 ps
CPU time	5760.21 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 03:00:27 PM PST 24
Peak memory	668176 kb
Host	smart-9e797668-cac7-4a6c-928a-7aba73f3ce75
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4078094140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.4078094140 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.1503534097
Short name	T1066
Test name
Test status
Simulation time	55127938506 ps
CPU time	4127.93 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 02:32:36 PM PST 24
Peak memory	567340 kb
Host	smart-7931c950-5cf4-44ba-a5f2-848bc92ad8d0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1503534097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1503534097 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.169703073
Short name	T652
Test name
Test status
Simulation time	45041715 ps
CPU time	0.94 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:24:15 PM PST 24
Peak memory	218656 kb
Host	smart-f952de66-0a62-466c-957f-fdc375259e7d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169703073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.169703073 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.1054425782
Short name	T791
Test name
Test status
Simulation time	1780213796 ps
CPU time	11.48 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	226508 kb
Host	smart-8fb84faf-c804-479b-8454-e99362d076e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054425782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1054425782 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.4187655315
Short name	T653
Test name
Test status
Simulation time	21927224158 ps
CPU time	1028.78 seconds
Started	Jan 03 01:23:14 PM PST 24
Finished	Jan 03 01:40:36 PM PST 24
Peak memory	239328 kb
Host	smart-8c4f861f-c0ff-4d7a-987b-0560bf82df5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187655315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.4187655315 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.1447166538
Short name	T608
Test name
Test status
Simulation time	15062720957 ps
CPU time	279.8 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 01:28:31 PM PST 24
Peak memory	248532 kb
Host	smart-93652512-547a-49b1-9930-95510c57db7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447166538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1447166538 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_error.292621466
Short name	T1070
Test name
Test status
Simulation time	4455544397 ps
CPU time	370.31 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:30:09 PM PST 24
Peak memory	271432 kb
Host	smart-6c135e1c-1b46-4c6f-9f40-2655c2bd10ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292621466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.292621466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.4121523192
Short name	T858
Test name
Test status
Simulation time	423802426 ps
CPU time	1.32 seconds
Started	Jan 03 01:23:48 PM PST 24
Finished	Jan 03 01:23:53 PM PST 24
Peak memory	218384 kb
Host	smart-fb7a0047-21e8-451b-b2e2-e9d571ee2475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121523192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4121523192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.988526726
Short name	T187
Test name
Test status
Simulation time	94987219 ps
CPU time	1.33 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:23:54 PM PST 24
Peak memory	219968 kb
Host	smart-879fc627-9e4d-4026-9612-ab14f6c00799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988526726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.988526726 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.938871553
Short name	T859
Test name
Test status
Simulation time	217811155132 ps
CPU time	2170.95 seconds
Started	Jan 03 01:23:12 PM PST 24
Finished	Jan 03 01:59:38 PM PST 24
Peak memory	398892 kb
Host	smart-a94e2b6a-9459-4962-a661-fa4192f35caf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938871553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an d_output.938871553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.1984105360
Short name	T545
Test name
Test status
Simulation time	16451036687 ps
CPU time	427.68 seconds
Started	Jan 03 01:23:40 PM PST 24
Finished	Jan 03 01:30:49 PM PST 24
Peak memory	250812 kb
Host	smart-2d093f2f-0eda-4ace-abb4-2b7a94e35a64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984105360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1984105360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.3082732891
Short name	T990
Test name
Test status
Simulation time	3838639491 ps
CPU time	40.26 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:24:26 PM PST 24
Peak memory	224556 kb
Host	smart-6037bc93-fe6c-4c4f-b4b5-f74b881a601a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082732891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3082732891 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.2447328292
Short name	T805
Test name
Test status
Simulation time	83076555558 ps
CPU time	2215.42 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 02:00:55 PM PST 24
Peak memory	419240 kb
Host	smart-8e5b63a2-9687-4428-9f11-c0115cb0b578
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2447328292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2447328292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.4255602794
Short name	T328
Test name
Test status
Simulation time	2185245798 ps
CPU time	6.2 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:15 PM PST 24
Peak memory	218876 kb
Host	smart-3c9cf058-35ae-43d3-ab9f-86461830637c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255602794 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.4255602794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3556650216
Short name	T622
Test name
Test status
Simulation time	258126243 ps
CPU time	6.16 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	218876 kb
Host	smart-20b9774b-def7-4827-bbbf-9ca007143400
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556650216 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3556650216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.2477973831
Short name	T203
Test name
Test status
Simulation time	67427954971 ps
CPU time	2362.23 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 02:03:10 PM PST 24
Peak memory	401932 kb
Host	smart-89042968-fdc8-473e-b3d2-3cd2cc0aba98
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2477973831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2477973831 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.4077100101
Short name	T1086
Test name
Test status
Simulation time	81441144897 ps
CPU time	1861.36 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 01:54:51 PM PST 24
Peak memory	390340 kb
Host	smart-333158ff-e39a-4b88-b322-267ffc7b82f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4077100101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.4077100101 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.2260396816
Short name	T720
Test name
Test status
Simulation time	46638222133 ps
CPU time	1594.51 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:50:21 PM PST 24
Peak memory	337016 kb
Host	smart-381b1bd3-1a17-409a-986f-0e6c751a5e18
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2260396816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2260396816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.771629517
Short name	T1123
Test name
Test status
Simulation time	150664149660 ps
CPU time	1243.9 seconds
Started	Jan 03 01:23:51 PM PST 24
Finished	Jan 03 01:44:40 PM PST 24
Peak memory	301748 kb
Host	smart-6b47a4d4-4e6a-43b3-8853-0cce654a56ea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=771629517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.771629517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.1675530828
Short name	T418
Test name
Test status
Simulation time	3550250684282 ps
CPU time	6304.52 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 03:09:02 PM PST 24
Peak memory	661916 kb
Host	smart-59730eec-ac92-4212-9307-dc553c6beddc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1675530828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.1675530828 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.2318062825
Short name	T510
Test name
Test status
Simulation time	238361229814 ps
CPU time	4084.61 seconds
Started	Jan 03 01:23:15 PM PST 24
Finished	Jan 03 02:31:32 PM PST 24
Peak memory	578808 kb
Host	smart-1c482e62-e7ca-4182-bf6f-392c582cecd1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2318062825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2318062825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.3032128142
Short name	T311
Test name
Test status
Simulation time	74031609 ps
CPU time	0.83 seconds
Started	Jan 03 01:23:37 PM PST 24
Finished	Jan 03 01:23:41 PM PST 24
Peak memory	218648 kb
Host	smart-440e41ce-9530-438f-874c-524c28626d42
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032128142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3032128142 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.559669400
Short name	T370
Test name
Test status
Simulation time	4832323354 ps
CPU time	26.29 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 01:25:15 PM PST 24
Peak memory	226052 kb
Host	smart-2b726b27-d09a-48fe-b16b-dbef04d00f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559669400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.559669400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.1104763900
Short name	T692
Test name
Test status
Simulation time	27670530025 ps
CPU time	713.24 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:36:08 PM PST 24
Peak memory	236540 kb
Host	smart-e8d81e87-a469-4f16-8ac7-52b4e2d3bcb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104763900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1104763900 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.2455715469
Short name	T883
Test name
Test status
Simulation time	7816293177 ps
CPU time	380.07 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:30:27 PM PST 24
Peak memory	254704 kb
Host	smart-f670442d-74aa-4d9e-be99-3ca0276d625b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455715469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2455715469 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.2779453177
Short name	T631
Test name
Test status
Simulation time	6323555865 ps
CPU time	36.97 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 01:25:03 PM PST 24
Peak memory	243252 kb
Host	smart-e1398864-471c-48ee-8a5c-2ea330b6db24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779453177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2779453177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.3382249027
Short name	T52
Test name
Test status
Simulation time	3525504155 ps
CPU time	6.36 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 01:23:43 PM PST 24
Peak memory	218740 kb
Host	smart-ee003d6d-edd1-4e26-b226-10d383620d3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382249027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3382249027 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.3434709694
Short name	T730
Test name
Test status
Simulation time	5701371247 ps
CPU time	13.78 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	235360 kb
Host	smart-b73481cd-0035-4f6a-bbbf-7140eca62055
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434709694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3434709694 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.332413314
Short name	T194
Test name
Test status
Simulation time	1098844820220 ps
CPU time	3400.5 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 02:20:55 PM PST 24
Peak memory	481856 kb
Host	smart-bebcb9c0-c0fc-44df-9cb1-10531b28b38c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332413314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_an d_output.332413314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.3416896298
Short name	T1061
Test name
Test status
Simulation time	19148749984 ps
CPU time	422.18 seconds
Started	Jan 03 01:24:10 PM PST 24
Finished	Jan 03 01:31:18 PM PST 24
Peak memory	254276 kb
Host	smart-a8902a46-87c4-45c4-81c1-de0fad731248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416896298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3416896298 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.2915492802
Short name	T568
Test name
Test status
Simulation time	249710963 ps
CPU time	5.39 seconds
Started	Jan 03 01:24:19 PM PST 24
Finished	Jan 03 01:24:26 PM PST 24
Peak memory	226912 kb
Host	smart-7b96c9ca-b355-46c6-8b32-076fbf943d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915492802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2915492802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.3568212556
Short name	T457
Test name
Test status
Simulation time	14454450573 ps
CPU time	747.16 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:36:16 PM PST 24
Peak memory	333616 kb
Host	smart-f32ddffb-724c-4c01-a87a-21cfa6e22375
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3568212556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3568212556 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.1147061349
Short name	T997
Test name
Test status
Simulation time	43250113523 ps
CPU time	1017.04 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:40:45 PM PST 24
Peak memory	309016 kb
Host	smart-2d849381-e3da-41d1-ab9a-8a6e40a6525d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1147061349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.1147061349 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.873284972
Short name	T191
Test name
Test status
Simulation time	1203036651 ps
CPU time	7.08 seconds
Started	Jan 03 01:24:23 PM PST 24
Finished	Jan 03 01:24:32 PM PST 24
Peak memory	220128 kb
Host	smart-ac46ea22-d90e-4573-86e7-3de91893ebad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873284972 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.kmac_test_vectors_kmac.873284972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2745723242
Short name	T224
Test name
Test status
Simulation time	821664253 ps
CPU time	6.89 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:25:06 PM PST 24
Peak memory	220080 kb
Host	smart-b3346763-9282-4a2e-8a1f-94551e3f0405
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745723242 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2745723242 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.941588171
Short name	T757
Test name
Test status
Simulation time	288497665152 ps
CPU time	2305.29 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 02:03:24 PM PST 24
Peak memory	401292 kb
Host	smart-d15fa14a-3c9c-4a4d-8c8f-283a705032f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=941588171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.941588171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.2233024603
Short name	T1082
Test name
Test status
Simulation time	429150122853 ps
CPU time	2153.94 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 02:00:00 PM PST 24
Peak memory	390528 kb
Host	smart-040ecc9f-3109-4582-bd27-279ecab20de5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2233024603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.2233024603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.2566436639
Short name	T307
Test name
Test status
Simulation time	147672789622 ps
CPU time	1898.57 seconds
Started	Jan 03 01:24:13 PM PST 24
Finished	Jan 03 01:55:57 PM PST 24
Peak memory	343132 kb
Host	smart-38cf1cfc-b6c7-4a9e-9114-aa8b0dafc648
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2566436639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2566436639 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.594732467
Short name	T821
Test name
Test status
Simulation time	44323186289 ps
CPU time	1184.73 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:43:52 PM PST 24
Peak memory	302196 kb
Host	smart-861c31d5-f869-4100-b517-7899b5fbb4bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=594732467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.594732467 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.488146742
Short name	T611
Test name
Test status
Simulation time	236048474363 ps
CPU time	5746.87 seconds
Started	Jan 03 01:24:32 PM PST 24
Finished	Jan 03 03:00:24 PM PST 24
Peak memory	653364 kb
Host	smart-05f17d20-d5a1-4562-9e63-43853086fc03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=488146742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.488146742 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.541810284
Short name	T340
Test name
Test status
Simulation time	969745297068 ps
CPU time	5384.42 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 02:53:43 PM PST 24
Peak memory	589424 kb
Host	smart-7d4c4e05-7577-45f8-9f29-31709f70d0ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=541810284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.541810284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.2408007176
Short name	T689
Test name
Test status
Simulation time	18321282 ps
CPU time	0.85 seconds
Started	Jan 03 01:19:40 PM PST 24
Finished	Jan 03 01:19:46 PM PST 24
Peak memory	219744 kb
Host	smart-6d0dd292-81b2-470e-878c-a784532c9c69
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408007176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2408007176 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.855481170
Short name	T501
Test name
Test status
Simulation time	17805140540 ps
CPU time	169.36 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:22:20 PM PST 24
Peak memory	242200 kb
Host	smart-c76fe7b3-91a3-4754-919f-955885c06a18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855481170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.855481170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.1925791517
Short name	T1028
Test name
Test status
Simulation time	25681801246 ps
CPU time	139.98 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:21:51 PM PST 24
Peak memory	243332 kb
Host	smart-1a0735d8-f7f4-4028-9102-f9ef414c743e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925791517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1925791517 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.1259045346
Short name	T896
Test name
Test status
Simulation time	164672410993 ps
CPU time	794.59 seconds
Started	Jan 03 01:19:30 PM PST 24
Finished	Jan 03 01:32:50 PM PST 24
Peak memory	243260 kb
Host	smart-81cebfc2-d3a4-4525-9f93-64573286234b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259045346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1259045346 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.2258498617
Short name	T543
Test name
Test status
Simulation time	69715867 ps
CPU time	1.11 seconds
Started	Jan 03 01:19:43 PM PST 24
Finished	Jan 03 01:19:50 PM PST 24
Peak memory	218600 kb
Host	smart-28111f5f-34b8-406e-bd2e-c65410d82a48
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2258498617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2258498617 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.3262526947
Short name	T35
Test name
Test status
Simulation time	4482905496 ps
CPU time	48.67 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 01:20:20 PM PST 24
Peak memory	229784 kb
Host	smart-77a4bac2-f075-4933-a9d5-ec82b799ba1d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3262526947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3262526947 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.2009238438
Short name	T49
Test name
Test status
Simulation time	14446419833 ps
CPU time	38.23 seconds
Started	Jan 03 01:19:38 PM PST 24
Finished	Jan 03 01:20:20 PM PST 24
Peak memory	226944 kb
Host	smart-26a710a3-34ae-4c6b-9ccf-5038c45a4c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009238438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2009238438 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.2907677529
Short name	T282
Test name
Test status
Simulation time	34304787751 ps
CPU time	201.34 seconds
Started	Jan 03 01:19:30 PM PST 24
Finished	Jan 03 01:22:56 PM PST 24
Peak memory	242188 kb
Host	smart-7f41bbbe-66bc-4efd-97ab-86a1cfbf5b32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907677529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2907677529 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.1444936270
Short name	T975
Test name
Test status
Simulation time	53317785731 ps
CPU time	385.02 seconds
Started	Jan 03 01:19:29 PM PST 24
Finished	Jan 03 01:25:59 PM PST 24
Peak memory	262472 kb
Host	smart-fd630ba4-f59b-4397-b608-704ee05e9b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444936270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1444936270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.1207525631
Short name	T420
Test name
Test status
Simulation time	316264075 ps
CPU time	2.62 seconds
Started	Jan 03 01:19:35 PM PST 24
Finished	Jan 03 01:19:41 PM PST 24
Peak memory	218724 kb
Host	smart-646030c1-b4ad-43b0-bfeb-c77da73c9736
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207525631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1207525631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.809496411
Short name	T402
Test name
Test status
Simulation time	79119389 ps
CPU time	1.42 seconds
Started	Jan 03 01:19:38 PM PST 24
Finished	Jan 03 01:19:44 PM PST 24
Peak memory	219812 kb
Host	smart-b2d6a172-5eb3-4fde-b8a7-7e26a519c79b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809496411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.809496411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.3145710235
Short name	T1136
Test name
Test status
Simulation time	50544333596 ps
CPU time	1269.41 seconds
Started	Jan 03 01:20:33 PM PST 24
Finished	Jan 03 01:41:46 PM PST 24
Peak memory	338572 kb
Host	smart-be0bbf00-557e-4314-9685-839036f34a77
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145710235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.3145710235 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.4158088569
Short name	T911
Test name
Test status
Simulation time	143793066067 ps
CPU time	322.16 seconds
Started	Jan 03 01:19:37 PM PST 24
Finished	Jan 03 01:25:03 PM PST 24
Peak memory	250068 kb
Host	smart-db914a0b-ed17-4b4b-9cbc-2af1765b946a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158088569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.4158088569 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.2096924262
Short name	T110
Test name
Test status
Simulation time	12794806847 ps
CPU time	41.4 seconds
Started	Jan 03 01:19:39 PM PST 24
Finished	Jan 03 01:20:24 PM PST 24
Peak memory	250464 kb
Host	smart-b17bb974-fe2a-4e29-9ea1-5a4be583899c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096924262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2096924262 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.164813216
Short name	T909
Test name
Test status
Simulation time	3410199833 ps
CPU time	111.26 seconds
Started	Jan 03 01:19:34 PM PST 24
Finished	Jan 03 01:21:28 PM PST 24
Peak memory	242312 kb
Host	smart-53b73d78-76b4-48d3-bfd6-224e9e9ce891
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164813216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.164813216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.4098511609
Short name	T722
Test name
Test status
Simulation time	11773111561 ps
CPU time	73.11 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:21:49 PM PST 24
Peak memory	226972 kb
Host	smart-ddaa6ecf-6253-40ab-9893-d4d6eb8311bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098511609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4098511609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.1038636298
Short name	T662
Test name
Test status
Simulation time	51726699772 ps
CPU time	1177.74 seconds
Started	Jan 03 01:19:30 PM PST 24
Finished	Jan 03 01:39:13 PM PST 24
Peak memory	355696 kb
Host	smart-af610971-8307-46a5-ba22-f991f8100878
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1038636298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1038636298 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.2219179545
Short name	T352
Test name
Test status
Simulation time	29760340321 ps
CPU time	1808.96 seconds
Started	Jan 03 01:19:42 PM PST 24
Finished	Jan 03 01:49:57 PM PST 24
Peak memory	317216 kb
Host	smart-34bdbb72-c8d9-4f01-8ec6-506ecfb64270
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2219179545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.2219179545 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1550797393
Short name	T482
Test name
Test status
Simulation time	3185382354 ps
CPU time	7.22 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:19:29 PM PST 24
Peak memory	220236 kb
Host	smart-35879773-93f4-4848-914d-38d2f10eb5a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550797393 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1550797393 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.999214272
Short name	T800
Test name
Test status
Simulation time	21804439564 ps
CPU time	2026.81 seconds
Started	Jan 03 01:19:27 PM PST 24
Finished	Jan 03 01:53:19 PM PST 24
Peak memory	399560 kb
Host	smart-0b3aa39c-339c-4cf5-ac35-597e94a838f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=999214272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.999214272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.3308128571
Short name	T269
Test name
Test status
Simulation time	83163570294 ps
CPU time	1989.32 seconds
Started	Jan 03 01:19:31 PM PST 24
Finished	Jan 03 01:52:45 PM PST 24
Peak memory	392616 kb
Host	smart-f6e53f22-0923-4f5e-a757-289eea9a9a54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3308128571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3308128571 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.3133617540
Short name	T260
Test name
Test status
Simulation time	49228832990 ps
CPU time	1615.7 seconds
Started	Jan 03 01:19:18 PM PST 24
Finished	Jan 03 01:46:18 PM PST 24
Peak memory	339660 kb
Host	smart-4e776873-2c39-4e97-bca3-9b76a90a0dd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3133617540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3133617540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.3248668483
Short name	T450
Test name
Test status
Simulation time	51570072716 ps
CPU time	1280.4 seconds
Started	Jan 03 01:19:22 PM PST 24
Finished	Jan 03 01:40:47 PM PST 24
Peak memory	301996 kb
Host	smart-5b68a1c2-96dd-4517-8aa6-0c6c933b8dbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3248668483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3248668483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.1534224078
Short name	T430
Test name
Test status
Simulation time	67759963830 ps
CPU time	4861.19 seconds
Started	Jan 03 01:19:19 PM PST 24
Finished	Jan 03 02:40:24 PM PST 24
Peak memory	656860 kb
Host	smart-20b5db6a-26a9-4b67-a5b7-4289c93081cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1534224078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1534224078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.3011081982
Short name	T721
Test name
Test status
Simulation time	210716684814 ps
CPU time	4111.62 seconds
Started	Jan 03 01:19:26 PM PST 24
Finished	Jan 03 02:28:03 PM PST 24
Peak memory	578768 kb
Host	smart-9143a69b-3797-4210-88f9-61d76e020616
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3011081982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3011081982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.2235262720
Short name	T1055
Test name
Test status
Simulation time	12975140 ps
CPU time	0.83 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 01:23:51 PM PST 24
Peak memory	219744 kb
Host	smart-15d3223a-a0ff-4f43-bf4d-d375efc2aad6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235262720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2235262720 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.1714235755
Short name	T276
Test name
Test status
Simulation time	34195303668 ps
CPU time	419.56 seconds
Started	Jan 03 01:23:28 PM PST 24
Finished	Jan 03 01:30:35 PM PST 24
Peak memory	258400 kb
Host	smart-33569616-7945-426c-aa1e-42bb03564aef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714235755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1714235755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.956818609
Short name	T830
Test name
Test status
Simulation time	6171491442 ps
CPU time	297.51 seconds
Started	Jan 03 01:23:30 PM PST 24
Finished	Jan 03 01:28:33 PM PST 24
Peak memory	238756 kb
Host	smart-04dbe613-49f2-4977-b524-080971022a86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956818609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.956818609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.3987293856
Short name	T1113
Test name
Test status
Simulation time	43944688296 ps
CPU time	284.94 seconds
Started	Jan 03 01:23:31 PM PST 24
Finished	Jan 03 01:28:21 PM PST 24
Peak memory	250556 kb
Host	smart-c7fba4a7-4410-4151-a912-e78d7c4f3656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987293856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3987293856 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.2900311451
Short name	T594
Test name
Test status
Simulation time	13026568975 ps
CPU time	211.14 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 01:27:22 PM PST 24
Peak memory	253920 kb
Host	smart-e9c07573-93e4-4016-9daf-8d016fe91f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900311451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2900311451 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.1533323685
Short name	T1002
Test name
Test status
Simulation time	5311025886 ps
CPU time	7.83 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:24:10 PM PST 24
Peak memory	218728 kb
Host	smart-25c6480c-307a-45c5-883e-01a305bbf3e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533323685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1533323685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.1568702720
Short name	T322
Test name
Test status
Simulation time	67156334 ps
CPU time	1.21 seconds
Started	Jan 03 01:23:48 PM PST 24
Finished	Jan 03 01:23:53 PM PST 24
Peak memory	219836 kb
Host	smart-9efc58a2-89ce-4fcb-ab89-52c9d8794677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568702720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1568702720 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.1457976849
Short name	T214
Test name
Test status
Simulation time	87233143239 ps
CPU time	1179.3 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:43:26 PM PST 24
Peak memory	321912 kb
Host	smart-3a996837-44db-45d7-84bf-1a17e7cbca4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457976849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a nd_output.1457976849 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.3947814162
Short name	T699
Test name
Test status
Simulation time	2023650460 ps
CPU time	45.44 seconds
Started	Jan 03 01:23:30 PM PST 24
Finished	Jan 03 01:24:22 PM PST 24
Peak memory	233740 kb
Host	smart-f80cdb34-ce5f-46ac-9e5b-34de49f433a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947814162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3947814162 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.3140896261
Short name	T551
Test name
Test status
Simulation time	255643088 ps
CPU time	7.3 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 01:23:44 PM PST 24
Peak memory	226944 kb
Host	smart-4e327f44-bf31-4b0a-8be8-137e599c5a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140896261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3140896261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.614503432
Short name	T377
Test name
Test status
Simulation time	4775848717 ps
CPU time	440.47 seconds
Started	Jan 03 01:24:06 PM PST 24
Finished	Jan 03 01:31:32 PM PST 24
Peak memory	292784 kb
Host	smart-f1d17886-3412-48c7-9968-0f341d010e8c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=614503432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.614503432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.981137035
Short name	T343
Test name
Test status
Simulation time	721125932 ps
CPU time	5.75 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:23:52 PM PST 24
Peak memory	220100 kb
Host	smart-59b86d3c-53d8-4944-b46b-995ac711e3ec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981137035 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.kmac_test_vectors_kmac.981137035 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3529528486
Short name	T570
Test name
Test status
Simulation time	434096004 ps
CPU time	6.06 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:23:55 PM PST 24
Peak memory	218820 kb
Host	smart-79be41b9-66b4-4678-bac7-7e79318becc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529528486 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3529528486 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.2985686754
Short name	T280
Test name
Test status
Simulation time	403031607787 ps
CPU time	2432.99 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 02:04:21 PM PST 24
Peak memory	393780 kb
Host	smart-03dfa35b-f50d-4305-b1e9-2eab35eeffaa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2985686754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2985686754 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.941694304
Short name	T1101
Test name
Test status
Simulation time	273125394978 ps
CPU time	2181.17 seconds
Started	Jan 03 01:23:40 PM PST 24
Finished	Jan 03 02:00:04 PM PST 24
Peak memory	390672 kb
Host	smart-2f60dddc-66ed-47da-9086-5ac7227c00cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=941694304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.941694304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.2029079975
Short name	T1005
Test name
Test status
Simulation time	628479839865 ps
CPU time	1849.69 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:54:36 PM PST 24
Peak memory	337512 kb
Host	smart-83c443b5-0acb-42cf-84e3-e48a307c971d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2029079975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2029079975 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.2709527306
Short name	T1043
Test name
Test status
Simulation time	21628379809 ps
CPU time	1103.29 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:42:11 PM PST 24
Peak memory	304136 kb
Host	smart-9a59f5ae-21a7-4be4-a40b-add371279e0f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2709527306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2709527306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.3308828627
Short name	T552
Test name
Test status
Simulation time	256949901607 ps
CPU time	4544.5 seconds
Started	Jan 03 01:23:30 PM PST 24
Finished	Jan 03 02:39:21 PM PST 24
Peak memory	653840 kb
Host	smart-fd403525-f6e2-47ec-8dd8-401c95338505
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3308828627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.3308828627 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.448877393
Short name	T716
Test name
Test status
Simulation time	193777380823 ps
CPU time	4859.27 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 02:44:36 PM PST 24
Peak memory	582596 kb
Host	smart-7725bbf8-0519-4f47-b3e1-144906bcde8a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=448877393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.448877393 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.931278523
Short name	T957
Test name
Test status
Simulation time	32896361 ps
CPU time	0.85 seconds
Started	Jan 03 01:24:13 PM PST 24
Finished	Jan 03 01:24:19 PM PST 24
Peak memory	219628 kb
Host	smart-0ddf5fc6-16be-49e4-8661-7ed306d4a6ce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931278523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.931278523 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.1778237177
Short name	T1011
Test name
Test status
Simulation time	4376673564 ps
CPU time	94.85 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:25:50 PM PST 24
Peak memory	233532 kb
Host	smart-2b20faca-e71d-4c7d-864f-c952aa6a505a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778237177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1778237177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.1442061211
Short name	T333
Test name
Test status
Simulation time	22370928706 ps
CPU time	221.15 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:27:40 PM PST 24
Peak memory	230324 kb
Host	smart-3839d0c3-5b31-49aa-8daa-168b04c5edde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442061211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1442061211 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.775382034
Short name	T530
Test name
Test status
Simulation time	35610242404 ps
CPU time	200.02 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 01:27:26 PM PST 24
Peak memory	244076 kb
Host	smart-19350573-bed4-43cc-9c2b-096aca0d9b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775382034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.775382034 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.4140328455
Short name	T635
Test name
Test status
Simulation time	83933803636 ps
CPU time	488.04 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 01:32:14 PM PST 24
Peak memory	274780 kb
Host	smart-1f875a1e-c64b-4633-87ca-f6dba1270db2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140328455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4140328455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.3099135481
Short name	T1130
Test name
Test status
Simulation time	4458275432 ps
CPU time	6.96 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:24:07 PM PST 24
Peak memory	218696 kb
Host	smart-996795db-5490-400a-b961-b6231e598212
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099135481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3099135481 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.1025149923
Short name	T829
Test name
Test status
Simulation time	69292434 ps
CPU time	1.37 seconds
Started	Jan 03 01:24:12 PM PST 24
Finished	Jan 03 01:24:18 PM PST 24
Peak memory	219912 kb
Host	smart-5d92d844-baf3-481a-b102-1638f0a81d7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025149923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1025149923 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.3470883625
Short name	T648
Test name
Test status
Simulation time	3821376308 ps
CPU time	96.63 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:25:39 PM PST 24
Peak memory	235584 kb
Host	smart-4955798d-09d1-4617-a37c-a1ba6378ff04
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470883625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.3470883625 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.990119727
Short name	T346
Test name
Test status
Simulation time	7398294578 ps
CPU time	112.65 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:25:51 PM PST 24
Peak memory	235860 kb
Host	smart-67c2630a-19b8-432f-8a2e-b9ed003ce122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990119727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.990119727 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.1613235884
Short name	T1047
Test name
Test status
Simulation time	1514844478 ps
CPU time	40.19 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:24:41 PM PST 24
Peak memory	226880 kb
Host	smart-af6e2a63-87f3-49b7-9a29-0540a33af716
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613235884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1613235884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.541376237
Short name	T665
Test name
Test status
Simulation time	41025020138 ps
CPU time	663.6 seconds
Started	Jan 03 01:23:52 PM PST 24
Finished	Jan 03 01:35:01 PM PST 24
Peak memory	309808 kb
Host	smart-5e75acce-ea81-4dc1-b155-28194c26bcee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=541376237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.541376237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.2971387532
Short name	T1087
Test name
Test status
Simulation time	114353417 ps
CPU time	5.68 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:24:21 PM PST 24
Peak memory	220176 kb
Host	smart-622da8d8-45b5-4697-8e1d-5f9b336e49d0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971387532 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.2971387532 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.3724915700
Short name	T388
Test name
Test status
Simulation time	1285610377 ps
CPU time	6.23 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:24:22 PM PST 24
Peak memory	218676 kb
Host	smart-ccfaf869-b8a9-4403-9c82-0f371a4df901
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724915700 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.3724915700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.929710090
Short name	T860
Test name
Test status
Simulation time	21369701340 ps
CPU time	1959.48 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:56:39 PM PST 24
Peak memory	403184 kb
Host	smart-945bef32-7814-4af0-8a23-35f732ca66fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=929710090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.929710090 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.4029756061
Short name	T293
Test name
Test status
Simulation time	112870395682 ps
CPU time	2032.64 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:57:45 PM PST 24
Peak memory	389008 kb
Host	smart-c0fc1990-70d0-4f21-98f0-c38fa4b2241a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4029756061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.4029756061 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.3877049464
Short name	T351
Test name
Test status
Simulation time	249027281547 ps
CPU time	1754.6 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:53:28 PM PST 24
Peak memory	346432 kb
Host	smart-7c66d9f9-ee2e-45c8-931c-a5f9630e0aee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3877049464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3877049464 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.948664076
Short name	T642
Test name
Test status
Simulation time	48270132148 ps
CPU time	1285.36 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:45:36 PM PST 24
Peak memory	299164 kb
Host	smart-a943f173-f77a-436f-b4a0-62da4061a424
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=948664076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.948664076 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.1999053163
Short name	T1048
Test name
Test status
Simulation time	682198875285 ps
CPU time	5545.79 seconds
Started	Jan 03 01:23:57 PM PST 24
Finished	Jan 03 02:56:29 PM PST 24
Peak memory	662468 kb
Host	smart-47bddc35-bb43-4622-aed0-6e63a954779d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1999053163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1999053163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.451907690
Short name	T577
Test name
Test status
Simulation time	1047301867490 ps
CPU time	4268.83 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 02:35:23 PM PST 24
Peak memory	567096 kb
Host	smart-2c04fb39-fe77-4196-8a78-f740e8629d17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=451907690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.451907690 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.2786045012
Short name	T595
Test name
Test status
Simulation time	17097741 ps
CPU time	0.9 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:23:49 PM PST 24
Peak memory	218552 kb
Host	smart-957a0bd9-adbe-492c-b11b-c81f46bb6037
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786045012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2786045012 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.3328314005
Short name	T479
Test name
Test status
Simulation time	1696008576 ps
CPU time	27.47 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:24:16 PM PST 24
Peak memory	234224 kb
Host	smart-4552b182-36f6-48b6-a5b7-b7d3a6a59fd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328314005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3328314005 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.3719954595
Short name	T932
Test name
Test status
Simulation time	23230939395 ps
CPU time	1175.43 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:44:38 PM PST 24
Peak memory	239744 kb
Host	smart-950423d2-b890-4b8f-bd36-6bf0ced905f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719954595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3719954595 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_error.3761127988
Short name	T691
Test name
Test status
Simulation time	5579405928 ps
CPU time	211.56 seconds
Started	Jan 03 01:23:33 PM PST 24
Finished	Jan 03 01:27:09 PM PST 24
Peak memory	253980 kb
Host	smart-9fcbf2aa-0535-4510-b946-7522122dd501
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761127988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3761127988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_key_error.3202595881
Short name	T951
Test name
Test status
Simulation time	2536470569 ps
CPU time	4.97 seconds
Started	Jan 03 01:23:31 PM PST 24
Finished	Jan 03 01:23:41 PM PST 24
Peak memory	218916 kb
Host	smart-4cfadebd-1f10-43b0-b90a-f370cfee4246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202595881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3202595881 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.777176439
Short name	T357
Test name
Test status
Simulation time	34504401 ps
CPU time	1.39 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:23:50 PM PST 24
Peak memory	220156 kb
Host	smart-fbdbbd9f-74a2-4ec8-9084-157ded8ea791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777176439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.777176439 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.4097295363
Short name	T179
Test name
Test status
Simulation time	39126377675 ps
CPU time	2019.44 seconds
Started	Jan 03 01:24:23 PM PST 24
Finished	Jan 03 01:58:05 PM PST 24
Peak memory	405904 kb
Host	smart-0912a6aa-d024-4894-a0c8-615e886b23f3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097295363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.4097295363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.3063610330
Short name	T1000
Test name
Test status
Simulation time	167385287622 ps
CPU time	319.64 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:30:22 PM PST 24
Peak memory	249428 kb
Host	smart-be654e82-241c-4900-8c31-d664c6c44385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063610330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3063610330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.2678362994
Short name	T640
Test name
Test status
Simulation time	14616859281 ps
CPU time	77.12 seconds
Started	Jan 03 01:24:31 PM PST 24
Finished	Jan 03 01:25:52 PM PST 24
Peak memory	226332 kb
Host	smart-1c98c83b-6fc6-4432-b508-e9eb2d9138cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678362994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2678362994 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.23204897
Short name	T464
Test name
Test status
Simulation time	30087700014 ps
CPU time	1097.07 seconds
Started	Jan 03 01:23:31 PM PST 24
Finished	Jan 03 01:41:54 PM PST 24
Peak memory	292748 kb
Host	smart-76fca879-6927-4d81-8827-4ce4e27d98f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=23204897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.23204897 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.1979871221
Short name	T198
Test name
Test status
Simulation time	2917180384 ps
CPU time	6.74 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:25:03 PM PST 24
Peak memory	218808 kb
Host	smart-aee45492-32e0-4259-988f-cd78d97756c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979871221 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.kmac_test_vectors_kmac.1979871221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2479906007
Short name	T717
Test name
Test status
Simulation time	238792473 ps
CPU time	5.14 seconds
Started	Jan 03 01:24:31 PM PST 24
Finished	Jan 03 01:24:40 PM PST 24
Peak memory	219632 kb
Host	smart-d76150ae-2f2b-4a44-9e1c-772972e3d5a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479906007 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2479906007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.2729594339
Short name	T744
Test name
Test status
Simulation time	64738603564 ps
CPU time	2074.75 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:59:27 PM PST 24
Peak memory	391544 kb
Host	smart-21352a43-91be-406f-b35c-69dfe6d98389
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2729594339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.2729594339 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.3258660106
Short name	T604
Test name
Test status
Simulation time	37413185902 ps
CPU time	1784.34 seconds
Started	Jan 03 01:24:21 PM PST 24
Finished	Jan 03 01:54:08 PM PST 24
Peak memory	392644 kb
Host	smart-84dded80-024d-40a2-9fe4-2da61687dcf2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3258660106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3258660106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.1244458288
Short name	T556
Test name
Test status
Simulation time	93703367390 ps
CPU time	1538.23 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:50:30 PM PST 24
Peak memory	339600 kb
Host	smart-6c9c9afd-3e7f-4444-80c7-ae883fb92b66
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1244458288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1244458288 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.2212899659
Short name	T499
Test name
Test status
Simulation time	13650182156 ps
CPU time	1101.44 seconds
Started	Jan 03 01:24:21 PM PST 24
Finished	Jan 03 01:42:45 PM PST 24
Peak memory	301348 kb
Host	smart-f2ca6bc2-e06f-41b2-8c2e-66afd61bcbf4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2212899659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2212899659 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.1418176079
Short name	T974
Test name
Test status
Simulation time	354641154321 ps
CPU time	5333.15 seconds
Started	Jan 03 01:24:48 PM PST 24
Finished	Jan 03 02:53:48 PM PST 24
Peak memory	655308 kb
Host	smart-fc00b5d2-1145-4d91-b6ed-b85cd910ae18
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1418176079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.1418176079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.3551235698
Short name	T184
Test name
Test status
Simulation time	220462792492 ps
CPU time	4464.37 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 02:39:16 PM PST 24
Peak memory	576304 kb
Host	smart-7405a0e1-ffd2-42fd-aa7c-10ba03e08a01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3551235698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3551235698 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.3332564831
Short name	T953
Test name
Test status
Simulation time	198676209 ps
CPU time	0.99 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:24:10 PM PST 24
Peak memory	218632 kb
Host	smart-363d5017-e098-400f-867a-8175b89a8885
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332564831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3332564831 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.3191286628
Short name	T835
Test name
Test status
Simulation time	15766640510 ps
CPU time	256.05 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:28:26 PM PST 24
Peak memory	245220 kb
Host	smart-48b49458-bd1d-4872-8757-522e3aa94fa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191286628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3191286628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.1386428429
Short name	T891
Test name
Test status
Simulation time	17841194491 ps
CPU time	902.44 seconds
Started	Jan 03 01:23:44 PM PST 24
Finished	Jan 03 01:38:52 PM PST 24
Peak memory	243304 kb
Host	smart-ad20a71e-2261-4c83-bfcc-89f51f7f6a3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386428429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1386428429 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.3704569794
Short name	T1030
Test name
Test status
Simulation time	31205494392 ps
CPU time	346.52 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:29:40 PM PST 24
Peak memory	253840 kb
Host	smart-095784a0-cd73-45a1-8f3e-4fb575425ba9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704569794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3704569794 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.855720653
Short name	T599
Test name
Test status
Simulation time	25116040213 ps
CPU time	405.1 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:30:43 PM PST 24
Peak memory	267884 kb
Host	smart-6e2b8b89-09b8-40a7-bbb9-7bcee0d7974e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855720653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.855720653 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.2913766603
Short name	T409
Test name
Test status
Simulation time	2014895163 ps
CPU time	3.66 seconds
Started	Jan 03 01:23:51 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	218696 kb
Host	smart-ef0a6f20-0313-4d82-914e-fa7ff46a8f9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913766603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2913766603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.305844390
Short name	T225
Test name
Test status
Simulation time	35494435 ps
CPU time	1.29 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:24:16 PM PST 24
Peak memory	218864 kb
Host	smart-2166841f-e624-4457-9f05-695de2c1d645
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305844390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.305844390 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.10915768
Short name	T495
Test name
Test status
Simulation time	319334602741 ps
CPU time	2036.83 seconds
Started	Jan 03 01:23:43 PM PST 24
Finished	Jan 03 01:57:46 PM PST 24
Peak memory	383008 kb
Host	smart-9792d6d7-993a-4d8f-ae22-4da61cea45bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and _output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and _output.10915768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.2694914088
Short name	T318
Test name
Test status
Simulation time	24593517328 ps
CPU time	281.02 seconds
Started	Jan 03 01:23:42 PM PST 24
Finished	Jan 03 01:28:28 PM PST 24
Peak memory	245652 kb
Host	smart-625fd73a-d868-4d76-9dd6-b365e9c3262a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694914088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2694914088 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.2533498697
Short name	T417
Test name
Test status
Simulation time	5488297984 ps
CPU time	87.17 seconds
Started	Jan 03 01:23:32 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	226952 kb
Host	smart-4d34bacf-640c-4ab4-8137-dd8f1d9aa54b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533498697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2533498697 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.800328675
Short name	T502
Test name
Test status
Simulation time	12967253367 ps
CPU time	100.94 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:25:41 PM PST 24
Peak memory	243500 kb
Host	smart-288da781-a514-4f7f-9ee5-cbf20304608e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=800328675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.800328675 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_stress_all_with_rand_reset.594473791
Short name	T862
Test name
Test status
Simulation time	726054147023 ps
CPU time	2372.53 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 02:03:38 PM PST 24
Peak memory	334784 kb
Host	smart-2c40ddea-aa64-42c8-8a03-71db61b43464
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=594473791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.594473791 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.478672835
Short name	T389
Test name
Test status
Simulation time	162204725 ps
CPU time	5.75 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	220292 kb
Host	smart-5c5fa8f1-5068-4080-be60-c4ba1a81a5fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478672835 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 33.kmac_test_vectors_kmac.478672835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.2222083889
Short name	T671
Test name
Test status
Simulation time	330754457 ps
CPU time	6.03 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:24:08 PM PST 24
Peak memory	220316 kb
Host	smart-bfaefa2f-8c23-4899-882c-6f38c39b31ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222083889 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.2222083889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.3592788808
Short name	T1079
Test name
Test status
Simulation time	141764730689 ps
CPU time	2129.24 seconds
Started	Jan 03 01:23:31 PM PST 24
Finished	Jan 03 01:59:06 PM PST 24
Peak memory	413348 kb
Host	smart-822f221f-af54-4bce-9e37-f7755aeb9ddd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3592788808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3592788808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.3128926890
Short name	T798
Test name
Test status
Simulation time	96297681023 ps
CPU time	2159.91 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:59:58 PM PST 24
Peak memory	383468 kb
Host	smart-4fa177a5-5901-40cf-97b8-28aeac140b70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3128926890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3128926890 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.2595143867
Short name	T257
Test name
Test status
Simulation time	336236758432 ps
CPU time	2005.46 seconds
Started	Jan 03 01:23:33 PM PST 24
Finished	Jan 03 01:57:03 PM PST 24
Peak memory	342484 kb
Host	smart-56623287-2460-443a-8cf5-bb55096f429a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2595143867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2595143867 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.959520415
Short name	T316
Test name
Test status
Simulation time	217585609395 ps
CPU time	1375.25 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:46:58 PM PST 24
Peak memory	305864 kb
Host	smart-212daba4-aacc-4a6b-8909-1f21d93fdf00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=959520415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.959520415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.3161021200
Short name	T607
Test name
Test status
Simulation time	202569583602 ps
CPU time	5379.63 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 02:53:33 PM PST 24
Peak memory	652088 kb
Host	smart-954d71cf-cd74-4b51-a978-fab62503a51a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3161021200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3161021200 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.2131481037
Short name	T492
Test name
Test status
Simulation time	53406499439 ps
CPU time	3960.68 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 02:30:02 PM PST 24
Peak memory	571616 kb
Host	smart-722a3548-7021-4f54-9558-9ad8c277c4b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2131481037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2131481037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.1449738353
Short name	T924
Test name
Test status
Simulation time	18094380 ps
CPU time	0.81 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	219756 kb
Host	smart-20b259da-a6a8-440f-82b5-5ca95a78e4cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449738353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1449738353 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.3319405719
Short name	T761
Test name
Test status
Simulation time	2134961541 ps
CPU time	46.25 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:55 PM PST 24
Peak memory	237264 kb
Host	smart-c9916b79-820c-4527-a58c-f35c0efff758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319405719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3319405719 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.3537212726
Short name	T99
Test name
Test status
Simulation time	5026210857 ps
CPU time	547.49 seconds
Started	Jan 03 01:24:02 PM PST 24
Finished	Jan 03 01:33:16 PM PST 24
Peak memory	234512 kb
Host	smart-517b5b2a-b13a-45e1-8121-ed10caea9afd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537212726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3537212726 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.596797789
Short name	T247
Test name
Test status
Simulation time	9441178625 ps
CPU time	181.87 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:26:56 PM PST 24
Peak memory	241600 kb
Host	smart-8f54da7e-d1f8-4d29-9a31-06956c952418
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596797789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.596797789 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.850749735
Short name	T814
Test name
Test status
Simulation time	18424006100 ps
CPU time	352.62 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:30:02 PM PST 24
Peak memory	267884 kb
Host	smart-74c80677-de35-4e82-a42c-be7942a2efcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850749735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.850749735 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.2250552832
Short name	T286
Test name
Test status
Simulation time	410559397 ps
CPU time	1.71 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:24:01 PM PST 24
Peak memory	218780 kb
Host	smart-600315e9-4e4b-42ba-8053-521341b1c8b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250552832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2250552832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.3625494102
Short name	T183
Test name
Test status
Simulation time	180923613 ps
CPU time	1.65 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:24:02 PM PST 24
Peak memory	219832 kb
Host	smart-17edb841-7f1e-4045-ab78-fefae9179529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625494102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3625494102 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.1737339902
Short name	T752
Test name
Test status
Simulation time	49015307535 ps
CPU time	907.4 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:39:58 PM PST 24
Peak memory	297580 kb
Host	smart-b84771d1-c8b1-481a-8090-6f8dd27f0f1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737339902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a nd_output.1737339902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.3852316271
Short name	T969
Test name
Test status
Simulation time	14939524598 ps
CPU time	164.07 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:26:58 PM PST 24
Peak memory	243204 kb
Host	smart-853f6a88-59bb-4967-97f5-8a88d6879480
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852316271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3852316271 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.276993306
Short name	T753
Test name
Test status
Simulation time	4288526588 ps
CPU time	92.63 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 01:25:59 PM PST 24
Peak memory	225568 kb
Host	smart-72c49de5-58d9-4da0-bae8-ae78e7217578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276993306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.276993306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.2038814667
Short name	T18
Test name
Test status
Simulation time	37509796606 ps
CPU time	752.2 seconds
Started	Jan 03 01:24:06 PM PST 24
Finished	Jan 03 01:36:44 PM PST 24
Peak memory	303524 kb
Host	smart-04e89b78-9ebd-431a-a1ca-485308a9ba75
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2038814667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2038814667 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.3654773716
Short name	T1042
Test name
Test status
Simulation time	363681441 ps
CPU time	7.09 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 01:24:05 PM PST 24
Peak memory	218856 kb
Host	smart-b0795c05-e00d-4f84-a7c4-979223d3bee0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654773716 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.3654773716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.689096715
Short name	T877
Test name
Test status
Simulation time	471337570 ps
CPU time	6.97 seconds
Started	Jan 03 01:24:06 PM PST 24
Finished	Jan 03 01:24:18 PM PST 24
Peak memory	218764 kb
Host	smart-6d5b1626-6701-4d81-b814-b3fc3e430b45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689096715 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 34.kmac_test_vectors_kmac_xof.689096715 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.638798705
Short name	T638
Test name
Test status
Simulation time	277885438358 ps
CPU time	2285.69 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 02:02:07 PM PST 24
Peak memory	403804 kb
Host	smart-7a5e1a5b-ef33-4810-baeb-f57f4c3027b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=638798705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.638798705 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.2993307645
Short name	T1128
Test name
Test status
Simulation time	189425987167 ps
CPU time	2257.4 seconds
Started	Jan 03 01:23:47 PM PST 24
Finished	Jan 03 02:01:29 PM PST 24
Peak memory	385280 kb
Host	smart-12f66bc3-e275-40e4-af5f-a5bc25980afa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2993307645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2993307645 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.3569704237
Short name	T1039
Test name
Test status
Simulation time	31922626725 ps
CPU time	1522.06 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:49:21 PM PST 24
Peak memory	338824 kb
Host	smart-e89e4328-0fe2-4573-8f65-6aaa3bb730a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3569704237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.3569704237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.1659783615
Short name	T205
Test name
Test status
Simulation time	10716170404 ps
CPU time	1135.37 seconds
Started	Jan 03 01:24:08 PM PST 24
Finished	Jan 03 01:43:10 PM PST 24
Peak memory	302736 kb
Host	smart-57688cd6-6bc6-47e4-bffe-1d1aa9bbfc56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1659783615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1659783615 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.3690443113
Short name	T508
Test name
Test status
Simulation time	242148200433 ps
CPU time	5002.92 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 02:47:33 PM PST 24
Peak memory	654336 kb
Host	smart-db066392-69d3-495d-a104-38990e5ec905
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3690443113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.3690443113 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.2959213163
Short name	T297
Test name
Test status
Simulation time	55262024676 ps
CPU time	4163.37 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 02:33:23 PM PST 24
Peak memory	574380 kb
Host	smart-07a30127-9767-48de-92c9-9919c2c5f901
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2959213163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2959213163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.3822364221
Short name	T244
Test name
Test status
Simulation time	128579131 ps
CPU time	0.86 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:24:11 PM PST 24
Peak memory	218444 kb
Host	smart-23533f7f-dba0-402f-a140-6feb72d291f6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822364221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3822364221 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.935320880
Short name	T1068
Test name
Test status
Simulation time	36234416396 ps
CPU time	425.08 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:30:58 PM PST 24
Peak memory	253912 kb
Host	smart-910cc92b-4d53-4c93-8992-a7d944847772
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935320880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.935320880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.3643893558
Short name	T1023
Test name
Test status
Simulation time	137629894346 ps
CPU time	1136.85 seconds
Started	Jan 03 01:23:51 PM PST 24
Finished	Jan 03 01:42:53 PM PST 24
Peak memory	240692 kb
Host	smart-7415f3b1-879b-4e97-9bd8-434ed6ca0f24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643893558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3643893558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.3877848733
Short name	T849
Test name
Test status
Simulation time	22448015413 ps
CPU time	324.57 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:29:24 PM PST 24
Peak memory	251928 kb
Host	smart-7143cb77-dce4-4f84-ac95-57b7a927da67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877848733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3877848733 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_key_error.3399662519
Short name	T1137
Test name
Test status
Simulation time	1856225141 ps
CPU time	5.48 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:14 PM PST 24
Peak memory	218576 kb
Host	smart-b440d6d1-832a-4cf8-91db-25d1f02d4e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399662519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3399662519 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.394469265
Short name	T486
Test name
Test status
Simulation time	58254488 ps
CPU time	1.39 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	219864 kb
Host	smart-6f41d9c6-f177-40e5-8496-34e89b22751c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394469265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.394469265 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.3944933628
Short name	T11
Test name
Test status
Simulation time	75136094302 ps
CPU time	2139.35 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:59:39 PM PST 24
Peak memory	418624 kb
Host	smart-c6946729-9533-45bd-aa6c-8b7d9eef2183
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944933628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.3944933628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.381654604
Short name	T1057
Test name
Test status
Simulation time	30532910873 ps
CPU time	474.25 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:31:54 PM PST 24
Peak memory	259304 kb
Host	smart-47c8fdc0-7817-4143-944d-b94c37e4df59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381654604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.381654604 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.2669472118
Short name	T306
Test name
Test status
Simulation time	928993029 ps
CPU time	30.25 seconds
Started	Jan 03 01:23:49 PM PST 24
Finished	Jan 03 01:24:23 PM PST 24
Peak memory	224016 kb
Host	smart-10f12d69-ec22-4e20-ae29-748e5fcfecfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669472118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2669472118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.1988194082
Short name	T807
Test name
Test status
Simulation time	9271081699 ps
CPU time	864.85 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:38:28 PM PST 24
Peak memory	311404 kb
Host	smart-d4e2b5f4-143c-4f44-98a4-1a6570674f09
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1988194082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1988194082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_stress_all_with_rand_reset.4025099589
Short name	T20
Test name
Test status
Simulation time	352416817475 ps
CPU time	1996.33 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 01:57:15 PM PST 24
Peak memory	353956 kb
Host	smart-50a66a77-417a-4500-b77e-be319ee78f61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4025099589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.4025099589 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.98997901
Short name	T695
Test name
Test status
Simulation time	420478369 ps
CPU time	6.53 seconds
Started	Jan 03 01:23:50 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	218788 kb
Host	smart-75ed335a-0a9c-4048-834f-0e26313931ec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98997901 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 35.kmac_test_vectors_kmac.98997901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.101848484
Short name	T408
Test name
Test status
Simulation time	455672631 ps
CPU time	5.74 seconds
Started	Jan 03 01:24:03 PM PST 24
Finished	Jan 03 01:24:14 PM PST 24
Peak memory	220172 kb
Host	smart-1a16d06e-aa53-44fb-b065-1bbf957dbdda
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101848484 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 35.kmac_test_vectors_kmac_xof.101848484 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.1628213676
Short name	T844
Test name
Test status
Simulation time	21156675068 ps
CPU time	1920.09 seconds
Started	Jan 03 01:23:55 PM PST 24
Finished	Jan 03 01:56:00 PM PST 24
Peak memory	399156 kb
Host	smart-54ffb681-6d8f-41b6-b549-47caa6733451
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1628213676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.1628213676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.1575181520
Short name	T1020
Test name
Test status
Simulation time	75942370355 ps
CPU time	1798.26 seconds
Started	Jan 03 01:23:48 PM PST 24
Finished	Jan 03 01:53:50 PM PST 24
Peak memory	387364 kb
Host	smart-71529356-40be-45c3-99dd-d3c2e26253bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1575181520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1575181520 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.364299557
Short name	T196
Test name
Test status
Simulation time	200210085968 ps
CPU time	1746.13 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:53:17 PM PST 24
Peak memory	345464 kb
Host	smart-1f0492bc-af48-40c2-ac0b-f505d366de25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=364299557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.364299557 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.54288563
Short name	T528
Test name
Test status
Simulation time	441724889354 ps
CPU time	1413.66 seconds
Started	Jan 03 01:24:04 PM PST 24
Finished	Jan 03 01:47:43 PM PST 24
Peak memory	300900 kb
Host	smart-3ddce6c7-81d3-4190-a3f9-7c32897fece3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=54288563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.54288563 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.85583725
Short name	T707
Test name
Test status
Simulation time	788910260646 ps
CPU time	5450.11 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 02:55:01 PM PST 24
Peak memory	674744 kb
Host	smart-7d735062-27ba-47a3-a1c4-1b99ea05a287
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=85583725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.85583725 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.700684973
Short name	T706
Test name
Test status
Simulation time	229255605139 ps
CPU time	4229.08 seconds
Started	Jan 03 01:23:53 PM PST 24
Finished	Jan 03 02:34:28 PM PST 24
Peak memory	568960 kb
Host	smart-0fba871f-1ff7-4774-81f6-99e4475cf3f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=700684973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.700684973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.3660788866
Short name	T820
Test name
Test status
Simulation time	35113321 ps
CPU time	0.84 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:31 PM PST 24
Peak memory	218592 kb
Host	smart-98cdbfb2-e077-4d3a-86ca-85dccb1ae3db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660788866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3660788866 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.83387984
Short name	T656
Test name
Test status
Simulation time	3952790140 ps
CPU time	116.43 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:26:57 PM PST 24
Peak memory	235556 kb
Host	smart-96e14160-b44c-46dd-8f64-1e2c439924a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83387984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.83387984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.2477929216
Short name	T803
Test name
Test status
Simulation time	8937072743 ps
CPU time	412.96 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:31:07 PM PST 24
Peak memory	241200 kb
Host	smart-f4775945-89ce-454a-a051-d1872d04beb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477929216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2477929216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.2279968288
Short name	T337
Test name
Test status
Simulation time	52384811332 ps
CPU time	260.31 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:28:49 PM PST 24
Peak memory	246824 kb
Host	smart-61b1a580-d8ca-46d3-9c43-7f90379c4dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279968288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2279968288 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.1791885988
Short name	T704
Test name
Test status
Simulation time	8393862527 ps
CPU time	332.72 seconds
Started	Jan 03 01:24:42 PM PST 24
Finished	Jan 03 01:30:19 PM PST 24
Peak memory	259704 kb
Host	smart-88c09c0c-7cae-424d-ab32-58f35aa96f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791885988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1791885988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.4131619815
Short name	T626
Test name
Test status
Simulation time	397908368 ps
CPU time	2.64 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:24:52 PM PST 24
Peak memory	218652 kb
Host	smart-7978b0fb-e960-435d-a3a0-3183a6394b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131619815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.4131619815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.3215216667
Short name	T283
Test name
Test status
Simulation time	171868973 ps
CPU time	1.43 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 01:24:30 PM PST 24
Peak memory	219796 kb
Host	smart-906a3f6d-c820-44fc-b1e9-71eca3e28804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215216667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3215216667 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.2837267633
Short name	T326
Test name
Test status
Simulation time	1562248306452 ps
CPU time	3199.56 seconds
Started	Jan 03 01:24:10 PM PST 24
Finished	Jan 03 02:17:36 PM PST 24
Peak memory	450300 kb
Host	smart-3dc8c641-458e-44a1-b3da-7b8ebe506881
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837267633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.2837267633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.1936295016
Short name	T906
Test name
Test status
Simulation time	2617371429 ps
CPU time	44.46 seconds
Started	Jan 03 01:24:00 PM PST 24
Finished	Jan 03 01:24:52 PM PST 24
Peak memory	242680 kb
Host	smart-24319a1e-949d-4f3e-8cf6-dc84571e9834
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936295016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1936295016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.1942189541
Short name	T946
Test name
Test status
Simulation time	104729792 ps
CPU time	4.55 seconds
Started	Jan 03 01:23:56 PM PST 24
Finished	Jan 03 01:24:06 PM PST 24
Peak memory	226960 kb
Host	smart-796c92b6-a9f5-41e6-bc14-b9c421e7912b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942189541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1942189541 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.985724176
Short name	T503
Test name
Test status
Simulation time	20100608237 ps
CPU time	707.92 seconds
Started	Jan 03 01:24:30 PM PST 24
Finished	Jan 03 01:36:21 PM PST 24
Peak memory	308204 kb
Host	smart-460d15e7-7e26-4c87-b46f-f446b922d97d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=985724176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.985724176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.31838416
Short name	T737
Test name
Test status
Simulation time	19902896578 ps
CPU time	1035.55 seconds
Started	Jan 03 01:24:29 PM PST 24
Finished	Jan 03 01:41:49 PM PST 24
Peak memory	321008 kb
Host	smart-356a6073-cc0a-44b2-8f67-57ce409e9879
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=31838416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.31838416 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.2370176212
Short name	T770
Test name
Test status
Simulation time	199643428 ps
CPU time	6.25 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:24:21 PM PST 24
Peak memory	218768 kb
Host	smart-a819cb27-e8ef-478c-8525-d5df714c4d87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370176212 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.2370176212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.689945884
Short name	T777
Test name
Test status
Simulation time	1125438250 ps
CPU time	6.54 seconds
Started	Jan 03 01:24:31 PM PST 24
Finished	Jan 03 01:24:41 PM PST 24
Peak memory	220304 kb
Host	smart-85ddeef0-b85f-4a7c-956b-ef4f8adf4ea3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689945884 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 36.kmac_test_vectors_kmac_xof.689945884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.2977950485
Short name	T750
Test name
Test status
Simulation time	143772456696 ps
CPU time	2333.27 seconds
Started	Jan 03 01:23:59 PM PST 24
Finished	Jan 03 02:03:00 PM PST 24
Peak memory	402612 kb
Host	smart-172a753a-f1e9-4b5c-8a14-39122b1a962b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2977950485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2977950485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.3000971170
Short name	T527
Test name
Test status
Simulation time	88178069137 ps
CPU time	2027.17 seconds
Started	Jan 03 01:24:05 PM PST 24
Finished	Jan 03 01:57:58 PM PST 24
Peak memory	383556 kb
Host	smart-0ca8c1dd-f5a0-45ae-8db5-250533360225
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3000971170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3000971170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.1877524676
Short name	T1004
Test name
Test status
Simulation time	285518846737 ps
CPU time	2039.32 seconds
Started	Jan 03 01:24:01 PM PST 24
Finished	Jan 03 01:58:07 PM PST 24
Peak memory	346372 kb
Host	smart-1119e763-a20b-48f4-914b-60c904c609e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1877524676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1877524676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.1352672801
Short name	T43
Test name
Test status
Simulation time	44165912315 ps
CPU time	1101.68 seconds
Started	Jan 03 01:24:09 PM PST 24
Finished	Jan 03 01:42:37 PM PST 24
Peak memory	299944 kb
Host	smart-3b6532c3-6a41-418e-90dd-d96084b4b3bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1352672801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1352672801 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.1433870163
Short name	T728
Test name
Test status
Simulation time	254437670215 ps
CPU time	5032.26 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 02:48:22 PM PST 24
Peak memory	659016 kb
Host	smart-665ffcfc-9e72-47d8-9f44-f35293ad83ff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1433870163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1433870163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.127382341
Short name	T733
Test name
Test status
Simulation time	162458939434 ps
CPU time	4553.39 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 02:40:22 PM PST 24
Peak memory	581684 kb
Host	smart-c4a83bb0-8b73-4043-9a39-d3a644ccdd19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=127382341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.127382341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.1362097180
Short name	T101
Test name
Test status
Simulation time	39022745 ps
CPU time	0.77 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 01:24:29 PM PST 24
Peak memory	219680 kb
Host	smart-b9ac0cb2-7414-4515-a021-236a71326fba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362097180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1362097180 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.1454675955
Short name	T471
Test name
Test status
Simulation time	1117688814 ps
CPU time	29.83 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 01:24:56 PM PST 24
Peak memory	227808 kb
Host	smart-61d501d5-b1d2-44c6-9dff-a8d36de6a85d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454675955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1454675955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.545179694
Short name	T353
Test name
Test status
Simulation time	54375898127 ps
CPU time	697.75 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:36:40 PM PST 24
Peak memory	243316 kb
Host	smart-8af291bf-0092-4291-b1dd-3019b2229d58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545179694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.545179694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.3596209142
Short name	T491
Test name
Test status
Simulation time	544278232 ps
CPU time	8.14 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:37 PM PST 24
Peak memory	225932 kb
Host	smart-15b5944a-efde-4ba1-82e6-252885408ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596209142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3596209142 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.2178634159
Short name	T1108
Test name
Test status
Simulation time	3060874743 ps
CPU time	58.63 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:25:57 PM PST 24
Peak memory	243272 kb
Host	smart-7e006c21-04b6-4f1b-9927-3a43ff3a03ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178634159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2178634159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.2852039160
Short name	T51
Test name
Test status
Simulation time	1409359126 ps
CPU time	4.82 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	218568 kb
Host	smart-17b1043d-0ecc-4029-9270-a6e9382fa055
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852039160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2852039160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.2023983655
Short name	T410
Test name
Test status
Simulation time	128599237 ps
CPU time	1.39 seconds
Started	Jan 03 01:24:21 PM PST 24
Finished	Jan 03 01:24:25 PM PST 24
Peak memory	219852 kb
Host	smart-8f1214d4-0367-4841-8105-fd889d3b2f86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023983655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2023983655 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.2138374256
Short name	T1065
Test name
Test status
Simulation time	492638440129 ps
CPU time	2156.82 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 02:00:34 PM PST 24
Peak memory	396964 kb
Host	smart-64cfe733-51d3-4d0a-8133-56599d2b8eec
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138374256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.2138374256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.3190439797
Short name	T313
Test name
Test status
Simulation time	123947490180 ps
CPU time	527.23 seconds
Started	Jan 03 01:24:35 PM PST 24
Finished	Jan 03 01:33:25 PM PST 24
Peak memory	258212 kb
Host	smart-eebb5254-404e-4b3a-b37a-e7df1ca99c75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190439797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3190439797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.827612130
Short name	T1017
Test name
Test status
Simulation time	8913887306 ps
CPU time	49.99 seconds
Started	Jan 03 01:24:30 PM PST 24
Finished	Jan 03 01:25:24 PM PST 24
Peak memory	227080 kb
Host	smart-8565922d-8b4b-49e2-a8cd-89888332eda4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827612130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.827612130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.1467510924
Short name	T630
Test name
Test status
Simulation time	31593092433 ps
CPU time	750.37 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:37:29 PM PST 24
Peak memory	323876 kb
Host	smart-b987d5b8-763c-4fbf-99ad-9ec5ba6906f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1467510924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1467510924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.504083311
Short name	T441
Test name
Test status
Simulation time	205407920 ps
CPU time	5.99 seconds
Started	Jan 03 01:24:24 PM PST 24
Finished	Jan 03 01:24:32 PM PST 24
Peak memory	220408 kb
Host	smart-4cc795fd-25a4-42f0-a2c3-844c44d00b67
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504083311 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.kmac_test_vectors_kmac.504083311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.1070825695
Short name	T268
Test name
Test status
Simulation time	889889989 ps
CPU time	6.37 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:24:58 PM PST 24
Peak memory	220280 kb
Host	smart-dbb21eee-4720-4348-a7f9-42aea30d9c6c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070825695 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.1070825695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.466074986
Short name	T973
Test name
Test status
Simulation time	256943205379 ps
CPU time	2225.16 seconds
Started	Jan 03 01:24:35 PM PST 24
Finished	Jan 03 02:01:43 PM PST 24
Peak memory	406252 kb
Host	smart-fd808022-08a2-42bc-a14c-11993bf1e6b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=466074986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.466074986 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.2164808168
Short name	T886
Test name
Test status
Simulation time	127439512646 ps
CPU time	1962.52 seconds
Started	Jan 03 01:24:30 PM PST 24
Finished	Jan 03 01:57:17 PM PST 24
Peak memory	391868 kb
Host	smart-00928d4a-3961-4aea-b615-3ddc883338d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2164808168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2164808168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.3666390444
Short name	T1050
Test name
Test status
Simulation time	119541490541 ps
CPU time	1678.69 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:52:59 PM PST 24
Peak memory	343604 kb
Host	smart-72e235b4-7ff0-44d3-b67e-1c863a4478ec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3666390444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3666390444 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.2927201605
Short name	T825
Test name
Test status
Simulation time	40681587849 ps
CPU time	1223.72 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:45:01 PM PST 24
Peak memory	301584 kb
Host	smart-a9f56243-49c7-4bf7-b953-3fb64556ccfc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2927201605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2927201605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.3476473047
Short name	T1026
Test name
Test status
Simulation time	950321825735 ps
CPU time	5616.55 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 02:58:28 PM PST 24
Peak memory	661456 kb
Host	smart-30afc4da-ec2c-4da9-ab7f-87eafab46587
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3476473047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3476473047 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.1618299166
Short name	T365
Test name
Test status
Simulation time	218232161540 ps
CPU time	4852.2 seconds
Started	Jan 03 01:24:23 PM PST 24
Finished	Jan 03 02:45:18 PM PST 24
Peak memory	548864 kb
Host	smart-25c4a927-9d87-4e12-bfe2-98915d1fa134
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1618299166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.1618299166 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.2031812836
Short name	T755
Test name
Test status
Simulation time	23653872 ps
CPU time	0.83 seconds
Started	Jan 03 01:24:20 PM PST 24
Finished	Jan 03 01:24:22 PM PST 24
Peak memory	218440 kb
Host	smart-06546c44-89af-4266-af68-5580c725049c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031812836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2031812836 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.3198863878
Short name	T215
Test name
Test status
Simulation time	3079452781 ps
CPU time	22.58 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:24:59 PM PST 24
Peak memory	232244 kb
Host	smart-a83a12c2-159b-450c-bd56-b01fbfaa6ea0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198863878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3198863878 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.1548741034
Short name	T845
Test name
Test status
Simulation time	15559934000 ps
CPU time	257.18 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:28:47 PM PST 24
Peak memory	230668 kb
Host	smart-65fed0c9-10f0-4f82-a1ae-d689bc6fe67a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548741034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1548741034 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.3832447203
Short name	T848
Test name
Test status
Simulation time	5810506605 ps
CPU time	137.59 seconds
Started	Jan 03 01:24:22 PM PST 24
Finished	Jan 03 01:26:41 PM PST 24
Peak memory	238288 kb
Host	smart-907b6419-a333-497f-ad98-dd0a33c67b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832447203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3832447203 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.2435546276
Short name	T382
Test name
Test status
Simulation time	8158855816 ps
CPU time	165.66 seconds
Started	Jan 03 01:24:20 PM PST 24
Finished	Jan 03 01:27:08 PM PST 24
Peak memory	258536 kb
Host	smart-47f1122e-eaf8-4d4f-8be7-f0d19c001ca1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435546276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2435546276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.1387130580
Short name	T797
Test name
Test status
Simulation time	465096077 ps
CPU time	2.08 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:31 PM PST 24
Peak memory	218604 kb
Host	smart-eb052669-038e-4af5-bf41-f48a818fcc09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387130580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1387130580 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.2127904397
Short name	T880
Test name
Test status
Simulation time	134397376 ps
CPU time	1.47 seconds
Started	Jan 03 01:24:29 PM PST 24
Finished	Jan 03 01:24:34 PM PST 24
Peak memory	219812 kb
Host	smart-0c84633f-a913-4e2f-adbb-24092cca7e0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127904397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2127904397 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.3969774787
Short name	T655
Test name
Test status
Simulation time	229699577723 ps
CPU time	3161.91 seconds
Started	Jan 03 01:24:20 PM PST 24
Finished	Jan 03 02:17:03 PM PST 24
Peak memory	452704 kb
Host	smart-cb8e58cd-8b65-4bcb-9958-02085430987e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969774787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.3969774787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.2006945631
Short name	T44
Test name
Test status
Simulation time	23542353573 ps
CPU time	486.41 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:33:07 PM PST 24
Peak memory	259408 kb
Host	smart-80a19c30-ec5b-4060-b484-4c950f4b286a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006945631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2006945631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.3298075426
Short name	T111
Test name
Test status
Simulation time	11831077307 ps
CPU time	42.41 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:25:35 PM PST 24
Peak memory	226932 kb
Host	smart-d9fd6621-e68a-4df4-8541-a4f766a1e4c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298075426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3298075426 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.2020927007
Short name	T813
Test name
Test status
Simulation time	73868843282 ps
CPU time	1282.69 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:46:00 PM PST 24
Peak memory	323092 kb
Host	smart-204b1e38-0ba7-451f-9b00-d5f1fd880bd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2020927007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2020927007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_stress_all_with_rand_reset.3708396127
Short name	T366
Test name
Test status
Simulation time	34093896766 ps
CPU time	354.3 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:30:23 PM PST 24
Peak memory	289052 kb
Host	smart-c350523e-32b4-440b-9973-408be626f2d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3708396127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.3708396127 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.665981024
Short name	T842
Test name
Test status
Simulation time	681863350 ps
CPU time	5.78 seconds
Started	Jan 03 01:24:43 PM PST 24
Finished	Jan 03 01:24:53 PM PST 24
Peak memory	218792 kb
Host	smart-85c0bbc4-cdef-47bc-82e5-ea1f1d1330bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665981024 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.kmac_test_vectors_kmac.665981024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2629514616
Short name	T781
Test name
Test status
Simulation time	244526551 ps
CPU time	5.63 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 01:24:33 PM PST 24
Peak memory	220020 kb
Host	smart-7d2b452b-974f-4694-9e8b-21f9bdfab8ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629514616 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2629514616 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.1680205621
Short name	T1060
Test name
Test status
Simulation time	21208219847 ps
CPU time	1991.46 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:58:11 PM PST 24
Peak memory	403428 kb
Host	smart-aa97ad48-f668-4ebe-9b94-aa1d96ed410c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1680205621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1680205621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.2565331468
Short name	T793
Test name
Test status
Simulation time	24257979944 ps
CPU time	1988.27 seconds
Started	Jan 03 01:24:43 PM PST 24
Finished	Jan 03 01:57:57 PM PST 24
Peak memory	388640 kb
Host	smart-f5a20006-e08b-4701-a80b-2bee3aaca1c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2565331468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2565331468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.693107905
Short name	T670
Test name
Test status
Simulation time	16719658657 ps
CPU time	1387.93 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:47:58 PM PST 24
Peak memory	336024 kb
Host	smart-2f867f6f-3689-44d8-a591-92d63ada979a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=693107905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.693107905 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.2397325771
Short name	T1092
Test name
Test status
Simulation time	20780855362 ps
CPU time	1208.62 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:45:06 PM PST 24
Peak memory	296504 kb
Host	smart-c81d73fc-8510-48bc-b2e8-078ab7b90ddf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2397325771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2397325771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.2758673936
Short name	T749
Test name
Test status
Simulation time	270276392218 ps
CPU time	4978.77 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 02:47:48 PM PST 24
Peak memory	669080 kb
Host	smart-0e0535d6-aa29-4461-9353-cb1438c6b33f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2758673936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.2758673936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.3563063544
Short name	T285
Test name
Test status
Simulation time	457365123398 ps
CPU time	5062.68 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 02:48:53 PM PST 24
Peak memory	569936 kb
Host	smart-bebd16f1-436f-4569-98c6-b7037e0a015a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3563063544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3563063544 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.2453741548
Short name	T940
Test name
Test status
Simulation time	18001884 ps
CPU time	0.82 seconds
Started	Jan 03 01:24:28 PM PST 24
Finished	Jan 03 01:24:32 PM PST 24
Peak memory	219720 kb
Host	smart-16af26aa-0a7c-4b57-962b-556c5188f5c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453741548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2453741548 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.2014454260
Short name	T161
Test name
Test status
Simulation time	6000698987 ps
CPU time	140.42 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:27:17 PM PST 24
Peak memory	239940 kb
Host	smart-1d450ac8-a970-48b2-ac3b-073679170dbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014454260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2014454260 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.3007140996
Short name	T913
Test name
Test status
Simulation time	48658765653 ps
CPU time	441.77 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:31:59 PM PST 24
Peak memory	241176 kb
Host	smart-12c45850-a092-4e82-abec-5f933d6b7ed6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007140996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3007140996 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.2069172874
Short name	T367
Test name
Test status
Simulation time	11435199977 ps
CPU time	203.37 seconds
Started	Jan 03 01:24:19 PM PST 24
Finished	Jan 03 01:27:44 PM PST 24
Peak memory	243332 kb
Host	smart-7ae93c9e-0018-48c3-9e67-862ed33f8c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069172874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2069172874 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.3936842356
Short name	T789
Test name
Test status
Simulation time	5870442780 ps
CPU time	75.68 seconds
Started	Jan 03 01:24:25 PM PST 24
Finished	Jan 03 01:25:43 PM PST 24
Peak memory	243392 kb
Host	smart-71128236-89ef-44c3-94f8-b20928d989ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936842356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3936842356 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.3373040677
Short name	T754
Test name
Test status
Simulation time	1866879488 ps
CPU time	2.63 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:32 PM PST 24
Peak memory	218716 kb
Host	smart-5a651a0b-7589-44da-85f0-08af43da8867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373040677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3373040677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.3276170083
Short name	T13
Test name
Test status
Simulation time	87548788 ps
CPU time	1.28 seconds
Started	Jan 03 01:24:28 PM PST 24
Finished	Jan 03 01:24:33 PM PST 24
Peak memory	220000 kb
Host	smart-244035b9-2c5e-4866-967e-5d18e54f4d27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276170083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3276170083 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.1002761597
Short name	T856
Test name
Test status
Simulation time	84543232822 ps
CPU time	636.49 seconds
Started	Jan 03 01:24:22 PM PST 24
Finished	Jan 03 01:35:00 PM PST 24
Peak memory	273932 kb
Host	smart-fef27fe1-07db-4e72-be57-2643ffb0afaa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002761597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.1002761597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.1602295333
Short name	T1093
Test name
Test status
Simulation time	131488929375 ps
CPU time	289.86 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:29:20 PM PST 24
Peak memory	246000 kb
Host	smart-b3b3cf44-6c02-43c9-aaba-907ca3416b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602295333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1602295333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.1575285304
Short name	T661
Test name
Test status
Simulation time	2746178116 ps
CPU time	50.34 seconds
Started	Jan 03 01:24:48 PM PST 24
Finished	Jan 03 01:25:45 PM PST 24
Peak memory	219836 kb
Host	smart-f9e4f8ce-be4b-4249-ae50-169bf3235430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575285304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1575285304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.3674726159
Short name	T739
Test name
Test status
Simulation time	34860192477 ps
CPU time	671.62 seconds
Started	Jan 03 01:24:30 PM PST 24
Finished	Jan 03 01:35:46 PM PST 24
Peak memory	300972 kb
Host	smart-72ac046f-7906-40f3-8bda-a3b01a0fbbce
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3674726159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3674726159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.3321673313
Short name	T855
Test name
Test status
Simulation time	401375197 ps
CPU time	6.46 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:24:36 PM PST 24
Peak memory	218828 kb
Host	smart-3aac6a2c-b72b-44eb-bbf0-8f70e4b3924a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321673313 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.3321673313 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2080546930
Short name	T178
Test name
Test status
Simulation time	948997362 ps
CPU time	6.63 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:24:44 PM PST 24
Peak memory	220300 kb
Host	smart-1350770b-d390-4655-81e2-4858ff4d7e55
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080546930 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2080546930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.278642533
Short name	T1129
Test name
Test status
Simulation time	70067559232 ps
CPU time	1957.17 seconds
Started	Jan 03 01:24:22 PM PST 24
Finished	Jan 03 01:57:01 PM PST 24
Peak memory	403620 kb
Host	smart-3d000c7d-a781-41b4-b41f-460e2fc752ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=278642533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.278642533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.750750325
Short name	T873
Test name
Test status
Simulation time	22305448305 ps
CPU time	1909.34 seconds
Started	Jan 03 01:24:26 PM PST 24
Finished	Jan 03 01:56:18 PM PST 24
Peak memory	393980 kb
Host	smart-f63d5447-2304-4ef3-98ef-ccb62827e5c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=750750325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.750750325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.2170594120
Short name	T29
Test name
Test status
Simulation time	67843985326 ps
CPU time	1561.89 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 01:50:52 PM PST 24
Peak memory	345736 kb
Host	smart-780eb76e-a5f6-4944-ba0d-7fef459609ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2170594120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2170594120 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.2237382530
Short name	T516
Test name
Test status
Simulation time	42359677169 ps
CPU time	1121.96 seconds
Started	Jan 03 01:24:48 PM PST 24
Finished	Jan 03 01:43:36 PM PST 24
Peak memory	299588 kb
Host	smart-2b2acadf-0233-484e-b5aa-be0e2bdb36fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2237382530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2237382530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.316258720
Short name	T919
Test name
Test status
Simulation time	878481334962 ps
CPU time	4128.61 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 02:33:18 PM PST 24
Peak memory	574228 kb
Host	smart-07da5166-1f47-4397-a0ef-d71bb6c07717
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=316258720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.316258720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.3409614317
Short name	T339
Test name
Test status
Simulation time	20954998 ps
CPU time	0.91 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	219752 kb
Host	smart-6f12b2ac-332c-441b-a68c-a6c4b68cc992
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409614317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3409614317 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.350830810
Short name	T784
Test name
Test status
Simulation time	2603598826 ps
CPU time	38.99 seconds
Started	Jan 03 01:20:07 PM PST 24
Finished	Jan 03 01:20:50 PM PST 24
Peak memory	227176 kb
Host	smart-b977360d-33b8-4514-a5ee-41816ad35b6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350830810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.350830810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.104828493
Short name	T819
Test name
Test status
Simulation time	10201994286 ps
CPU time	187.22 seconds
Started	Jan 03 01:20:28 PM PST 24
Finished	Jan 03 01:23:37 PM PST 24
Peak memory	243280 kb
Host	smart-711f7ecc-44a1-4ca9-9e1f-c4308feb1d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104828493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.104828493 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.4283578190
Short name	T334
Test name
Test status
Simulation time	110267759716 ps
CPU time	1152.99 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:39:04 PM PST 24
Peak memory	243384 kb
Host	smart-6356bd08-77bc-4f4c-a117-ae5fe537475e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283578190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.4283578190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.1268648304
Short name	T204
Test name
Test status
Simulation time	612115805 ps
CPU time	20.41 seconds
Started	Jan 03 01:20:30 PM PST 24
Finished	Jan 03 01:20:54 PM PST 24
Peak memory	224880 kb
Host	smart-8e6d08c3-2e6d-4c3b-9fca-8c579c864bd0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1268648304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1268648304 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.1442222938
Short name	T1064
Test name
Test status
Simulation time	1526559367 ps
CPU time	19.53 seconds
Started	Jan 03 01:20:07 PM PST 24
Finished	Jan 03 01:20:31 PM PST 24
Peak memory	219908 kb
Host	smart-52265cdd-8650-4f63-bc67-8bcc25bd796e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442222938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1442222938 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.3227538218
Short name	T678
Test name
Test status
Simulation time	29066836339 ps
CPU time	80.2 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 01:21:15 PM PST 24
Peak memory	232544 kb
Host	smart-279f8b68-5976-43f7-b09c-60f0a1fe0983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227538218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3227538218 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.1304367010
Short name	T1119
Test name
Test status
Simulation time	5564698916 ps
CPU time	34.21 seconds
Started	Jan 03 01:19:55 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	238728 kb
Host	smart-5415605c-76a5-4e53-b987-d02048917451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304367010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1304367010 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.4184700965
Short name	T476
Test name
Test status
Simulation time	344707664 ps
CPU time	2.43 seconds
Started	Jan 03 01:20:13 PM PST 24
Finished	Jan 03 01:20:19 PM PST 24
Peak memory	218332 kb
Host	smart-541900a3-c770-414b-ac7c-7b4d3584c39e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184700965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.4184700965 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.3175740371
Short name	T546
Test name
Test status
Simulation time	233582569 ps
CPU time	1.65 seconds
Started	Jan 03 01:20:06 PM PST 24
Finished	Jan 03 01:20:13 PM PST 24
Peak memory	219868 kb
Host	smart-1a86ae81-980f-4ed2-86cd-2fd3504734a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175740371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3175740371 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.3462963947
Short name	T1015
Test name
Test status
Simulation time	82594160192 ps
CPU time	582.41 seconds
Started	Jan 03 01:19:45 PM PST 24
Finished	Jan 03 01:29:34 PM PST 24
Peak memory	269728 kb
Host	smart-da8f2b36-0805-4415-8cc0-1b66d6eb9e0c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462963947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.3462963947 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.464296202
Short name	T589
Test name
Test status
Simulation time	12307638500 ps
CPU time	191.17 seconds
Started	Jan 03 01:20:10 PM PST 24
Finished	Jan 03 01:23:26 PM PST 24
Peak memory	243196 kb
Host	smart-1d01dec6-d9b3-4aa4-bbaa-666923007a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464296202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.464296202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.71194383
Short name	T98
Test name
Test status
Simulation time	29583012581 ps
CPU time	118.7 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:22:34 PM PST 24
Peak memory	296044 kb
Host	smart-6228e392-314d-473e-9f3e-1c0da282c0a4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71194383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.71194383 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/default/4.kmac_sideload.4120846586
Short name	T968
Test name
Test status
Simulation time	4612981676 ps
CPU time	172.14 seconds
Started	Jan 03 01:19:43 PM PST 24
Finished	Jan 03 01:22:41 PM PST 24
Peak memory	241044 kb
Host	smart-7ed652d1-53bd-4872-9958-887b7990e4b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120846586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.4120846586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.1856788730
Short name	T748
Test name
Test status
Simulation time	1964919725 ps
CPU time	40.74 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:20:31 PM PST 24
Peak memory	218712 kb
Host	smart-f756cc8f-00eb-4b52-9a55-5f71f0d2d9df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856788730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1856788730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.4065827269
Short name	T518
Test name
Test status
Simulation time	49802640559 ps
CPU time	1421.26 seconds
Started	Jan 03 01:20:10 PM PST 24
Finished	Jan 03 01:43:56 PM PST 24
Peak memory	340400 kb
Host	smart-d4518ade-3c31-4129-8644-b19b24c8de6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4065827269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.4065827269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.3854826500
Short name	T195
Test name
Test status
Simulation time	7363768465 ps
CPU time	6.58 seconds
Started	Jan 03 01:19:52 PM PST 24
Finished	Jan 03 01:20:06 PM PST 24
Peak memory	218816 kb
Host	smart-a70cf895-52df-4091-b640-bc936b633ff7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854826500 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.3854826500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2102964960
Short name	T1069
Test name
Test status
Simulation time	252533566 ps
CPU time	6.18 seconds
Started	Jan 03 01:20:13 PM PST 24
Finished	Jan 03 01:20:23 PM PST 24
Peak memory	219944 kb
Host	smart-cc72d1d7-748a-42cc-ab3b-f51c38527ad2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102964960 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2102964960 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.1714276956
Short name	T967
Test name
Test status
Simulation time	66784836797 ps
CPU time	2294.17 seconds
Started	Jan 03 01:19:50 PM PST 24
Finished	Jan 03 01:58:11 PM PST 24
Peak memory	404208 kb
Host	smart-208c2bec-8963-429a-b5ea-77221b9abe89
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1714276956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1714276956 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.3752225655
Short name	T206
Test name
Test status
Simulation time	38809641786 ps
CPU time	1908.54 seconds
Started	Jan 03 01:19:41 PM PST 24
Finished	Jan 03 01:51:35 PM PST 24
Peak memory	386272 kb
Host	smart-e8f35f2f-897b-4db4-bae3-3068409c54a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3752225655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3752225655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.1864728937
Short name	T424
Test name
Test status
Simulation time	61787636139 ps
CPU time	1570.5 seconds
Started	Jan 03 01:20:06 PM PST 24
Finished	Jan 03 01:46:22 PM PST 24
Peak memory	348396 kb
Host	smart-5e9792f5-7865-45cc-8a9d-c548e09684e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1864728937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1864728937 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.3860070045
Short name	T746
Test name
Test status
Simulation time	15677711666 ps
CPU time	1140.5 seconds
Started	Jan 03 01:19:47 PM PST 24
Finished	Jan 03 01:38:53 PM PST 24
Peak memory	303084 kb
Host	smart-579a183b-f0d6-4fbc-964f-d91698206420
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3860070045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3860070045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.3943273652
Short name	T541
Test name
Test status
Simulation time	669494403280 ps
CPU time	5321.96 seconds
Started	Jan 03 01:19:52 PM PST 24
Finished	Jan 03 02:48:41 PM PST 24
Peak memory	663336 kb
Host	smart-3d39c44c-a100-43a5-b5fa-5c26861757f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3943273652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3943273652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.325935363
Short name	T380
Test name
Test status
Simulation time	152616661566 ps
CPU time	4903.64 seconds
Started	Jan 03 01:20:06 PM PST 24
Finished	Jan 03 02:41:55 PM PST 24
Peak memory	584120 kb
Host	smart-de642421-a349-4499-8316-bb8bd35bd6fc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=325935363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.325935363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.3855047015
Short name	T481
Test name
Test status
Simulation time	44811877 ps
CPU time	0.82 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:21 PM PST 24
Peak memory	218672 kb
Host	smart-b682ad68-8ac0-4ed6-9b0d-0ecf098cd85d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855047015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3855047015 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.4078762328
Short name	T726
Test name
Test status
Simulation time	1173328127 ps
CPU time	62.18 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:26:29 PM PST 24
Peak memory	229912 kb
Host	smart-7716044d-2941-43b0-b0ec-be8777154d2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078762328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.4078762328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.996126031
Short name	T1037
Test name
Test status
Simulation time	21157371617 ps
CPU time	1677.34 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:52:35 PM PST 24
Peak memory	240968 kb
Host	smart-0a26ba44-8ec6-4a2c-b997-b837df641064
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996126031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.996126031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.2989540021
Short name	T462
Test name
Test status
Simulation time	7364456357 ps
CPU time	265.63 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:29:42 PM PST 24
Peak memory	249356 kb
Host	smart-985ff5a0-c248-47ea-8c26-2624ee9cc7eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989540021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2989540021 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.1104317426
Short name	T493
Test name
Test status
Simulation time	4734930037 ps
CPU time	74.94 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:26:19 PM PST 24
Peak memory	241880 kb
Host	smart-4156a232-f195-4ac7-83e5-f72a911c4fb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104317426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1104317426 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.927200255
Short name	T1112
Test name
Test status
Simulation time	3925828705 ps
CPU time	5.46 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:25:27 PM PST 24
Peak memory	218736 kb
Host	smart-96d21731-114c-4220-b37d-a9f5e0a727bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927200255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.927200255 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.487000640
Short name	T875
Test name
Test status
Simulation time	113370007 ps
CPU time	3.73 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:23 PM PST 24
Peak memory	222804 kb
Host	smart-19f04c61-fe14-42d0-930b-e7a545a42aa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487000640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.487000640 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.3686699094
Short name	T899
Test name
Test status
Simulation time	145024274949 ps
CPU time	1257.75 seconds
Started	Jan 03 01:24:29 PM PST 24
Finished	Jan 03 01:45:30 PM PST 24
Peak memory	328836 kb
Host	smart-2eda7170-e3d2-4d66-ad7f-d3714069b487
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686699094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a nd_output.3686699094 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.2983537787
Short name	T5
Test name
Test status
Simulation time	5506728780 ps
CPU time	456.08 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:32:37 PM PST 24
Peak memory	258932 kb
Host	smart-d7616996-6828-44f2-b69b-d30e0b07fabc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983537787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2983537787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.1587402941
Short name	T488
Test name
Test status
Simulation time	654740691 ps
CPU time	22.89 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:25:25 PM PST 24
Peak memory	226944 kb
Host	smart-ea2f3ae0-5124-4806-bccb-993ae9ed0ea2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587402941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1587402941 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.3959015272
Short name	T21
Test name
Test status
Simulation time	39000759670 ps
CPU time	1011.71 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:41:56 PM PST 24
Peak memory	347576 kb
Host	smart-1c58b2de-2797-4aa8-a8ee-bb1a5e3f3a82
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3959015272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3959015272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.1812233008
Short name	T114
Test name
Test status
Simulation time	27950891326 ps
CPU time	257.09 seconds
Started	Jan 03 01:25:01 PM PST 24
Finished	Jan 03 01:29:31 PM PST 24
Peak memory	251572 kb
Host	smart-30f24b68-3251-4110-9c2c-36bce58a963b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1812233008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.1812233008 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.60995547
Short name	T1091
Test name
Test status
Simulation time	123568228 ps
CPU time	6.33 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:27 PM PST 24
Peak memory	218888 kb
Host	smart-8f6317e8-ca4f-43ec-b206-fd49feff6724
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60995547 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 40.kmac_test_vectors_kmac.60995547 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1715190846
Short name	T364
Test name
Test status
Simulation time	1624637488 ps
CPU time	5.58 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:25:03 PM PST 24
Peak memory	218752 kb
Host	smart-4c58f15c-abbf-4e81-9e0d-48320a35eab9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715190846 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1715190846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.3900636721
Short name	T548
Test name
Test status
Simulation time	82066623965 ps
CPU time	2001.46 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:58:24 PM PST 24
Peak memory	403132 kb
Host	smart-db2a71d0-971d-41e0-afec-f0b14ba118c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3900636721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3900636721 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.2854741608
Short name	T383
Test name
Test status
Simulation time	65106458474 ps
CPU time	2012.27 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:58:31 PM PST 24
Peak memory	391896 kb
Host	smart-24ef6f93-8d60-4892-bfe0-9b9446bce1d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2854741608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2854741608 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.2828717446
Short name	T785
Test name
Test status
Simulation time	189090842023 ps
CPU time	1676.61 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:52:56 PM PST 24
Peak memory	339680 kb
Host	smart-3a7f2c41-f8d6-4962-8914-33d9f5365578
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2828717446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2828717446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.1024415974
Short name	T439
Test name
Test status
Simulation time	61589128435 ps
CPU time	1467.08 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:49:04 PM PST 24
Peak memory	307916 kb
Host	smart-fb57a7f9-09cb-4652-b990-a1eb6c91ac03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1024415974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1024415974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.1657869101
Short name	T422
Test name
Test status
Simulation time	393169888742 ps
CPU time	5568.38 seconds
Started	Jan 03 01:24:55 PM PST 24
Finished	Jan 03 02:57:56 PM PST 24
Peak memory	654816 kb
Host	smart-e1df174c-b7a0-4431-9e43-2c725b12dafe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1657869101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1657869101 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.1713901853
Short name	T727
Test name
Test status
Simulation time	224078951497 ps
CPU time	4726.99 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 02:43:47 PM PST 24
Peak memory	570508 kb
Host	smart-a642aba1-59ea-4c86-832d-13ea30051e4f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1713901853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1713901853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.851823005
Short name	T894
Test name
Test status
Simulation time	35101441 ps
CPU time	0.86 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:25:00 PM PST 24
Peak memory	219712 kb
Host	smart-1b34a111-f4f9-482a-b5c2-4c820b14ef5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851823005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.851823005 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.2202623908
Short name	T928
Test name
Test status
Simulation time	48899181164 ps
CPU time	330.27 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:30:53 PM PST 24
Peak memory	251624 kb
Host	smart-a5549311-a8c5-4dc3-ae03-6711fffc9596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202623908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2202623908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.3532580862
Short name	T1007
Test name
Test status
Simulation time	9432818779 ps
CPU time	323.47 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:30:42 PM PST 24
Peak memory	242540 kb
Host	smart-447146c3-8c5d-468c-9c0e-8ff8207cf397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532580862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3532580862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.1498033932
Short name	T190
Test name
Test status
Simulation time	60862208699 ps
CPU time	322.43 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:30:50 PM PST 24
Peak memory	250300 kb
Host	smart-8670d835-d41c-4fe7-9ef0-a3b354ee4599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498033932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1498033932 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.4052384031
Short name	T1052
Test name
Test status
Simulation time	20871622631 ps
CPU time	135.46 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:27:43 PM PST 24
Peak memory	252576 kb
Host	smart-aabd8d24-7a12-4cb9-927e-06db99502716
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052384031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.4052384031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.977741413
Short name	T846
Test name
Test status
Simulation time	8546448971 ps
CPU time	3.5 seconds
Started	Jan 03 01:25:11 PM PST 24
Finished	Jan 03 01:25:33 PM PST 24
Peak memory	218752 kb
Host	smart-31e912b6-1eab-4c51-9631-3139e908a2e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977741413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.977741413 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.964846634
Short name	T857
Test name
Test status
Simulation time	128380101 ps
CPU time	1.26 seconds
Started	Jan 03 01:25:12 PM PST 24
Finished	Jan 03 01:25:32 PM PST 24
Peak memory	219752 kb
Host	smart-e99de995-45f9-4f70-a16a-9621d184b462
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964846634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.964846634 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.2352146882
Short name	T419
Test name
Test status
Simulation time	33563248212 ps
CPU time	1761.5 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:54:39 PM PST 24
Peak memory	382708 kb
Host	smart-3c73007a-49fa-48f6-b1c8-38e4e72bdfe7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352146882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.2352146882 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.1489277848
Short name	T396
Test name
Test status
Simulation time	135137523 ps
CPU time	10.19 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:25:37 PM PST 24
Peak memory	221512 kb
Host	smart-bdec75ec-dad1-46c4-90ca-adf2ebe7ab70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489277848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1489277848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.3049853678
Short name	T217
Test name
Test status
Simulation time	2230151662 ps
CPU time	45.6 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:26:08 PM PST 24
Peak memory	226848 kb
Host	smart-829ac3c1-a2be-4de4-84e6-51f1c32a719a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049853678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3049853678 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.1524462244
Short name	T404
Test name
Test status
Simulation time	223190257112 ps
CPU time	1609.32 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:51:52 PM PST 24
Peak memory	354792 kb
Host	smart-726a6216-927f-419f-bb26-85b5284c6d0f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1524462244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1524462244 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/41.kmac_stress_all_with_rand_reset.2858146316
Short name	T421
Test name
Test status
Simulation time	173614386191 ps
CPU time	629.98 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:35:20 PM PST 24
Peak memory	291872 kb
Host	smart-92cb05b9-fcaa-47d2-ad9e-73381be71889
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2858146316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.2858146316 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.2369858699
Short name	T1013
Test name
Test status
Simulation time	102306575 ps
CPU time	5.56 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:25:27 PM PST 24
Peak memory	218804 kb
Host	smart-8ded1b21-2ed7-436d-88fd-83aeb2ed64cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369858699 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.2369858699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.329556168
Short name	T779
Test name
Test status
Simulation time	553134942 ps
CPU time	6.84 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:26 PM PST 24
Peak memory	220068 kb
Host	smart-6cc89aea-a47a-4ca5-b1d5-ee22e52b91b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329556168 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 41.kmac_test_vectors_kmac_xof.329556168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.2352882454
Short name	T524
Test name
Test status
Simulation time	1350261479869 ps
CPU time	2764.79 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 02:11:24 PM PST 24
Peak memory	409896 kb
Host	smart-a27b92e5-28eb-4a82-b6eb-e4d34960f79e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2352882454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2352882454 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.186479761
Short name	T228
Test name
Test status
Simulation time	34902588601 ps
CPU time	1867.79 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:56:33 PM PST 24
Peak memory	391144 kb
Host	smart-705c6818-91f1-4b6b-beab-92c141f320db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=186479761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.186479761 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.4183577103
Short name	T406
Test name
Test status
Simulation time	148719992321 ps
CPU time	1735.91 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:54:17 PM PST 24
Peak memory	342076 kb
Host	smart-33918d6c-ee74-4c4d-b083-ae6a245b7426
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4183577103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.4183577103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.199628277
Short name	T658
Test name
Test status
Simulation time	101140290716 ps
CPU time	1374.37 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:48:19 PM PST 24
Peak memory	303620 kb
Host	smart-95d17b1d-ed30-406f-b6c2-5d38a17648ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=199628277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.199628277 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.242024238
Short name	T988
Test name
Test status
Simulation time	671624130888 ps
CPU time	5072.29 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 02:49:56 PM PST 24
Peak memory	657948 kb
Host	smart-b768ae17-2367-4a6a-a055-38b88b58b732
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=242024238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.242024238 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.2206783813
Short name	T390
Test name
Test status
Simulation time	73745465789 ps
CPU time	4209.19 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 02:35:32 PM PST 24
Peak memory	582708 kb
Host	smart-7aa8f7c4-10e0-4946-ac56-5e984d736fbc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2206783813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2206783813 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.1522087371
Short name	T219
Test name
Test status
Simulation time	42691281 ps
CPU time	0.83 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:24:53 PM PST 24
Peak memory	219716 kb
Host	smart-4c16e92e-7281-4327-b334-7c398264da6a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522087371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1522087371 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.696642665
Short name	T731
Test name
Test status
Simulation time	16030241151 ps
CPU time	357.31 seconds
Started	Jan 03 01:24:29 PM PST 24
Finished	Jan 03 01:30:31 PM PST 24
Peak memory	254548 kb
Host	smart-a9ccf4d6-6901-40c2-83e7-ff8bbff6d739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696642665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.696642665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.189633713
Short name	T398
Test name
Test status
Simulation time	1256331276 ps
CPU time	119.1 seconds
Started	Jan 03 01:24:29 PM PST 24
Finished	Jan 03 01:26:31 PM PST 24
Peak memory	242256 kb
Host	smart-c6a6b8c1-afb0-4f97-91dd-18f105dc4aec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189633713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.189633713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.3158437373
Short name	T274
Test name
Test status
Simulation time	718038835 ps
CPU time	18.22 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:25:09 PM PST 24
Peak memory	224996 kb
Host	smart-70cb1e6b-069b-4d8e-a66f-6eb0e7af1e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158437373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3158437373 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_key_error.250464087
Short name	T50
Test name
Test status
Simulation time	2905721095 ps
CPU time	4.66 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:25:07 PM PST 24
Peak memory	218700 kb
Host	smart-60f37aaf-64bb-43b7-8d1c-f1193d476acb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250464087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.250464087 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.2328011975
Short name	T947
Test name
Test status
Simulation time	31816887 ps
CPU time	1.4 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:24:51 PM PST 24
Peak memory	220264 kb
Host	smart-508ab8f0-7583-4e52-acea-616ddd02a2f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328011975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2328011975 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.3326391456
Short name	T1114
Test name
Test status
Simulation time	63500143976 ps
CPU time	1559.93 seconds
Started	Jan 03 01:24:20 PM PST 24
Finished	Jan 03 01:50:22 PM PST 24
Peak memory	362892 kb
Host	smart-118b8085-4161-472a-8e21-9f4594bd360a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326391456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.3326391456 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.3726828200
Short name	T917
Test name
Test status
Simulation time	1485934377 ps
CPU time	114.68 seconds
Started	Jan 03 01:24:30 PM PST 24
Finished	Jan 03 01:26:28 PM PST 24
Peak memory	234812 kb
Host	smart-bf91b57c-d362-4a4d-9513-f895ab0ec307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726828200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3726828200 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.1740941665
Short name	T201
Test name
Test status
Simulation time	3868978954 ps
CPU time	28.08 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:25:18 PM PST 24
Peak memory	224136 kb
Host	smart-fbe2efb7-f26a-442c-8654-58f8c2da3316
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740941665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1740941665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.37216306
Short name	T19
Test name
Test status
Simulation time	37609811105 ps
CPU time	1177.67 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:45:05 PM PST 24
Peak memory	357884 kb
Host	smart-89c87eaa-b231-4f53-8b97-2da228dc846b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=37216306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.37216306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.30382234
Short name	T327
Test name
Test status
Simulation time	196122800 ps
CPU time	6.18 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:24:59 PM PST 24
Peak memory	218776 kb
Host	smart-30f2a6e3-1bec-4cbb-94dd-12812b7dbb51
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382234 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 42.kmac_test_vectors_kmac.30382234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.3581801092
Short name	T253
Test name
Test status
Simulation time	272146650 ps
CPU time	6.94 seconds
Started	Jan 03 01:24:35 PM PST 24
Finished	Jan 03 01:24:45 PM PST 24
Peak memory	218868 kb
Host	smart-10246599-5f79-4e3f-b593-c3662507093f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581801092 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.3581801092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.2104158300
Short name	T941
Test name
Test status
Simulation time	20469982809 ps
CPU time	1933.89 seconds
Started	Jan 03 01:24:27 PM PST 24
Finished	Jan 03 01:56:44 PM PST 24
Peak memory	395844 kb
Host	smart-af097ba5-859b-429b-b487-294be10dbf7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2104158300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2104158300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.3366498478
Short name	T1127
Test name
Test status
Simulation time	162109308522 ps
CPU time	1746.64 seconds
Started	Jan 03 01:24:25 PM PST 24
Finished	Jan 03 01:53:34 PM PST 24
Peak memory	384636 kb
Host	smart-52a9f540-bede-4b85-bbb5-4928940432f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3366498478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3366498478 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.255078568
Short name	T436
Test name
Test status
Simulation time	54456382861 ps
CPU time	1649.44 seconds
Started	Jan 03 01:24:22 PM PST 24
Finished	Jan 03 01:51:53 PM PST 24
Peak memory	333756 kb
Host	smart-1bc1a798-cf57-4cc5-8948-a449f5f9fdbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=255078568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.255078568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.922561219
Short name	T965
Test name
Test status
Simulation time	145512082764 ps
CPU time	1306.27 seconds
Started	Jan 03 01:24:34 PM PST 24
Finished	Jan 03 01:46:23 PM PST 24
Peak memory	301000 kb
Host	smart-e5d1de29-5145-46a7-81ff-d89bbfcfaeae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=922561219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.922561219 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.2462800907
Short name	T709
Test name
Test status
Simulation time	188995809160 ps
CPU time	5403.24 seconds
Started	Jan 03 01:24:43 PM PST 24
Finished	Jan 03 02:54:51 PM PST 24
Peak memory	664860 kb
Host	smart-9a901c37-26e8-4fba-ad2a-7945a17cb992
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2462800907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.2462800907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.2075633971
Short name	T475
Test name
Test status
Simulation time	677755388332 ps
CPU time	4062.56 seconds
Started	Jan 03 01:24:22 PM PST 24
Finished	Jan 03 02:32:07 PM PST 24
Peak memory	572000 kb
Host	smart-03b51ff1-8c8c-4c08-83e6-9c0d03a4f0d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2075633971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2075633971 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.483441874
Short name	T632
Test name
Test status
Simulation time	64363629 ps
CPU time	0.83 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:20 PM PST 24
Peak memory	219744 kb
Host	smart-1cafcc68-cd59-4a83-8f20-d52ec68c37a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483441874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.483441874 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.3116104261
Short name	T560
Test name
Test status
Simulation time	43720429213 ps
CPU time	231.96 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:29:08 PM PST 24
Peak memory	246184 kb
Host	smart-1f538045-5c19-4167-a66d-3108e5ba2d44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116104261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3116104261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.563583592
Short name	T264
Test name
Test status
Simulation time	9559716457 ps
CPU time	873.99 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:39:25 PM PST 24
Peak memory	238244 kb
Host	smart-9ecfa670-e02f-4930-843e-c0368852e230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563583592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.563583592 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.3692740893
Short name	T391
Test name
Test status
Simulation time	5804539760 ps
CPU time	306.95 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:30:27 PM PST 24
Peak memory	250284 kb
Host	smart-53f8bc5f-6dbf-4b88-af22-5322616010d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692740893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3692740893 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.3166347603
Short name	T555
Test name
Test status
Simulation time	15717012691 ps
CPU time	387.87 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:31:55 PM PST 24
Peak memory	267928 kb
Host	smart-8e870066-2beb-4381-a9e3-7137a903e90e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166347603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3166347603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.4073700314
Short name	T596
Test name
Test status
Simulation time	481093022 ps
CPU time	3.28 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:22 PM PST 24
Peak memory	218712 kb
Host	smart-4f406e8b-7f79-4f56-8a33-3bec2511cb47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073700314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.4073700314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.2372406366
Short name	T10
Test name
Test status
Simulation time	61403565 ps
CPU time	1.54 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:25:18 PM PST 24
Peak memory	219872 kb
Host	smart-096f6a06-8cb7-41cf-9a26-b7f81902fe63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372406366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2372406366 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.1678837769
Short name	T937
Test name
Test status
Simulation time	173364967887 ps
CPU time	2277.66 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 02:02:49 PM PST 24
Peak memory	394444 kb
Host	smart-801887cf-e249-4d18-84a5-7b15577904b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678837769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.1678837769 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.2700404271
Short name	T336
Test name
Test status
Simulation time	3598161100 ps
CPU time	121.54 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:26:54 PM PST 24
Peak memory	234744 kb
Host	smart-a2432511-124f-44e3-9666-7fcc28cbda5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700404271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2700404271 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.3040370790
Short name	T597
Test name
Test status
Simulation time	1307284660 ps
CPU time	17.36 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:25:07 PM PST 24
Peak memory	226976 kb
Host	smart-8ab3c065-dbc2-4f5b-aa3c-5422f32e928b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040370790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3040370790 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.757537986
Short name	T847
Test name
Test status
Simulation time	358437444350 ps
CPU time	2378.23 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 02:04:59 PM PST 24
Peak memory	464712 kb
Host	smart-691463cf-4d36-4f6c-ac73-22a130b53b1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=757537986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.757537986 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_stress_all_with_rand_reset.105515043
Short name	T559
Test name
Test status
Simulation time	178852230746 ps
CPU time	2074.01 seconds
Started	Jan 03 01:25:10 PM PST 24
Finished	Jan 03 02:00:03 PM PST 24
Peak memory	378508 kb
Host	smart-70269674-b681-4b09-87b0-716bc3665bb3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=105515043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.105515043 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.1149950192
Short name	T1053
Test name
Test status
Simulation time	948313172 ps
CPU time	6.55 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:25:07 PM PST 24
Peak memory	218876 kb
Host	smart-0a233d31-3df1-41a2-9ce9-d00faf174cc2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149950192 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.1149950192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1004842434
Short name	T498
Test name
Test status
Simulation time	403074958 ps
CPU time	6.06 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:25:11 PM PST 24
Peak memory	218692 kb
Host	smart-36fceef9-3445-4005-86d6-3012bbb4f2b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004842434 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1004842434 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.3694283364
Short name	T790
Test name
Test status
Simulation time	85737874965 ps
CPU time	2284.64 seconds
Started	Jan 03 01:24:56 PM PST 24
Finished	Jan 03 02:03:13 PM PST 24
Peak memory	388660 kb
Host	smart-19eaa04a-a6e5-4092-b26b-86883061d906
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3694283364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3694283364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.2176193553
Short name	T320
Test name
Test status
Simulation time	19697955491 ps
CPU time	1957.94 seconds
Started	Jan 03 01:24:54 PM PST 24
Finished	Jan 03 01:57:44 PM PST 24
Peak memory	384080 kb
Host	smart-28c6eeba-4e21-45a7-9d2b-4865feff17fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2176193553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2176193553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.2452055092
Short name	T1071
Test name
Test status
Simulation time	48401908514 ps
CPU time	1496.13 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:49:57 PM PST 24
Peak memory	345256 kb
Host	smart-cdda1cf6-4ac0-42a5-a2f7-5d39424b73bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2452055092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2452055092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.2398840908
Short name	T362
Test name
Test status
Simulation time	111885199218 ps
CPU time	1330.66 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:47:04 PM PST 24
Peak memory	302312 kb
Host	smart-b39dec92-fd5c-4ea0-860b-36f8f55d5bad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2398840908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2398840908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.4080460717
Short name	T575
Test name
Test status
Simulation time	348678252337 ps
CPU time	5155.69 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 02:50:59 PM PST 24
Peak memory	639884 kb
Host	smart-32e625f8-34fe-4dd9-b7ca-abc2e1983f3c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4080460717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.4080460717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.1282505111
Short name	T617
Test name
Test status
Simulation time	53298444406 ps
CPU time	4251.09 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 02:35:56 PM PST 24
Peak memory	573952 kb
Host	smart-1d65bebe-bfc2-4a36-a657-2134df3f9431
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1282505111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1282505111 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.3059699801
Short name	T792
Test name
Test status
Simulation time	15274627 ps
CPU time	0.82 seconds
Started	Jan 03 01:25:18 PM PST 24
Finished	Jan 03 01:25:41 PM PST 24
Peak memory	218548 kb
Host	smart-6b465eba-a82d-4746-bc91-97bf4eadfb12
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059699801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3059699801 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.244258015
Short name	T309
Test name
Test status
Simulation time	2671642897 ps
CPU time	122.76 seconds
Started	Jan 03 01:25:12 PM PST 24
Finished	Jan 03 01:27:34 PM PST 24
Peak memory	237816 kb
Host	smart-df3da816-4e25-400b-93b6-b783f6fddc45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244258015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.244258015 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.1427806293
Short name	T456
Test name
Test status
Simulation time	94568876714 ps
CPU time	878.28 seconds
Started	Jan 03 01:25:10 PM PST 24
Finished	Jan 03 01:40:07 PM PST 24
Peak memory	242140 kb
Host	smart-d3a62469-9310-495c-8c14-0701efc9297f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427806293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1427806293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.30370438
Short name	T80
Test name
Test status
Simulation time	49256458964 ps
CPU time	78.67 seconds
Started	Jan 03 01:25:19 PM PST 24
Finished	Jan 03 01:27:00 PM PST 24
Peak memory	233440 kb
Host	smart-d9977104-99f7-48bf-8c45-4890fbe58ca0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30370438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.30370438 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.3085835306
Short name	T578
Test name
Test status
Simulation time	489721034 ps
CPU time	14.78 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:25:42 PM PST 24
Peak memory	233728 kb
Host	smart-18dbea23-52d9-4cef-8b17-572134adb07e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085835306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3085835306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.3094093619
Short name	T668
Test name
Test status
Simulation time	495429072 ps
CPU time	1.72 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:25:29 PM PST 24
Peak memory	218396 kb
Host	smart-43a05708-14f1-4cfd-962a-5a3af95cadd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094093619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3094093619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.4215159228
Short name	T558
Test name
Test status
Simulation time	183176393 ps
CPU time	1.44 seconds
Started	Jan 03 01:25:18 PM PST 24
Finished	Jan 03 01:25:42 PM PST 24
Peak memory	218816 kb
Host	smart-2ef0916e-12be-4c9e-8954-3b241c7a5bf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215159228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4215159228 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.709314058
Short name	T294
Test name
Test status
Simulation time	124687672168 ps
CPU time	535.41 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:34:22 PM PST 24
Peak memory	268048 kb
Host	smart-1bbb338c-c788-48d8-988f-78483d976315
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709314058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an d_output.709314058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.1618152645
Short name	T786
Test name
Test status
Simulation time	11599706346 ps
CPU time	369.6 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:31:32 PM PST 24
Peak memory	252996 kb
Host	smart-e57decd9-04e7-4d21-9928-8466d961b951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618152645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1618152645 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.3680372744
Short name	T1063
Test name
Test status
Simulation time	2579437449 ps
CPU time	59.28 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:26:25 PM PST 24
Peak memory	222904 kb
Host	smart-e7218cda-91a8-4d32-b3c5-32dd16b26cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680372744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3680372744 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.1116771183
Short name	T500
Test name
Test status
Simulation time	84138284676 ps
CPU time	313.79 seconds
Started	Jan 03 01:25:16 PM PST 24
Finished	Jan 03 01:30:52 PM PST 24
Peak memory	242536 kb
Host	smart-57e0b1b6-035a-4e0c-a454-a75b99ac50a5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1116771183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1116771183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.3261797076
Short name	T1126
Test name
Test status
Simulation time	104116153 ps
CPU time	5.08 seconds
Started	Jan 03 01:25:13 PM PST 24
Finished	Jan 03 01:25:38 PM PST 24
Peak memory	218820 kb
Host	smart-fef08c6d-4331-4b10-83e5-ef47bd2f3a42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261797076 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.kmac_test_vectors_kmac.3261797076 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1374693921
Short name	T249
Test name
Test status
Simulation time	1546943545 ps
CPU time	6.34 seconds
Started	Jan 03 01:25:19 PM PST 24
Finished	Jan 03 01:25:48 PM PST 24
Peak memory	220224 kb
Host	smart-d1ef5df9-c80e-42c5-84a8-48657ae06210
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374693921 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1374693921 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.4272785351
Short name	T561
Test name
Test status
Simulation time	143324099596 ps
CPU time	1930.51 seconds
Started	Jan 03 01:25:11 PM PST 24
Finished	Jan 03 01:57:40 PM PST 24
Peak memory	395272 kb
Host	smart-4b04b37b-54ce-4ebe-977d-82c3ac194dcd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4272785351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.4272785351 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.2890118720
Short name	T452
Test name
Test status
Simulation time	63908055053 ps
CPU time	2093.23 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 02:00:15 PM PST 24
Peak memory	383516 kb
Host	smart-197e9795-e341-465e-8b1b-bdd0dbd91bf6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2890118720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2890118720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.990306335
Short name	T824
Test name
Test status
Simulation time	113327395821 ps
CPU time	1744.61 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:54:23 PM PST 24
Peak memory	342272 kb
Host	smart-a371240f-4c6f-4c9a-8fcd-d6f82b7536bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=990306335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.990306335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.900685199
Short name	T1084
Test name
Test status
Simulation time	69954684673 ps
CPU time	1238.83 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:45:59 PM PST 24
Peak memory	303600 kb
Host	smart-a94209d1-d2dc-4171-9bf0-445091ec4dea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=900685199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.900685199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.3911382463
Short name	T1131
Test name
Test status
Simulation time	61175145675 ps
CPU time	5191.36 seconds
Started	Jan 03 01:25:13 PM PST 24
Finished	Jan 03 02:52:04 PM PST 24
Peak memory	647532 kb
Host	smart-61673469-5243-49d6-b1e7-9d5e3ec98215
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3911382463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3911382463 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.2100039297
Short name	T273
Test name
Test status
Simulation time	1395609045402 ps
CPU time	4912.02 seconds
Started	Jan 03 01:25:16 PM PST 24
Finished	Jan 03 02:47:30 PM PST 24
Peak memory	577996 kb
Host	smart-b89192f3-3ed9-461c-a307-0303a22979a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2100039297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2100039297 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.1062238811
Short name	T100
Test name
Test status
Simulation time	17717264 ps
CPU time	0.84 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:24:51 PM PST 24
Peak memory	219680 kb
Host	smart-fbcb6db9-611e-4d10-a4dd-a78705b9cddc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062238811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1062238811 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.2431949270
Short name	T159
Test name
Test status
Simulation time	15237602266 ps
CPU time	104.69 seconds
Started	Jan 03 01:24:54 PM PST 24
Finished	Jan 03 01:26:50 PM PST 24
Peak memory	237180 kb
Host	smart-e22ec161-b158-48e0-a433-425bc100837c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431949270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2431949270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.520218941
Short name	T697
Test name
Test status
Simulation time	8400874308 ps
CPU time	750.7 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:37:50 PM PST 24
Peak memory	243304 kb
Host	smart-1e06efb3-3904-4527-bf43-c9e543219d26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520218941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.520218941 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.1641964441
Short name	T42
Test name
Test status
Simulation time	395971234 ps
CPU time	1.52 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	218480 kb
Host	smart-2197d191-3d57-4ec7-b23d-ef30e0702229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641964441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1641964441 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.3142194163
Short name	T714
Test name
Test status
Simulation time	65296747929 ps
CPU time	455.06 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:32:32 PM PST 24
Peak memory	275920 kb
Host	smart-034f5c9b-dd19-41b4-bffd-ecf8c003e41f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142194163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3142194163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.3478742626
Short name	T564
Test name
Test status
Simulation time	922050378 ps
CPU time	1.97 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:24:52 PM PST 24
Peak memory	218760 kb
Host	smart-75b31a27-7da4-4970-ab35-9028b6c13445
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478742626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3478742626 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.539930580
Short name	T933
Test name
Test status
Simulation time	158657021 ps
CPU time	1.81 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:24:54 PM PST 24
Peak memory	220544 kb
Host	smart-fbfdee55-f04f-4e22-87ed-d173f83d3761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539930580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.539930580 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.3305164370
Short name	T1116
Test name
Test status
Simulation time	32377582660 ps
CPU time	851.18 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:39:01 PM PST 24
Peak memory	298924 kb
Host	smart-b1b9ff42-3f17-4245-8ed6-05d049789a08
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305164370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.3305164370 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.3237912525
Short name	T288
Test name
Test status
Simulation time	18805684780 ps
CPU time	381.2 seconds
Started	Jan 03 01:25:18 PM PST 24
Finished	Jan 03 01:32:01 PM PST 24
Peak memory	252676 kb
Host	smart-ebcff226-7887-4592-b6ab-4f7a256afe78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237912525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3237912525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.1489300545
Short name	T769
Test name
Test status
Simulation time	10845209057 ps
CPU time	68.7 seconds
Started	Jan 03 01:25:19 PM PST 24
Finished	Jan 03 01:26:50 PM PST 24
Peak memory	224676 kb
Host	smart-c3ab197b-8abb-4c3a-a327-62d1ede2fdec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489300545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1489300545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.3609026203
Short name	T415
Test name
Test status
Simulation time	8558024324 ps
CPU time	129.4 seconds
Started	Jan 03 01:24:55 PM PST 24
Finished	Jan 03 01:27:17 PM PST 24
Peak memory	251708 kb
Host	smart-1ddc58b4-53fa-44a8-8116-d7ce20380ea2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3609026203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3609026203 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.4156253627
Short name	T356
Test name
Test status
Simulation time	46515724134 ps
CPU time	471.59 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:32:56 PM PST 24
Peak memory	270148 kb
Host	smart-750b97e3-9fab-42fd-9a53-915b10b67b9f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4156253627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.4156253627 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.2203473333
Short name	T539
Test name
Test status
Simulation time	245783142 ps
CPU time	5.95 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:25:08 PM PST 24
Peak memory	220280 kb
Host	smart-d3b431d8-fe10-4dea-b41b-323ee747a3ba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203473333 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.2203473333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1506531830
Short name	T1019
Test name
Test status
Simulation time	234061206 ps
CPU time	6.51 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 01:24:56 PM PST 24
Peak memory	220200 kb
Host	smart-10a43331-f8ed-433b-8d40-f10fd5bd837a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506531830 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1506531830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.2220943028
Short name	T193
Test name
Test status
Simulation time	20851197236 ps
CPU time	1901.83 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:56:34 PM PST 24
Peak memory	392308 kb
Host	smart-e30005e3-f51f-4712-b0de-a517d49689c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2220943028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2220943028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.3963867187
Short name	T1105
Test name
Test status
Simulation time	39057763251 ps
CPU time	1813.69 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:55:05 PM PST 24
Peak memory	385796 kb
Host	smart-654b5917-0145-4b98-9533-d540fc6a9b9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3963867187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3963867187 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.393453707
Short name	T270
Test name
Test status
Simulation time	125763905422 ps
CPU time	1755.47 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:54:06 PM PST 24
Peak memory	342432 kb
Host	smart-dfe93452-832e-4d27-bfad-1d8fe6d54225
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=393453707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.393453707 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.1313046083
Short name	T385
Test name
Test status
Simulation time	34796614473 ps
CPU time	1304.29 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:46:45 PM PST 24
Peak memory	303320 kb
Host	smart-ee526827-cb00-4c82-963c-29239cc1791d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1313046083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1313046083 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.1635595090
Short name	T262
Test name
Test status
Simulation time	251346461261 ps
CPU time	4930.66 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 02:47:00 PM PST 24
Peak memory	649224 kb
Host	smart-700f7789-5545-4d52-9c7b-5a358ba2cd35
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1635595090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1635595090 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.3433684662
Short name	T1103
Test name
Test status
Simulation time	56718221636 ps
CPU time	4065.14 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 02:32:47 PM PST 24
Peak memory	574124 kb
Host	smart-86c565b7-c890-4f2a-b60a-77cca3f2c54e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3433684662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3433684662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.1837507500
Short name	T751
Test name
Test status
Simulation time	105961041 ps
CPU time	0.82 seconds
Started	Jan 03 01:25:12 PM PST 24
Finished	Jan 03 01:25:33 PM PST 24
Peak memory	218472 kb
Host	smart-e278d02d-6299-4785-b66e-d0c788a26929
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837507500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1837507500 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.3523335221
Short name	T520
Test name
Test status
Simulation time	875777518 ps
CPU time	45.98 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:26:03 PM PST 24
Peak memory	228960 kb
Host	smart-9d74a834-4066-4c98-b5f5-5eee0d158c25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523335221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3523335221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.522943747
Short name	T113
Test name
Test status
Simulation time	55877892148 ps
CPU time	1339.22 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:47:38 PM PST 24
Peak memory	239620 kb
Host	smart-30bb6091-0311-4ef7-b717-f7009a5d42fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522943747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.522943747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.3841229218
Short name	T41
Test name
Test status
Simulation time	6966903026 ps
CPU time	229.77 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:29:10 PM PST 24
Peak memory	246808 kb
Host	smart-e42653c1-3514-4877-b837-2c063201578f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841229218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3841229218 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.1667539142
Short name	T987
Test name
Test status
Simulation time	854984413 ps
CPU time	62.08 seconds
Started	Jan 03 01:25:11 PM PST 24
Finished	Jan 03 01:26:32 PM PST 24
Peak memory	243240 kb
Host	smart-738c5e3c-3e45-4e9d-a3b9-4b17d2652a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667539142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1667539142 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.4106411199
Short name	T449
Test name
Test status
Simulation time	1229318169 ps
CPU time	7.25 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:25:26 PM PST 24
Peak memory	218716 kb
Host	smart-b6ecbdf3-858f-4c6e-9dc1-391c072a3c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106411199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.4106411199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.1623754949
Short name	T732
Test name
Test status
Simulation time	111417070 ps
CPU time	1.35 seconds
Started	Jan 03 01:25:13 PM PST 24
Finished	Jan 03 01:25:35 PM PST 24
Peak memory	219840 kb
Host	smart-8f7a59cb-18e2-423d-bc5a-b4f98db7add2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623754949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1623754949 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.3106844601
Short name	T1075
Test name
Test status
Simulation time	206357330509 ps
CPU time	1365 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:48:03 PM PST 24
Peak memory	324952 kb
Host	smart-cc628e3d-ec97-443e-8ce9-30e993510b79
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106844601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.3106844601 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.3162078859
Short name	T644
Test name
Test status
Simulation time	18616114057 ps
CPU time	448.05 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:32:49 PM PST 24
Peak memory	253388 kb
Host	smart-e75dbdb3-81de-4ce7-b560-8c11d7fac7d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162078859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3162078859 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.410718424
Short name	T771
Test name
Test status
Simulation time	1727293250 ps
CPU time	9.76 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:25:14 PM PST 24
Peak memory	224128 kb
Host	smart-8dd15655-d165-455a-a0e3-fa7d06214d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410718424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.410718424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.1083655567
Short name	T23
Test name
Test status
Simulation time	68187133290 ps
CPU time	921.82 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:40:47 PM PST 24
Peak memory	302264 kb
Host	smart-ea345423-900d-4ec9-973c-6b3c74ae9bea
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1083655567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1083655567 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.1817352970
Short name	T760
Test name
Test status
Simulation time	721797939 ps
CPU time	5.82 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:26 PM PST 24
Peak memory	218844 kb
Host	smart-9e062acb-a55c-4677-8f9d-e21cc676c9bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817352970 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.1817352970 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.803129351
Short name	T317
Test name
Test status
Simulation time	204784417 ps
CPU time	5.87 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:25:29 PM PST 24
Peak memory	220184 kb
Host	smart-c3f17e0c-6177-4daf-a644-262ca41e764f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803129351 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 46.kmac_test_vectors_kmac_xof.803129351 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.1069150164
Short name	T1081
Test name
Test status
Simulation time	269829314402 ps
CPU time	2343.59 seconds
Started	Jan 03 01:24:55 PM PST 24
Finished	Jan 03 02:04:11 PM PST 24
Peak memory	396292 kb
Host	smart-d98e6675-ee35-49bb-a3cc-7df5efd3199c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1069150164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1069150164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.217718659
Short name	T669
Test name
Test status
Simulation time	80568910200 ps
CPU time	1826.24 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:55:47 PM PST 24
Peak memory	391792 kb
Host	smart-4c67f0b1-fa77-474c-83cb-d0b03f46e800
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=217718659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.217718659 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.1655781714
Short name	T279
Test name
Test status
Simulation time	48016657328 ps
CPU time	1707.4 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:53:55 PM PST 24
Peak memory	333656 kb
Host	smart-6ac6bed0-d1bb-406f-a2dd-b99f85b00e73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1655781714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1655781714 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.1003104565
Short name	T885
Test name
Test status
Simulation time	10918858037 ps
CPU time	1152.07 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:44:35 PM PST 24
Peak memory	305372 kb
Host	smart-dabd0dc2-c9fe-4e99-b4fa-dfafd1df8266
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1003104565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1003104565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.2897519295
Short name	T531
Test name
Test status
Simulation time	1541797497229 ps
CPU time	6213.47 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 03:08:54 PM PST 24
Peak memory	651896 kb
Host	smart-e39cd396-69c8-4b4b-8261-7d3c8d5d1f51
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2897519295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2897519295 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.4085542961
Short name	T654
Test name
Test status
Simulation time	310945633269 ps
CPU time	4782.85 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 02:45:03 PM PST 24
Peak memory	567448 kb
Host	smart-206febe2-6ba3-4afd-8ced-e94bfc7b06ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4085542961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.4085542961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.1701795815
Short name	T102
Test name
Test status
Simulation time	31164809 ps
CPU time	0.87 seconds
Started	Jan 03 01:24:54 PM PST 24
Finished	Jan 03 01:25:06 PM PST 24
Peak memory	219788 kb
Host	smart-9eb58b43-50e2-4dae-9a15-0ca8610faeb6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701795815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1701795815 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.298455470
Short name	T710
Test name
Test status
Simulation time	4202303663 ps
CPU time	240.19 seconds
Started	Jan 03 01:25:17 PM PST 24
Finished	Jan 03 01:29:39 PM PST 24
Peak memory	248232 kb
Host	smart-a88ab830-cc97-4f09-9088-e219b9b92760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298455470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.298455470 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.2405909874
Short name	T467
Test name
Test status
Simulation time	138702319788 ps
CPU time	1034.13 seconds
Started	Jan 03 01:25:09 PM PST 24
Finished	Jan 03 01:42:41 PM PST 24
Peak memory	243364 kb
Host	smart-a7dc6a65-a87f-4c44-8c16-84741479d69f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405909874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2405909874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.2865975450
Short name	T725
Test name
Test status
Simulation time	48424688413 ps
CPU time	109.68 seconds
Started	Jan 03 01:24:46 PM PST 24
Finished	Jan 03 01:26:40 PM PST 24
Peak memory	235276 kb
Host	smart-177eae67-8b32-45dd-aeed-26d1c48e0af0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865975450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2865975450 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.3877382093
Short name	T506
Test name
Test status
Simulation time	12624075536 ps
CPU time	168.96 seconds
Started	Jan 03 01:24:49 PM PST 24
Finished	Jan 03 01:27:46 PM PST 24
Peak memory	251556 kb
Host	smart-d5da3c43-efe5-42ad-8e11-5b130ef5ff9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877382093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3877382093 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.3764413973
Short name	T463
Test name
Test status
Simulation time	467023006 ps
CPU time	1.19 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	218452 kb
Host	smart-5c7cf722-9add-4768-8e1b-711cf2b28070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764413973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3764413973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.117876092
Short name	T241
Test name
Test status
Simulation time	230219277 ps
CPU time	1.39 seconds
Started	Jan 03 01:24:47 PM PST 24
Finished	Jan 03 01:24:54 PM PST 24
Peak memory	219972 kb
Host	smart-a991970b-6c81-466d-b808-e76a2d2598b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117876092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.117876092 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.3668206574
Short name	T646
Test name
Test status
Simulation time	23337580870 ps
CPU time	2279.26 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 02:03:24 PM PST 24
Peak memory	436724 kb
Host	smart-2ac12cce-5dc8-4d22-9f5e-04cedae6a3fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668206574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.3668206574 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.2943267172
Short name	T742
Test name
Test status
Simulation time	884384913 ps
CPU time	20.2 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:39 PM PST 24
Peak memory	223332 kb
Host	smart-7916ab8f-3221-4aab-9d32-144899c36b85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943267172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2943267172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.290531590
Short name	T1120
Test name
Test status
Simulation time	2181949419 ps
CPU time	45.96 seconds
Started	Jan 03 01:25:13 PM PST 24
Finished	Jan 03 01:26:18 PM PST 24
Peak memory	224920 kb
Host	smart-1a09c2cd-2417-4c66-8e7a-59d628e88ec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290531590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.290531590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.2552831495
Short name	T160
Test name
Test status
Simulation time	5831972898 ps
CPU time	542.23 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:33:52 PM PST 24
Peak memory	259352 kb
Host	smart-13ffbaab-3b20-4106-9fb8-179af9b8d114
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2552831495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2552831495 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_stress_all_with_rand_reset.3387556663
Short name	T929
Test name
Test status
Simulation time	23638772885 ps
CPU time	510.04 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:33:33 PM PST 24
Peak memory	264836 kb
Host	smart-9ca92d80-1c10-4fba-8bfa-941ae142a54d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3387556663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all_with_rand_reset.3387556663 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.2208187540
Short name	T1051
Test name
Test status
Simulation time	291088528 ps
CPU time	5.53 seconds
Started	Jan 03 01:25:18 PM PST 24
Finished	Jan 03 01:25:46 PM PST 24
Peak memory	218856 kb
Host	smart-0fe2bba3-898b-45c2-b027-e308914df6b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208187540 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.2208187540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.565378889
Short name	T592
Test name
Test status
Simulation time	1022583258 ps
CPU time	6.67 seconds
Started	Jan 03 01:25:17 PM PST 24
Finished	Jan 03 01:25:46 PM PST 24
Peak memory	220340 kb
Host	smart-f776c371-518e-4e96-adbf-6f833304c906
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565378889 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 47.kmac_test_vectors_kmac_xof.565378889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.838651568
Short name	T879
Test name
Test status
Simulation time	389369499427 ps
CPU time	2480.39 seconds
Started	Jan 03 01:25:15 PM PST 24
Finished	Jan 03 02:06:57 PM PST 24
Peak memory	400672 kb
Host	smart-ffc903fb-04df-41d9-8705-3ff2969c1d7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=838651568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.838651568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.2892561251
Short name	T425
Test name
Test status
Simulation time	157853566190 ps
CPU time	2090.23 seconds
Started	Jan 03 01:25:19 PM PST 24
Finished	Jan 03 02:00:32 PM PST 24
Peak memory	384740 kb
Host	smart-9a342e01-3623-4a63-8229-7398a0b3846a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2892561251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2892561251 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.597177566
Short name	T623
Test name
Test status
Simulation time	50900962275 ps
CPU time	1723.34 seconds
Started	Jan 03 01:25:17 PM PST 24
Finished	Jan 03 01:54:23 PM PST 24
Peak memory	348484 kb
Host	smart-35abde8e-d4c9-420d-bf02-c657ab82a7dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=597177566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.597177566 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.1877065514
Short name	T961
Test name
Test status
Simulation time	46999186925 ps
CPU time	1266.83 seconds
Started	Jan 03 01:25:15 PM PST 24
Finished	Jan 03 01:46:42 PM PST 24
Peak memory	301420 kb
Host	smart-5d35199b-d24a-4581-90f6-b4edab552cc0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1877065514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1877065514 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.2463052667
Short name	T427
Test name
Test status
Simulation time	1028072696748 ps
CPU time	4646.23 seconds
Started	Jan 03 01:25:17 PM PST 24
Finished	Jan 03 02:43:06 PM PST 24
Peak memory	663116 kb
Host	smart-4d9393d1-59e3-4b46-bd6e-1c31ecd29fd9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2463052667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2463052667 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.1382950041
Short name	T959
Test name
Test status
Simulation time	302369778896 ps
CPU time	4823.85 seconds
Started	Jan 03 01:25:19 PM PST 24
Finished	Jan 03 02:46:06 PM PST 24
Peak memory	567644 kb
Host	smart-02142bf9-3ce7-45e9-996e-999e999871cb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1382950041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1382950041 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.1803661534
Short name	T231
Test name
Test status
Simulation time	32808396 ps
CPU time	0.9 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:25:24 PM PST 24
Peak memory	219740 kb
Host	smart-77724301-8f3d-4e24-879f-41753e436cd1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803661534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1803661534 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.1659314385
Short name	T34
Test name
Test status
Simulation time	7065893500 ps
CPU time	150.41 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:27:52 PM PST 24
Peak memory	239012 kb
Host	smart-d5ab5f95-16f6-40c6-a5ff-ecd5afe5173f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659314385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1659314385 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.1203121510
Short name	T371
Test name
Test status
Simulation time	6456088107 ps
CPU time	631 seconds
Started	Jan 03 01:24:45 PM PST 24
Finished	Jan 03 01:35:21 PM PST 24
Peak memory	243352 kb
Host	smart-90b832a5-4f49-402b-84fd-06bcbca62865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203121510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1203121510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.3633691440
Short name	T117
Test name
Test status
Simulation time	19708082402 ps
CPU time	194.69 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:28:34 PM PST 24
Peak memory	242816 kb
Host	smart-86b579f4-5e0b-4142-b48d-f783fc0c2a67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633691440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3633691440 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.2832880130
Short name	T677
Test name
Test status
Simulation time	2510761638 ps
CPU time	94.36 seconds
Started	Jan 03 01:24:57 PM PST 24
Finished	Jan 03 01:26:45 PM PST 24
Peak memory	243576 kb
Host	smart-7a4fa6b4-221e-4ff0-9925-62bfd588afb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832880130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2832880130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.3431593725
Short name	T675
Test name
Test status
Simulation time	491809777 ps
CPU time	3.71 seconds
Started	Jan 03 01:24:57 PM PST 24
Finished	Jan 03 01:25:14 PM PST 24
Peak memory	218540 kb
Host	smart-5077801d-e056-405b-a39d-544da22e1ccc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431593725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3431593725 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.3252482810
Short name	T103
Test name
Test status
Simulation time	41107104 ps
CPU time	1.41 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:25:18 PM PST 24
Peak memory	219724 kb
Host	smart-4c79c48c-c913-4aa2-bbf9-efced54fbed8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252482810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3252482810 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.2577435870
Short name	T115
Test name
Test status
Simulation time	55190751387 ps
CPU time	310.01 seconds
Started	Jan 03 01:24:50 PM PST 24
Finished	Jan 03 01:30:09 PM PST 24
Peak memory	250176 kb
Host	smart-ec4cc214-2117-425a-8d21-84ae4cb8c0ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577435870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.2577435870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.1616754780
Short name	T795
Test name
Test status
Simulation time	14685398481 ps
CPU time	280.28 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 01:29:41 PM PST 24
Peak memory	248676 kb
Host	smart-65b95ec0-071c-4ce7-a276-40578c89fc5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616754780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1616754780 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.1335353049
Short name	T676
Test name
Test status
Simulation time	1177451405 ps
CPU time	42.21 seconds
Started	Jan 03 01:24:44 PM PST 24
Finished	Jan 03 01:25:32 PM PST 24
Peak memory	226856 kb
Host	smart-5f7296ab-a6fb-4d8e-adc2-3a01a721a4e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335353049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1335353049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.222857423
Short name	T242
Test name
Test status
Simulation time	81552463516 ps
CPU time	363.02 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:31:22 PM PST 24
Peak memory	275596 kb
Host	smart-6d2cb7a3-7435-4908-b7ca-95164760b6ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=222857423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.222857423 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.1047021148
Short name	T966
Test name
Test status
Simulation time	413004147 ps
CPU time	5.51 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:25:24 PM PST 24
Peak memory	218600 kb
Host	smart-66421ad7-71e4-4dc2-8844-318bf02973c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047021148 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.1047021148 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1852654419
Short name	T765
Test name
Test status
Simulation time	493988664 ps
CPU time	5.47 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:26 PM PST 24
Peak memory	218768 kb
Host	smart-f7d695b6-4433-437f-9f8c-c0ba82894129
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852654419 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1852654419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.702690378
Short name	T758
Test name
Test status
Simulation time	446377946874 ps
CPU time	2374.4 seconds
Started	Jan 03 01:24:54 PM PST 24
Finished	Jan 03 02:04:41 PM PST 24
Peak memory	402472 kb
Host	smart-26b81274-f237-4326-bea0-02c03ddca946
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=702690378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.702690378 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.1813540218
Short name	T650
Test name
Test status
Simulation time	65168007552 ps
CPU time	1776.52 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:54:40 PM PST 24
Peak memory	384088 kb
Host	smart-82f86f12-30c5-4f8f-b478-a0674a1f24f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1813540218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.1813540218 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.1093069821
Short name	T399
Test name
Test status
Simulation time	18951979123 ps
CPU time	1431.88 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:48:56 PM PST 24
Peak memory	338472 kb
Host	smart-d5494b76-a134-4cff-87fe-4f4ef8911259
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1093069821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.1093069821 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.38997405
Short name	T696
Test name
Test status
Simulation time	43608429644 ps
CPU time	1137.88 seconds
Started	Jan 03 01:24:48 PM PST 24
Finished	Jan 03 01:43:53 PM PST 24
Peak memory	302048 kb
Host	smart-03f3bc1b-e4de-40d1-97cd-4fa6e3c64f8a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=38997405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.38997405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.3301609846
Short name	T232
Test name
Test status
Simulation time	923707757714 ps
CPU time	6079.88 seconds
Started	Jan 03 01:24:51 PM PST 24
Finished	Jan 03 03:06:23 PM PST 24
Peak memory	656520 kb
Host	smart-9b3f7fe8-1fae-4533-bc04-3bb6d77c1594
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3301609846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3301609846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.3913988214
Short name	T908
Test name
Test status
Simulation time	219421238727 ps
CPU time	4053.73 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 02:32:39 PM PST 24
Peak memory	576636 kb
Host	smart-e6cb175f-64f0-42fa-93c9-f3d56467a16a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3913988214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3913988214 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.3837019776
Short name	T453
Test name
Test status
Simulation time	19703952 ps
CPU time	0.83 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:20 PM PST 24
Peak memory	218584 kb
Host	smart-4fe0ef4a-c1bf-4df7-8720-b45934a8d8de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837019776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3837019776 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.3629820967
Short name	T934
Test name
Test status
Simulation time	10167626795 ps
CPU time	116.22 seconds
Started	Jan 03 01:24:57 PM PST 24
Finished	Jan 03 01:27:07 PM PST 24
Peak memory	235576 kb
Host	smart-e8e58416-e99e-4986-8d0f-f70b4873f91a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629820967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3629820967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.2916457903
Short name	T393
Test name
Test status
Simulation time	77947365357 ps
CPU time	389.95 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 01:31:33 PM PST 24
Peak memory	252728 kb
Host	smart-1e3e2257-1606-4fd1-af90-c8abc4b6b982
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916457903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2916457903 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.586541986
Short name	T994
Test name
Test status
Simulation time	6799305860 ps
CPU time	56.29 seconds
Started	Jan 03 01:24:53 PM PST 24
Finished	Jan 03 01:26:01 PM PST 24
Peak memory	243368 kb
Host	smart-5f527874-f0cc-40aa-b6c3-38567a5be178
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586541986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.586541986 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.226188972
Short name	T715
Test name
Test status
Simulation time	857430735 ps
CPU time	3.16 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:25:24 PM PST 24
Peak memory	218756 kb
Host	smart-14fcc382-1670-4342-b148-6aa9332da41b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226188972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.226188972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.434952488
Short name	T534
Test name
Test status
Simulation time	52692689 ps
CPU time	1.4 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:25:20 PM PST 24
Peak memory	218956 kb
Host	smart-250e2bde-cb5e-4ee6-a4ad-e1936be0c2ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434952488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.434952488 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.826742091
Short name	T636
Test name
Test status
Simulation time	320565648563 ps
CPU time	3157.75 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 02:18:03 PM PST 24
Peak memory	474940 kb
Host	smart-c34ec1cf-ff18-497f-b26f-66e6fbde0cb9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826742091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an d_output.826742091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.1113030927
Short name	T222
Test name
Test status
Simulation time	1607302891 ps
CPU time	43.37 seconds
Started	Jan 03 01:25:10 PM PST 24
Finished	Jan 03 01:26:12 PM PST 24
Peak memory	241784 kb
Host	smart-14783a79-87e3-4b8e-8b7d-ad55f5f7cea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113030927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1113030927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.1095524815
Short name	T741
Test name
Test status
Simulation time	3949262627 ps
CPU time	42.03 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:26:07 PM PST 24
Peak memory	226876 kb
Host	smart-078863ef-6cf4-42c4-9251-4ba950f7996e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095524815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1095524815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.2072169012
Short name	T867
Test name
Test status
Simulation time	14625859185 ps
CPU time	719.33 seconds
Started	Jan 03 01:25:05 PM PST 24
Finished	Jan 03 01:37:18 PM PST 24
Peak memory	292008 kb
Host	smart-95761142-d57b-4eef-b2d9-33bb6936f0e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2072169012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2072169012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_stress_all_with_rand_reset.2634456388
Short name	T155
Test name
Test status
Simulation time	39668618256 ps
CPU time	205.94 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:28:45 PM PST 24
Peak memory	254644 kb
Host	smart-d8604aaf-d220-45da-9f79-1bb5d93d8ec4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2634456388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.2634456388 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.1521115370
Short name	T900
Test name
Test status
Simulation time	482970799 ps
CPU time	6.22 seconds
Started	Jan 03 01:25:06 PM PST 24
Finished	Jan 03 01:25:26 PM PST 24
Peak memory	220264 kb
Host	smart-3db3fc3f-3089-45b3-b17c-193a7df14d3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521115370 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.1521115370 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2972818565
Short name	T243
Test name
Test status
Simulation time	945221072 ps
CPU time	6.6 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 01:25:28 PM PST 24
Peak memory	220192 kb
Host	smart-69778585-dfb6-4962-9e67-dc46e26a2a78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972818565 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2972818565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.3042921973
Short name	T284
Test name
Test status
Simulation time	20944866829 ps
CPU time	1886.5 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:56:43 PM PST 24
Peak memory	396700 kb
Host	smart-4cb06e08-d540-4f7b-a8b1-b956ef33b4ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3042921973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3042921973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.2375695019
Short name	T435
Test name
Test status
Simulation time	83737198310 ps
CPU time	1954.69 seconds
Started	Jan 03 01:25:08 PM PST 24
Finished	Jan 03 01:57:58 PM PST 24
Peak memory	390560 kb
Host	smart-b7aae03b-384e-48d6-93f0-7b722e2e2589
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2375695019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2375695019 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.2204405451
Short name	T1033
Test name
Test status
Simulation time	20369749370 ps
CPU time	1470.51 seconds
Started	Jan 03 01:24:54 PM PST 24
Finished	Jan 03 01:49:36 PM PST 24
Peak memory	346968 kb
Host	smart-b7813b95-350f-4640-9dc1-66b0b5bdfa3b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2204405451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2204405451 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.3477314782
Short name	T275
Test name
Test status
Simulation time	103398575676 ps
CPU time	1344.52 seconds
Started	Jan 03 01:25:04 PM PST 24
Finished	Jan 03 01:47:40 PM PST 24
Peak memory	305192 kb
Host	smart-15310bbb-7aa3-46b6-861f-8fe3615cd9bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3477314782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3477314782 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.948823398
Short name	T171
Test name
Test status
Simulation time	759517806089 ps
CPU time	5632.8 seconds
Started	Jan 03 01:25:07 PM PST 24
Finished	Jan 03 02:59:15 PM PST 24
Peak memory	659212 kb
Host	smart-06d29162-ea3c-4aef-982c-31ee415df550
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=948823398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.948823398 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.81447776
Short name	T949
Test name
Test status
Simulation time	53499264466 ps
CPU time	4175.1 seconds
Started	Jan 03 01:24:52 PM PST 24
Finished	Jan 03 02:34:39 PM PST 24
Peak memory	551612 kb
Host	smart-68886fbe-2d99-4061-8458-32e04541ab31
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=81447776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.81447776 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.1748511466
Short name	T660
Test name
Test status
Simulation time	12523581 ps
CPU time	0.84 seconds
Started	Jan 03 01:19:47 PM PST 24
Finished	Jan 03 01:19:53 PM PST 24
Peak memory	218496 kb
Host	smart-57dcf621-7332-4f1a-ba2e-f34ead646f80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748511466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1748511466 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.3596181757
Short name	T711
Test name
Test status
Simulation time	16176648365 ps
CPU time	94.85 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:22:26 PM PST 24
Peak memory	234640 kb
Host	smart-fc7cb34f-483c-49c9-a5e6-4c3d3dce682f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596181757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3596181757 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.3994829609
Short name	T53
Test name
Test status
Simulation time	38423042678 ps
CPU time	313.13 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:26:04 PM PST 24
Peak memory	250920 kb
Host	smart-1b682d56-9818-4913-a273-f247e4db873a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994829609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3994829609 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.1063758479
Short name	T248
Test name
Test status
Simulation time	27570499963 ps
CPU time	1054.98 seconds
Started	Jan 03 01:20:35 PM PST 24
Finished	Jan 03 01:38:14 PM PST 24
Peak memory	240560 kb
Host	smart-6f3759df-ed9f-4f15-9b35-6286196cbeec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063758479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1063758479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.2416828651
Short name	T806
Test name
Test status
Simulation time	168956718 ps
CPU time	12.77 seconds
Started	Jan 03 01:20:49 PM PST 24
Finished	Jan 03 01:21:12 PM PST 24
Peak memory	233396 kb
Host	smart-79772026-609a-43ed-aab4-5e7f1d1523ff
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2416828651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2416828651 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.2082433155
Short name	T809
Test name
Test status
Simulation time	96239027 ps
CPU time	1.1 seconds
Started	Jan 03 01:20:59 PM PST 24
Finished	Jan 03 01:21:08 PM PST 24
Peak memory	218724 kb
Host	smart-9993ddb0-2f10-4989-b083-692e8a54c80d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2082433155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2082433155 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.281636550
Short name	T1090
Test name
Test status
Simulation time	3617867685 ps
CPU time	38.14 seconds
Started	Jan 03 01:20:41 PM PST 24
Finished	Jan 03 01:21:25 PM PST 24
Peak memory	220636 kb
Host	smart-23a1dc19-8c5f-4fc8-a613-af886b199d4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281636550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.281636550 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.2556055967
Short name	T31
Test name
Test status
Simulation time	8188529646 ps
CPU time	223.58 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:24:29 PM PST 24
Peak memory	243452 kb
Host	smart-cd73796b-ad72-44ca-9981-504bba399cd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556055967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2556055967 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.933753488
Short name	T54
Test name
Test status
Simulation time	4305303685 ps
CPU time	161.92 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:23:35 PM PST 24
Peak memory	251916 kb
Host	smart-62dd172d-0e14-4373-a89b-9371ff71d85c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933753488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.933753488 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.1715849794
Short name	T1035
Test name
Test status
Simulation time	10569446437 ps
CPU time	10.94 seconds
Started	Jan 03 01:20:48 PM PST 24
Finished	Jan 03 01:21:10 PM PST 24
Peak memory	218592 kb
Host	smart-0872de86-0615-46c3-bf9b-039268dac813
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715849794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1715849794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.1803237171
Short name	T236
Test name
Test status
Simulation time	72845592 ps
CPU time	1.45 seconds
Started	Jan 03 01:20:48 PM PST 24
Finished	Jan 03 01:21:00 PM PST 24
Peak memory	220256 kb
Host	smart-2f68cccf-a335-4418-af0c-1976507e14e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803237171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1803237171 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.759368231
Short name	T1139
Test name
Test status
Simulation time	87229122282 ps
CPU time	523.68 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:29:19 PM PST 24
Peak memory	262036 kb
Host	smart-40f8f9fa-73f7-46b2-af8e-5a9b94d13424
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759368231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and _output.759368231 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.953791773
Short name	T999
Test name
Test status
Simulation time	32573662083 ps
CPU time	218.34 seconds
Started	Jan 03 01:20:46 PM PST 24
Finished	Jan 03 01:24:33 PM PST 24
Peak memory	244704 kb
Host	smart-71f88564-3539-4293-8f81-5cb73efa2fee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953791773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.953791773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.2217155721
Short name	T939
Test name
Test status
Simulation time	17048543691 ps
CPU time	283.59 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:25:21 PM PST 24
Peak memory	247716 kb
Host	smart-06b25c54-122f-4309-aa5d-c42be303e352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217155721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2217155721 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.1651380440
Short name	T1095
Test name
Test status
Simulation time	1994761560 ps
CPU time	19.53 seconds
Started	Jan 03 01:20:33 PM PST 24
Finished	Jan 03 01:20:56 PM PST 24
Peak memory	219192 kb
Host	smart-96ab7fe0-5fa3-484c-a26f-536c7058d0d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651380440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1651380440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.519716110
Short name	T255
Test name
Test status
Simulation time	2948421775 ps
CPU time	21.31 seconds
Started	Jan 03 01:20:49 PM PST 24
Finished	Jan 03 01:21:21 PM PST 24
Peak memory	234648 kb
Host	smart-3cf2ba9a-937f-45b7-b051-8a36776d7810
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=519716110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.519716110 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.258545853
Short name	T443
Test name
Test status
Simulation time	348717748 ps
CPU time	5.58 seconds
Started	Jan 03 01:20:41 PM PST 24
Finished	Jan 03 01:20:52 PM PST 24
Peak memory	220056 kb
Host	smart-16e7d180-4784-46de-a495-6d7a921003c2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258545853 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.kmac_test_vectors_kmac.258545853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2250079836
Short name	T794
Test name
Test status
Simulation time	87695267 ps
CPU time	5.51 seconds
Started	Jan 03 01:20:39 PM PST 24
Finished	Jan 03 01:20:48 PM PST 24
Peak memory	218792 kb
Host	smart-d2679961-0e27-49c6-9310-de050d70f09b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250079836 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2250079836 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.3722540158
Short name	T363
Test name
Test status
Simulation time	385596561359 ps
CPU time	2220.35 seconds
Started	Jan 03 01:20:13 PM PST 24
Finished	Jan 03 01:57:18 PM PST 24
Peak memory	403608 kb
Host	smart-240f7c42-0af2-4e98-b1b9-38f582fc3c2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3722540158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3722540158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.1087734702
Short name	T898
Test name
Test status
Simulation time	19441750997 ps
CPU time	1845.73 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:51:37 PM PST 24
Peak memory	393304 kb
Host	smart-6a541eb6-a2d0-4606-9b56-14a035ee35cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1087734702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1087734702 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.2630994996
Short name	T772
Test name
Test status
Simulation time	195623062735 ps
CPU time	1686.84 seconds
Started	Jan 03 01:20:47 PM PST 24
Finished	Jan 03 01:49:03 PM PST 24
Peak memory	338084 kb
Host	smart-4aa92269-ba04-4a33-9485-16c7bddbca25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2630994996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2630994996 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2594412158
Short name	T426
Test name
Test status
Simulation time	229141090194 ps
CPU time	1310.04 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:42:29 PM PST 24
Peak memory	305944 kb
Host	smart-7cb1281d-6aea-4c51-a881-04250407e790
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2594412158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2594412158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.102905418
Short name	T511
Test name
Test status
Simulation time	188206506007 ps
CPU time	5970.64 seconds
Started	Jan 03 01:20:38 PM PST 24
Finished	Jan 03 03:00:13 PM PST 24
Peak memory	680464 kb
Host	smart-689f5c48-0e20-464d-a7f8-f4d8e4a27d8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=102905418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.102905418 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.3006972268
Short name	T394
Test name
Test status
Simulation time	311138242488 ps
CPU time	4885.7 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 02:42:28 PM PST 24
Peak memory	581976 kb
Host	smart-a4276e1a-cd20-49ec-8bc2-0d320a33d2c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3006972268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3006972268 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.1218308277
Short name	T432
Test name
Test status
Simulation time	38232952 ps
CPU time	0.86 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 01:21:02 PM PST 24
Peak memory	218236 kb
Host	smart-949d004c-a5f9-4556-81bd-8023aee08cf4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218308277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1218308277 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.1769118065
Short name	T289
Test name
Test status
Simulation time	13704658169 ps
CPU time	390.18 seconds
Started	Jan 03 01:20:12 PM PST 24
Finished	Jan 03 01:26:46 PM PST 24
Peak memory	254920 kb
Host	smart-380e1266-0888-4d24-ac4b-4925d6cb5b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769118065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1769118065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.1896357585
Short name	T27
Test name
Test status
Simulation time	3894351829 ps
CPU time	48.41 seconds
Started	Jan 03 01:20:30 PM PST 24
Finished	Jan 03 01:21:22 PM PST 24
Peak memory	230008 kb
Host	smart-d708cbef-d410-4460-9ced-dc6bdb616afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896357585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1896357585 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.249075683
Short name	T780
Test name
Test status
Simulation time	13572147487 ps
CPU time	689.7 seconds
Started	Jan 03 01:19:44 PM PST 24
Finished	Jan 03 01:31:21 PM PST 24
Peak memory	235816 kb
Host	smart-f902fff5-b688-4dab-b885-7c11cfa349e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249075683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.249075683 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.927614965
Short name	T401
Test name
Test status
Simulation time	459796210 ps
CPU time	35.06 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:21:25 PM PST 24
Peak memory	243104 kb
Host	smart-20ef769f-155e-4df3-afb0-a9d3668cfaa6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=927614965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.927614965 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.1443663032
Short name	T984
Test name
Test status
Simulation time	22213230 ps
CPU time	1.07 seconds
Started	Jan 03 01:20:41 PM PST 24
Finished	Jan 03 01:20:47 PM PST 24
Peak memory	218668 kb
Host	smart-fbb2f0cb-8891-4f48-8973-93220eb90183
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1443663032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1443663032 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.1519771261
Short name	T1109
Test name
Test status
Simulation time	4668147019 ps
CPU time	44.55 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 01:21:32 PM PST 24
Peak memory	227004 kb
Host	smart-9f3dbfad-0593-46d9-87db-59ccc7f151d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519771261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1519771261 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.624276510
Short name	T963
Test name
Test status
Simulation time	27962558678 ps
CPU time	216.74 seconds
Started	Jan 03 01:20:33 PM PST 24
Finished	Jan 03 01:24:14 PM PST 24
Peak memory	245260 kb
Host	smart-a994e802-cad0-422f-bfe8-2f872edd5f1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624276510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.624276510 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.2565138198
Short name	T1016
Test name
Test status
Simulation time	17185932671 ps
CPU time	320.48 seconds
Started	Jan 03 01:20:51 PM PST 24
Finished	Jan 03 01:26:21 PM PST 24
Peak memory	254768 kb
Host	smart-a68bf28a-3e1b-4245-ae90-b9174cf0db90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565138198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2565138198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.2072326968
Short name	T445
Test name
Test status
Simulation time	416129504 ps
CPU time	2.96 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:20:55 PM PST 24
Peak memory	218688 kb
Host	smart-f33ede8a-54f0-4863-887e-5d956420a047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072326968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2072326968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.550807443
Short name	T1138
Test name
Test status
Simulation time	452759542 ps
CPU time	2.17 seconds
Started	Jan 03 01:20:48 PM PST 24
Finished	Jan 03 01:21:00 PM PST 24
Peak memory	219740 kb
Host	smart-0afccad9-6717-45ee-9154-80ccb54d9c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550807443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.550807443 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.2290219213
Short name	T1049
Test name
Test status
Simulation time	80309369553 ps
CPU time	1507.26 seconds
Started	Jan 03 01:19:47 PM PST 24
Finished	Jan 03 01:45:01 PM PST 24
Peak memory	339608 kb
Host	smart-adc6ba0c-1b55-4cb1-b544-a0f05f7bee28
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290219213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.2290219213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.1751732356
Short name	T1001
Test name
Test status
Simulation time	1311405464 ps
CPU time	31.94 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:21:16 PM PST 24
Peak memory	227212 kb
Host	smart-b8ac45ec-c84d-4870-bd14-e3bde09c1ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751732356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1751732356 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.3882086259
Short name	T216
Test name
Test status
Simulation time	52786114366 ps
CPU time	435.28 seconds
Started	Jan 03 01:19:55 PM PST 24
Finished	Jan 03 01:27:17 PM PST 24
Peak memory	254048 kb
Host	smart-51e2715b-da19-4043-9d16-c1457b6913f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882086259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3882086259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.608894483
Short name	T736
Test name
Test status
Simulation time	926455177 ps
CPU time	34.31 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 01:20:28 PM PST 24
Peak memory	226732 kb
Host	smart-7321af5f-8f0b-4b57-bbc4-bf34692bc7cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608894483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.608894483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.2676690932
Short name	T81
Test name
Test status
Simulation time	26980458517 ps
CPU time	712.88 seconds
Started	Jan 03 01:20:45 PM PST 24
Finished	Jan 03 01:32:47 PM PST 24
Peak memory	299300 kb
Host	smart-b73c10ad-c9aa-49df-b911-b7fd7c5fef8e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2676690932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2676690932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_stress_all_with_rand_reset.3114341678
Short name	T895
Test name
Test status
Simulation time	5080911137 ps
CPU time	254.39 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:25:00 PM PST 24
Peak memory	272700 kb
Host	smart-10ae4f30-a687-4eaa-8e0c-036e6c586778
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3114341678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.3114341678 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.362884494
Short name	T290
Test name
Test status
Simulation time	532312738 ps
CPU time	6 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:20:20 PM PST 24
Peak memory	220164 kb
Host	smart-4e8f9671-a4b5-40b1-8d4b-0349478db164
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362884494 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.kmac_test_vectors_kmac.362884494 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.639238553
Short name	T347
Test name
Test status
Simulation time	163579665 ps
CPU time	6.39 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:20:44 PM PST 24
Peak memory	218852 kb
Host	smart-9af1758b-724a-4bcf-98fb-58710e98b831
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639238553 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.kmac_test_vectors_kmac_xof.639238553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.2165070217
Short name	T246
Test name
Test status
Simulation time	351842647971 ps
CPU time	2308.63 seconds
Started	Jan 03 01:19:54 PM PST 24
Finished	Jan 03 01:58:30 PM PST 24
Peak memory	399800 kb
Host	smart-8a08ca1a-8228-4be0-b094-14faab486fff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2165070217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2165070217 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.2253511249
Short name	T513
Test name
Test status
Simulation time	40535561882 ps
CPU time	1905.39 seconds
Started	Jan 03 01:19:46 PM PST 24
Finished	Jan 03 01:51:38 PM PST 24
Peak memory	388940 kb
Host	smart-9be07f55-dabd-478e-8fbe-db7c1e4cff9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2253511249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2253511249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.2377482755
Short name	T403
Test name
Test status
Simulation time	197892155054 ps
CPU time	1709.06 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:48:44 PM PST 24
Peak memory	341104 kb
Host	smart-e5bd2f18-ade2-48bd-b9a7-66cd4fcd0e02
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2377482755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.2377482755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.2058763654
Short name	T920
Test name
Test status
Simulation time	78664604715 ps
CPU time	1221.72 seconds
Started	Jan 03 01:19:48 PM PST 24
Finished	Jan 03 01:40:16 PM PST 24
Peak memory	301396 kb
Host	smart-ef5c3573-f77c-4b23-a676-80a9d4be1a61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2058763654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2058763654 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.112252397
Short name	T319
Test name
Test status
Simulation time	1377541814263 ps
CPU time	5938.95 seconds
Started	Jan 03 01:20:08 PM PST 24
Finished	Jan 03 02:59:12 PM PST 24
Peak memory	636812 kb
Host	smart-1b9a5888-9220-4a51-adc3-98d1f947a97f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=112252397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.112252397 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.3350936195
Short name	T735
Test name
Test status
Simulation time	597443764224 ps
CPU time	4660.76 seconds
Started	Jan 03 01:20:07 PM PST 24
Finished	Jan 03 02:37:53 PM PST 24
Peak memory	566712 kb
Host	smart-50c18d5e-9437-43ec-ac07-7086466ea615
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3350936195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3350936195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.3651958505
Short name	T823
Test name
Test status
Simulation time	34380579 ps
CPU time	0.94 seconds
Started	Jan 03 01:20:13 PM PST 24
Finished	Jan 03 01:20:18 PM PST 24
Peak memory	218656 kb
Host	smart-4c511254-f3d2-4a67-adbd-5114ddd70043
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651958505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3651958505 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.271931161
Short name	T446
Test name
Test status
Simulation time	8953342683 ps
CPU time	275.4 seconds
Started	Jan 03 01:20:31 PM PST 24
Finished	Jan 03 01:25:10 PM PST 24
Peak memory	248124 kb
Host	smart-c40cf2af-f491-41a1-9d3e-ce7929eb4f7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271931161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.271931161 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.52451374
Short name	T1067
Test name
Test status
Simulation time	22933576113 ps
CPU time	179.35 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:23:12 PM PST 24
Peak memory	241468 kb
Host	smart-2dacbe3c-3c9d-4e47-9edb-6d9150d7e522
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52451374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.52451374 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.2497307417
Short name	T938
Test name
Test status
Simulation time	187882737867 ps
CPU time	1787.9 seconds
Started	Jan 03 01:21:18 PM PST 24
Finished	Jan 03 01:51:07 PM PST 24
Peak memory	238804 kb
Host	smart-f501d67e-c7da-4865-91b2-91fcc14f7669
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497307417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2497307417 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.1166412185
Short name	T413
Test name
Test status
Simulation time	2528789159 ps
CPU time	36.22 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:20:49 PM PST 24
Peak memory	234476 kb
Host	smart-0ca8b1bd-5399-4fbd-a5af-d01130ff8456
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1166412185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1166412185 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.2571994047
Short name	T801
Test name
Test status
Simulation time	37240860 ps
CPU time	0.95 seconds
Started	Jan 03 01:20:30 PM PST 24
Finished	Jan 03 01:20:35 PM PST 24
Peak memory	218600 kb
Host	smart-c8f7e2ec-7a5c-4aab-829e-3f4b22cd9b7b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2571994047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2571994047 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.2605620720
Short name	T681
Test name
Test status
Simulation time	2307996598 ps
CPU time	22.61 seconds
Started	Jan 03 01:20:10 PM PST 24
Finished	Jan 03 01:20:38 PM PST 24
Peak memory	226660 kb
Host	smart-993be29c-caf6-466f-894d-4d57ca6079de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605620720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2605620720 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.350624994
Short name	T602
Test name
Test status
Simulation time	3695767887 ps
CPU time	47.37 seconds
Started	Jan 03 01:20:05 PM PST 24
Finished	Jan 03 01:20:57 PM PST 24
Peak memory	231256 kb
Host	smart-85901c2a-9cbc-41eb-880c-9b53c806cdb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350624994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.350624994 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.349505029
Short name	T870
Test name
Test status
Simulation time	4579718391 ps
CPU time	319.24 seconds
Started	Jan 03 01:20:30 PM PST 24
Finished	Jan 03 01:25:53 PM PST 24
Peak memory	259776 kb
Host	smart-fbef145d-29b9-49bd-8d6f-c54488064f54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349505029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.349505029 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.1947661541
Short name	T684
Test name
Test status
Simulation time	248703508 ps
CPU time	1.46 seconds
Started	Jan 03 01:20:33 PM PST 24
Finished	Jan 03 01:20:38 PM PST 24
Peak memory	218536 kb
Host	smart-370dc45e-409c-413e-9805-31fe2aca3913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947661541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1947661541 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.30311622
Short name	T588
Test name
Test status
Simulation time	35440501 ps
CPU time	1.31 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:20:37 PM PST 24
Peak memory	219904 kb
Host	smart-0f213aa9-1e57-4bff-8934-3689a19fb266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30311622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.30311622 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.3802011498
Short name	T1102
Test name
Test status
Simulation time	16016386816 ps
CPU time	409.91 seconds
Started	Jan 03 01:21:01 PM PST 24
Finished	Jan 03 01:27:57 PM PST 24
Peak memory	262212 kb
Host	smart-92ccb764-0267-499f-9a5c-693c7ccc6bb7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802011498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.3802011498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.3584576878
Short name	T664
Test name
Test status
Simulation time	19984820910 ps
CPU time	230.41 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:24:04 PM PST 24
Peak memory	245804 kb
Host	smart-6a9de37f-da22-40fd-ac00-3e927daa4f6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584576878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3584576878 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.1798263994
Short name	T897
Test name
Test status
Simulation time	57420785783 ps
CPU time	487.41 seconds
Started	Jan 03 01:21:03 PM PST 24
Finished	Jan 03 01:29:15 PM PST 24
Peak memory	258856 kb
Host	smart-cadd09ea-829c-4972-aecd-b9c10d6aba49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798263994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1798263994 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.2542988662
Short name	T680
Test name
Test status
Simulation time	669236635 ps
CPU time	22.53 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 01:21:23 PM PST 24
Peak memory	226824 kb
Host	smart-537c7596-f032-4300-9d63-b96977c86ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542988662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2542988662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.2138408677
Short name	T522
Test name
Test status
Simulation time	340220421 ps
CPU time	7.9 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:20:45 PM PST 24
Peak memory	228416 kb
Host	smart-c34e04ae-1205-47a4-a40d-ec870bb28292
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2138408677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2138408677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_stress_all_with_rand_reset.1668296496
Short name	T918
Test name
Test status
Simulation time	27164592567 ps
CPU time	921.25 seconds
Started	Jan 03 01:20:09 PM PST 24
Finished	Jan 03 01:35:36 PM PST 24
Peak memory	302592 kb
Host	smart-8ceeb158-6980-49d2-b083-d5fa726d8210
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1668296496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.1668296496 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.1048807784
Short name	T723
Test name
Test status
Simulation time	285393649 ps
CPU time	6.71 seconds
Started	Jan 03 01:20:06 PM PST 24
Finished	Jan 03 01:20:17 PM PST 24
Peak memory	220352 kb
Host	smart-04ee3162-fcbd-454e-b242-cace2724af87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048807784 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.1048807784 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2277411191
Short name	T977
Test name
Test status
Simulation time	975807086 ps
CPU time	6.1 seconds
Started	Jan 03 01:20:08 PM PST 24
Finished	Jan 03 01:20:18 PM PST 24
Peak memory	220144 kb
Host	smart-484bcf92-1a18-441c-8052-88cd542bc6eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277411191 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2277411191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.4198272042
Short name	T1018
Test name
Test status
Simulation time	39239992248 ps
CPU time	1867.54 seconds
Started	Jan 03 01:20:49 PM PST 24
Finished	Jan 03 01:52:07 PM PST 24
Peak memory	385584 kb
Host	smart-7411c4e0-873f-4041-82ff-51877062d4cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4198272042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.4198272042 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.1060855921
Short name	T1046
Test name
Test status
Simulation time	887182589819 ps
CPU time	2518.55 seconds
Started	Jan 03 01:20:46 PM PST 24
Finished	Jan 03 02:02:54 PM PST 24
Peak memory	388792 kb
Host	smart-2170fc32-1aa8-433b-ab38-00e52e9c6e4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1060855921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1060855921 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.412774131
Short name	T277
Test name
Test status
Simulation time	280444950596 ps
CPU time	1879.45 seconds
Started	Jan 03 01:20:52 PM PST 24
Finished	Jan 03 01:52:23 PM PST 24
Peak memory	339560 kb
Host	smart-c2d8b719-ceae-4a81-a526-d58e364b5904
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=412774131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.412774131 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.2240363717
Short name	T461
Test name
Test status
Simulation time	138972729521 ps
CPU time	1299.53 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:42:17 PM PST 24
Peak memory	304488 kb
Host	smart-00b7037a-80c0-4aa8-a2bb-2b84070f2e3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2240363717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2240363717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.4270145712
Short name	T1006
Test name
Test status
Simulation time	225292846705 ps
CPU time	5557.34 seconds
Started	Jan 03 01:20:46 PM PST 24
Finished	Jan 03 02:53:34 PM PST 24
Peak memory	650840 kb
Host	smart-d51060b4-93e1-4ec8-8810-dbccc3406fc4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4270145712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.4270145712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.1886487759
Short name	T287
Test name
Test status
Simulation time	344258047219 ps
CPU time	4732.62 seconds
Started	Jan 03 01:20:31 PM PST 24
Finished	Jan 03 02:39:28 PM PST 24
Peak memory	578772 kb
Host	smart-e98d0e6c-367a-42d9-8bc6-8e26f7911252
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1886487759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1886487759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.3131334714
Short name	T209
Test name
Test status
Simulation time	184399879 ps
CPU time	0.86 seconds
Started	Jan 03 01:21:22 PM PST 24
Finished	Jan 03 01:21:28 PM PST 24
Peak memory	218548 kb
Host	smart-bb2bf536-7cc9-4406-9398-ad450e54523b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131334714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3131334714 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.620319170
Short name	T639
Test name
Test status
Simulation time	20385488359 ps
CPU time	233.75 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:24:45 PM PST 24
Peak memory	245332 kb
Host	smart-fc62e4a3-3c82-48a2-a542-772470fea8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620319170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.620319170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.576807454
Short name	T355
Test name
Test status
Simulation time	7142409374 ps
CPU time	125.8 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:23:00 PM PST 24
Peak memory	237560 kb
Host	smart-dcf0b309-e06b-4e4b-a657-84f65daa429a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576807454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.576807454 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.1708499561
Short name	T659
Test name
Test status
Simulation time	6961083679 ps
CPU time	692.61 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:32:23 PM PST 24
Peak memory	243328 kb
Host	smart-8e7b2121-204a-4c26-8a23-6c1952966a0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708499561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1708499561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.1137305780
Short name	T478
Test name
Test status
Simulation time	151204094 ps
CPU time	1.26 seconds
Started	Jan 03 01:20:48 PM PST 24
Finished	Jan 03 01:21:00 PM PST 24
Peak memory	218688 kb
Host	smart-f172f845-5a5f-4a94-8f67-468cb55c5a34
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1137305780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1137305780 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.2184908602
Short name	T460
Test name
Test status
Simulation time	18904100 ps
CPU time	0.86 seconds
Started	Jan 03 01:20:50 PM PST 24
Finished	Jan 03 01:21:01 PM PST 24
Peak memory	218528 kb
Host	smart-97943d2f-123b-4b0c-8545-1f9fc8ffb127
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2184908602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2184908602 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.3207113609
Short name	T874
Test name
Test status
Simulation time	5801861164 ps
CPU time	70.22 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:22:02 PM PST 24
Peak memory	231940 kb
Host	smart-5844f2ef-1346-4f85-9af2-503a854c7d50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207113609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3207113609 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_error.2386241137
Short name	T210
Test name
Test status
Simulation time	106233408522 ps
CPU time	442.39 seconds
Started	Jan 03 01:20:47 PM PST 24
Finished	Jan 03 01:28:19 PM PST 24
Peak memory	268904 kb
Host	smart-836cc39a-c3da-4ccd-836b-ce5e3b080997
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386241137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2386241137 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.267178292
Short name	T605
Test name
Test status
Simulation time	3445985651 ps
CPU time	4.2 seconds
Started	Jan 03 01:20:44 PM PST 24
Finished	Jan 03 01:20:58 PM PST 24
Peak memory	218680 kb
Host	smart-b8ee794c-7e7f-445b-9830-52b67444409e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267178292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.267178292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.1205750328
Short name	T239
Test name
Test status
Simulation time	70913551 ps
CPU time	1.26 seconds
Started	Jan 03 01:21:16 PM PST 24
Finished	Jan 03 01:21:18 PM PST 24
Peak memory	219856 kb
Host	smart-ade5527e-121d-41ad-87ec-a8316e4c9a83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205750328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1205750328 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.4122023662
Short name	T952
Test name
Test status
Simulation time	110235355418 ps
CPU time	2943.39 seconds
Started	Jan 03 01:20:11 PM PST 24
Finished	Jan 03 02:09:19 PM PST 24
Peak memory	445776 kb
Host	smart-030718d3-ec7c-440d-af2a-47d4cb56fd54
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122023662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.4122023662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.962242924
Short name	T525
Test name
Test status
Simulation time	8812080824 ps
CPU time	201.27 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:24:13 PM PST 24
Peak memory	244344 kb
Host	smart-c9d59acd-b7ca-410f-8152-3ef8a29c32ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962242924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.962242924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.267947023
Short name	T412
Test name
Test status
Simulation time	16837624876 ps
CPU time	298.58 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 01:25:36 PM PST 24
Peak memory	250216 kb
Host	smart-0094d99b-0ec5-4234-899a-fc9a670b6f65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267947023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.267947023 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.3604546009
Short name	T332
Test name
Test status
Simulation time	8814726113 ps
CPU time	85.35 seconds
Started	Jan 03 01:20:32 PM PST 24
Finished	Jan 03 01:22:01 PM PST 24
Peak memory	224620 kb
Host	smart-3a5da323-2e0d-452b-9c54-ceac6a10a031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604546009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3604546009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.416865275
Short name	T619
Test name
Test status
Simulation time	270145352834 ps
CPU time	1874.45 seconds
Started	Jan 03 01:21:17 PM PST 24
Finished	Jan 03 01:52:33 PM PST 24
Peak memory	366048 kb
Host	smart-2f18990a-cdc1-4e0f-9b10-3ce742d60648
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=416865275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.416865275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_stress_all_with_rand_reset.1179207745
Short name	T925
Test name
Test status
Simulation time	42775692983 ps
CPU time	236.88 seconds
Started	Jan 03 01:21:18 PM PST 24
Finished	Jan 03 01:25:16 PM PST 24
Peak memory	254416 kb
Host	smart-826e3b21-f4c6-4ebf-bfd7-c0c759ca85c4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1179207745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.1179207745 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.3398953704
Short name	T954
Test name
Test status
Simulation time	112751034 ps
CPU time	5.55 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 01:20:54 PM PST 24
Peak memory	220144 kb
Host	smart-2bc160f8-4fb2-4d1b-a036-df785e62b722
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398953704 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.3398953704 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1957264558
Short name	T28
Test name
Test status
Simulation time	260923827 ps
CPU time	6.15 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:20:52 PM PST 24
Peak memory	220104 kb
Host	smart-bd122860-7c6e-4640-af75-a575003a6872
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957264558 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1957264558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.1342497147
Short name	T796
Test name
Test status
Simulation time	418198304291 ps
CPU time	2431.4 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 02:01:21 PM PST 24
Peak memory	395752 kb
Host	smart-513387b1-3c16-4058-9c83-1b5dbabf57d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1342497147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1342497147 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.1561856064
Short name	T207
Test name
Test status
Simulation time	261451105954 ps
CPU time	2098.33 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 01:55:49 PM PST 24
Peak memory	380700 kb
Host	smart-2b2aaf88-4035-4a2b-b5f4-cdea4b67d5b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1561856064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.1561856064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.791110301
Short name	T1040
Test name
Test status
Simulation time	31461746952 ps
CPU time	1505.92 seconds
Started	Jan 03 01:20:42 PM PST 24
Finished	Jan 03 01:45:55 PM PST 24
Peak memory	342328 kb
Host	smart-19328b51-f4a6-4dc4-b815-f6ad7f562966
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=791110301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.791110301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.3355581086
Short name	T1059
Test name
Test status
Simulation time	42288816217 ps
CPU time	1114 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:39:18 PM PST 24
Peak memory	300672 kb
Host	smart-e579465c-a17e-4151-864e-c46eee7a6cd0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3355581086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3355581086 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.291816481
Short name	T512
Test name
Test status
Simulation time	236610615568 ps
CPU time	5711.53 seconds
Started	Jan 03 01:20:45 PM PST 24
Finished	Jan 03 02:56:06 PM PST 24
Peak memory	664904 kb
Host	smart-0e65c703-74a9-452a-a362-8e825d8b457a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=291816481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.291816481 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.181282569
Short name	T303
Test name
Test status
Simulation time	2140255361599 ps
CPU time	5458.01 seconds
Started	Jan 03 01:20:43 PM PST 24
Finished	Jan 03 02:51:49 PM PST 24
Peak memory	572592 kb
Host	smart-50c1e407-17de-467e-9306-837bda24cc41
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=181282569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.181282569 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.2597496084
Short name	T411
Test name
Test status
Simulation time	143588083 ps
CPU time	0.86 seconds
Started	Jan 03 01:20:39 PM PST 24
Finished	Jan 03 01:20:44 PM PST 24
Peak memory	219784 kb
Host	smart-1153adfd-4d33-4c77-a2ba-2da552073210
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597496084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2597496084 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.845036205
Short name	T158
Test name
Test status
Simulation time	5344879838 ps
CPU time	140.22 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:24:07 PM PST 24
Peak memory	237444 kb
Host	smart-d4137f38-8588-4e39-a6ae-4e0cde2e9cc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845036205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.845036205 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.3876829069
Short name	T572
Test name
Test status
Simulation time	7778783504 ps
CPU time	167.31 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:24:35 PM PST 24
Peak memory	240520 kb
Host	smart-59a81a44-a876-4a19-8f21-397ba022adc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876829069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3876829069 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.2847483080
Short name	T585
Test name
Test status
Simulation time	35151377107 ps
CPU time	554 seconds
Started	Jan 03 01:21:16 PM PST 24
Finished	Jan 03 01:30:32 PM PST 24
Peak memory	235560 kb
Host	smart-7f849684-64ed-4be8-940a-3a129eb8e4e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847483080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2847483080 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.766394155
Short name	T683
Test name
Test status
Simulation time	157712926 ps
CPU time	1.31 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:21:48 PM PST 24
Peak memory	218780 kb
Host	smart-aacb79b8-970a-4c30-b2c8-eceb1fa3a1ab
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=766394155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.766394155 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.3145292868
Short name	T87
Test name
Test status
Simulation time	209406770 ps
CPU time	1.44 seconds
Started	Jan 03 01:20:46 PM PST 24
Finished	Jan 03 01:20:57 PM PST 24
Peak memory	218796 kb
Host	smart-72ce2768-9000-4f28-a4cf-be7dd7277a78
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3145292868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3145292868 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.630307346
Short name	T47
Test name
Test status
Simulation time	7212881048 ps
CPU time	68.98 seconds
Started	Jan 03 01:21:37 PM PST 24
Finished	Jan 03 01:22:54 PM PST 24
Peak memory	222492 kb
Host	smart-cdb74a25-a3c2-43fd-af9b-84a4bb8c9885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=630307346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.630307346 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.1063969150
Short name	T517
Test name
Test status
Simulation time	13794843637 ps
CPU time	70.48 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:22:57 PM PST 24
Peak memory	232352 kb
Host	smart-5938bac0-ea30-4c0c-a52c-0fbce4ecd0a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063969150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1063969150 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.2399479789
Short name	T811
Test name
Test status
Simulation time	2482859176 ps
CPU time	59.86 seconds
Started	Jan 03 01:21:39 PM PST 24
Finished	Jan 03 01:22:48 PM PST 24
Peak memory	243352 kb
Host	smart-362678ca-dfe9-446d-9138-bfb1a4e8f8b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399479789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2399479789 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.3508003466
Short name	T866
Test name
Test status
Simulation time	3539980568 ps
CPU time	4.66 seconds
Started	Jan 03 01:20:41 PM PST 24
Finished	Jan 03 01:20:51 PM PST 24
Peak memory	218740 kb
Host	smart-1e4ff090-a234-4292-8aea-986849bb0277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508003466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3508003466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.3708291637
Short name	T226
Test name
Test status
Simulation time	182575589 ps
CPU time	1.47 seconds
Started	Jan 03 01:20:41 PM PST 24
Finished	Jan 03 01:20:48 PM PST 24
Peak memory	219788 kb
Host	smart-c416a595-fa0c-4d9d-94ff-761877ad550b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708291637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3708291637 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.3718604448
Short name	T223
Test name
Test status
Simulation time	21993575432 ps
CPU time	1752.46 seconds
Started	Jan 03 01:21:33 PM PST 24
Finished	Jan 03 01:50:51 PM PST 24
Peak memory	401060 kb
Host	smart-1144711d-dd64-4b71-ae30-63799a764c16
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718604448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an d_output.3718604448 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.3176324890
Short name	T349
Test name
Test status
Simulation time	12385661203 ps
CPU time	58.81 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:22:40 PM PST 24
Peak memory	237796 kb
Host	smart-7e84cf14-93ff-4f74-aa39-b560b99212dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176324890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3176324890 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.2446003173
Short name	T944
Test name
Test status
Simulation time	62766328668 ps
CPU time	158.65 seconds
Started	Jan 03 01:21:31 PM PST 24
Finished	Jan 03 01:24:15 PM PST 24
Peak memory	239312 kb
Host	smart-5a2a7b72-5cca-4461-b451-36a99eb10bd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446003173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2446003173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.2083681948
Short name	T993
Test name
Test status
Simulation time	12506333934 ps
CPU time	57.2 seconds
Started	Jan 03 01:20:52 PM PST 24
Finished	Jan 03 01:22:00 PM PST 24
Peak memory	220128 kb
Host	smart-efff1f90-4bb3-4c00-83e7-f093c9a1567c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083681948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2083681948 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.765330558
Short name	T83
Test name
Test status
Simulation time	247341557687 ps
CPU time	3259.35 seconds
Started	Jan 03 01:20:34 PM PST 24
Finished	Jan 03 02:14:57 PM PST 24
Peak memory	489136 kb
Host	smart-f82fdda3-3b1a-42db-8b2e-d85fcfc33adb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=765330558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.765330558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_stress_all_with_rand_reset.744908859
Short name	T827
Test name
Test status
Simulation time	82900132435 ps
CPU time	1227.9 seconds
Started	Jan 03 01:20:40 PM PST 24
Finished	Jan 03 01:41:11 PM PST 24
Peak memory	305744 kb
Host	smart-b63ada18-eeec-4403-a2cc-de1fa75f8c17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=744908859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.744908859 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.429745841
Short name	T1012
Test name
Test status
Simulation time	166504070 ps
CPU time	5.81 seconds
Started	Jan 03 01:21:35 PM PST 24
Finished	Jan 03 01:21:47 PM PST 24
Peak memory	218672 kb
Host	smart-cb7aaaf8-1e31-4076-b0f9-e350876e0b82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429745841 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.429745841 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.1061593853
Short name	T433
Test name
Test status
Simulation time	224671017 ps
CPU time	5.94 seconds
Started	Jan 03 01:21:36 PM PST 24
Finished	Jan 03 01:21:49 PM PST 24
Peak memory	218728 kb
Host	smart-cf077f5a-a04c-48af-82f6-a1b0f94c5de9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061593853 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.1061593853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.1502984564
Short name	T738
Test name
Test status
Simulation time	89562769015 ps
CPU time	2011.35 seconds
Started	Jan 03 01:21:16 PM PST 24
Finished	Jan 03 01:54:49 PM PST 24
Peak memory	404632 kb
Host	smart-e151da86-40c8-4524-bd5a-3c602d63f7da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1502984564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1502984564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.642444667
Short name	T679
Test name
Test status
Simulation time	64604293214 ps
CPU time	2007.05 seconds
Started	Jan 03 01:21:31 PM PST 24
Finished	Jan 03 01:55:03 PM PST 24
Peak memory	389824 kb
Host	smart-1a657250-93d4-48c5-ae8d-0b193a95e47f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=642444667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.642444667 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.2639674296
Short name	T610
Test name
Test status
Simulation time	73316566690 ps
CPU time	1889.46 seconds
Started	Jan 03 01:21:20 PM PST 24
Finished	Jan 03 01:52:51 PM PST 24
Peak memory	341760 kb
Host	smart-82a0aebc-7468-4c27-b9c5-7bc329342b2f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2639674296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2639674296 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.983684254
Short name	T554
Test name
Test status
Simulation time	32624852115 ps
CPU time	1138.18 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 01:40:46 PM PST 24
Peak memory	299272 kb
Host	smart-b03c0332-a3bf-4460-94d4-a1d2718c2247
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=983684254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.983684254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.2913013774
Short name	T497
Test name
Test status
Simulation time	264722413716 ps
CPU time	5687.7 seconds
Started	Jan 03 01:23:54 PM PST 24
Finished	Jan 03 02:58:47 PM PST 24
Peak memory	660316 kb
Host	smart-90242b45-0b81-4fbb-af35-ce4f8ffce6c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2913013774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2913013774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.1125956531
Short name	T180
Test name
Test status
Simulation time	163615293902 ps
CPU time	4729.79 seconds
Started	Jan 03 01:21:38 PM PST 24
Finished	Jan 03 02:40:37 PM PST 24
Peak memory	575072 kb
Host	smart-5328645e-bedd-4803-ba31-582e2460a506
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1125956531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1125956531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

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