Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101590529	1			T54	8		T58	8		T4	8503
all_values[1]	101590529	1			T54	8		T58	8		T4	8503
all_values[2]	101590529	1			T54	8		T58	8		T4	8503

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

602256

1

T54

11

T58

14

T4

674

auto[1]

304169331

1

T54

13

T58

10

T4

24835

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303214530

1

T54

12

T58

15

T4

24690

auto[1]

1557057

1

T54

12

T58

9

T4

819

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180716	1			T54	4		T58	3		T4	369
all_values[0]	auto[0]	auto[1]	2299	1			T54	4		T58	1		T4	26
all_values[0]	auto[1]	auto[0]	100890794	1			T58	2		T4	7861		T5	19392
all_values[0]	auto[1]	auto[1]	516720	1			T58	2		T4	247		T5	185
all_values[1]	auto[0]	auto[0]	205571	1			T54	1		T58	4		T4	233
all_values[1]	auto[0]	auto[1]	1643	1			T58	2		T4	12		T36	2
all_values[1]	auto[1]	auto[0]	100865939	1			T54	3		T58	1		T4	7997
all_values[1]	auto[1]	auto[1]	517376	1			T54	4		T58	1		T4	261
all_values[2]	auto[0]	auto[0]	210217	1			T54	2		T58	2		T4	28
all_values[2]	auto[0]	auto[1]	1810	1			T58	2		T4	6		T6	3
all_values[2]	auto[1]	auto[0]	100861293	1			T54	2		T58	3		T4	8202
all_values[2]	auto[1]	auto[1]	517209	1			T54	4		T58	1		T4	267