Group : tb.dut.kmac_cov_if::cmd_process_cg
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Group : tb.dut.kmac_cov_if::cmd_process_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_cov_0/kmac_cov_if.sv



Summary for Group tb.dut.kmac_cov_if::cmd_process_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group tb.dut.kmac_cov_if::cmd_process_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
kmac_keccak_state 2 0 2 100.00 100 1 1 0
kmac_msgfifo_empty 2 0 2 100.00 100 1 1 0
kmac_msgfifo_full 2 0 2 100.00 100 1 1 0
kmac_msgfifo_has_data 1 0 1 100.00 100 1 1 0


Summary for Variable kmac_keccak_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_keccak_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
inactive 653642 1 T1 1 T2 1 T3 1
active 52847 1 T4 29 T5 18 T6 25



Summary for Variable kmac_msgfifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_msgfifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 38990 1 T4 21 T5 29 T6 62
empty 667499 1 T1 1 T2 1 T3 1



Summary for Variable kmac_msgfifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_msgfifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_full 706349 1 T1 1 T2 1 T3 1
full 140 1 T6 1 T13 3 T15 5



Summary for Variable kmac_msgfifo_has_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for kmac_msgfifo_has_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
has_data 33989 1 T4 2 T5 4 T6 40

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%