Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345358 |
1 |
|
|
T4 |
238 |
|
T5 |
2 |
|
T6 |
146 |
auto[1] |
361100 |
1 |
|
|
T4 |
184 |
|
T5 |
344 |
|
T22 |
222 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176802 |
1 |
|
|
T4 |
104 |
|
T5 |
90 |
|
T6 |
45 |
lower_val |
173556 |
1 |
|
|
T4 |
112 |
|
T5 |
64 |
|
T6 |
24 |
zero_val |
2093 |
1 |
|
|
T4 |
10 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
262600 |
1 |
|
|
T4 |
138 |
|
T5 |
108 |
|
T6 |
68 |
lower_val |
263418 |
1 |
|
|
T4 |
186 |
|
T5 |
76 |
|
T6 |
78 |
zero_val |
180440 |
1 |
|
|
T4 |
98 |
|
T5 |
162 |
|
T22 |
130 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43266 |
1 |
|
|
T4 |
29 |
|
T6 |
17 |
|
T23 |
20 |
higher_val |
higher_val |
auto[1] |
22583 |
1 |
|
|
T4 |
14 |
|
T5 |
36 |
|
T22 |
14 |
higher_val |
lower_val |
auto[0] |
43216 |
1 |
|
|
T4 |
29 |
|
T6 |
28 |
|
T23 |
8 |
higher_val |
lower_val |
auto[1] |
22750 |
1 |
|
|
T4 |
12 |
|
T5 |
18 |
|
T22 |
3 |
higher_val |
zero_val |
auto[0] |
98 |
1 |
|
|
T4 |
2 |
|
T36 |
1 |
|
T13 |
1 |
higher_val |
zero_val |
auto[1] |
44889 |
1 |
|
|
T4 |
18 |
|
T5 |
36 |
|
T22 |
27 |
lower_val |
higher_val |
auto[0] |
42276 |
1 |
|
|
T4 |
25 |
|
T6 |
9 |
|
T23 |
15 |
lower_val |
higher_val |
auto[1] |
22159 |
1 |
|
|
T4 |
4 |
|
T5 |
17 |
|
T22 |
14 |
lower_val |
lower_val |
auto[0] |
42303 |
1 |
|
|
T4 |
43 |
|
T6 |
15 |
|
T22 |
1 |
lower_val |
lower_val |
auto[1] |
22407 |
1 |
|
|
T4 |
18 |
|
T5 |
17 |
|
T22 |
6 |
lower_val |
zero_val |
auto[0] |
107 |
1 |
|
|
T4 |
1 |
|
T29 |
1 |
|
T17 |
1 |
lower_val |
zero_val |
auto[1] |
44304 |
1 |
|
|
T4 |
21 |
|
T5 |
30 |
|
T22 |
28 |
zero_val |
higher_val |
auto[0] |
574 |
1 |
|
|
T4 |
1 |
|
T23 |
1 |
|
T25 |
1 |
zero_val |
higher_val |
auto[1] |
183 |
1 |
|
|
T4 |
2 |
|
T36 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[0] |
594 |
1 |
|
|
T6 |
1 |
|
T22 |
1 |
|
T10 |
1 |
zero_val |
lower_val |
auto[1] |
187 |
1 |
|
|
T4 |
1 |
|
T13 |
5 |
|
T30 |
1 |
zero_val |
zero_val |
auto[0] |
287 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[1] |
268 |
1 |
|
|
T4 |
2 |
|
T36 |
3 |
|
T13 |
1 |