Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9433	1			T4	25		T22	30		T25	19
len_5001_7500	15269	1			T4	66		T22	50		T25	18
len_2501_5000	9434	1			T4	17		T22	11		T25	18
len_1025_2500	5516	1			T4	3		T22	5		T25	11
len_769_1024	6714	1			T4	14		T5	34		T6	6
len_513_768	7276	1			T4	9		T5	33		T6	10
len_257_512	21559	1			T4	12		T5	29		T6	10
len_0_256	260537	1			T4	36		T5	28		T6	15
len_keccak_block_sizes[72]	721	1			T25	2		T27	2		T35	2
len_keccak_block_sizes[104]	622	1			T25	2		T27	2		T35	2
len_keccak_block_sizes[136]	526	1			T25	2		T27	2		T35	2
len_keccak_block_sizes[144]	434	1			T5	1		T27	2		T36	3
len_keccak_block_sizes[168]	329	1			T6	1		T36	3		T165	3
len_1	771	1			T25	2		T27	2		T35	2
len_0	1261	1			T4	3		T22	5		T25	2