Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101590529	1			T54	8		T58	8		T4	8503
all_pins[1]	101590529	1			T54	8		T58	8		T4	8503
all_pins[2]	101590529	1			T54	8		T58	8		T4	8503

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	252331742	1			T54	21		T58	21		T4	20722
values[0x1]	52439845	1			T54	3		T58	3		T4	4787
transitions[0x0=>0x1]	52022583	1			T54	3		T58	3		T4	4118
transitions[0x1=>0x0]	52022602	1			T54	3		T58	3		T4	4118

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101073809	1			T54	8		T58	6		T4	8256
all_pins[0]	values[0x1]	516720	1			T58	2		T4	247		T5	185
all_pins[0]	transitions[0x0=>0x1]	217189	1			T58	2		T4	26		T5	15
all_pins[0]	transitions[0x1=>0x0]	51330424	1			T54	2		T58	1		T4	3295
all_pins[1]	values[0x0]	49960574	1			T54	6		T58	7		T4	4987
all_pins[1]	values[0x1]	51629955	1			T54	2		T58	1		T4	3516
all_pins[1]	transitions[0x0=>0x1]	51513975	1			T54	2		T58	1		T4	3077
all_pins[1]	transitions[0x1=>0x0]	177190	1			T54	1		T4	585		T13	3094
all_pins[2]	values[0x0]	101297359	1			T54	7		T58	8		T4	7479
all_pins[2]	values[0x1]	293170	1			T54	1		T4	1024		T13	5532
all_pins[2]	transitions[0x0=>0x1]	291419	1			T54	1		T4	1015		T13	5491
all_pins[2]	transitions[0x1=>0x0]	514988	1			T58	2		T4	238		T5	185