Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	741	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6034	1			T4	21		T5	31		T6	6
len_601_800	13986	1			T4	64		T5	44		T6	18
len_401_600	9081	1			T4	33		T5	22		T6	7
len_201_400	16865	1			T4	23		T5	18		T6	8
len_65_200	74679	1			T4	11		T5	3		T6	1
len_min_for_xof_require_squeeze	1000	1			T22	1		T36	9		T165	10
len_keccak_block_sizes[72]	781	1			T36	9		T165	5		T166	9
len_keccak_block_sizes[104]	770	1			T36	9		T13	1		T165	5
len_keccak_block_sizes[136]	759	1			T4	1		T36	9		T165	5
len_keccak_block_sizes[144]	289	1			T13	1		T165	5		T31	5
len_keccak_block_sizes[168]	289	1			T165	5		T31	5		T167	5
len_datapath_width	14481	1			T4	7		T5	1		T36	9
len_2_63	215719	1			T4	44		T5	52		T6	33
len_1	45	1			T168	2		T20	1		T169	1