Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 212 1 T54 7 T58 7 T157 4
all_values[1] 212 1 T54 7 T58 7 T157 4
all_values[2] 212 1 T54 7 T58 7 T157 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 382 1 T54 10 T58 11 T157 7
auto[1] 254 1 T54 11 T58 10 T157 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 248 1 T54 10 T58 12 T157 7
auto[1] 388 1 T54 11 T58 9 T157 5


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 378 1 T54 16 T58 15 T157 8
auto[1] 258 1 T54 5 T58 6 T157 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 45 1 T54 2 T58 3 T157 1
all_values[0] auto[0] auto[0] auto[1] 22 1 T54 3 T157 1 T158 1
all_values[0] auto[0] auto[1] auto[0] 29 1 T157 1 T159 2 T158 1
all_values[0] auto[0] auto[1] auto[1] 21 1 T58 1 T160 2 T161 1
all_values[0] auto[1] auto[0] auto[1] 59 1 T54 2 T58 2 T160 1
all_values[0] auto[1] auto[1] auto[1] 36 1 T58 1 T157 1 T160 1
all_values[1] auto[0] auto[0] auto[0] 52 1 T58 3 T157 1 T159 1
all_values[1] auto[0] auto[0] auto[1] 26 1 T58 1 T160 1 T159 1
all_values[1] auto[0] auto[1] auto[0] 33 1 T54 3 T58 1 T157 1
all_values[1] auto[0] auto[1] auto[1] 21 1 T54 2 T58 1 T160 1
all_values[1] auto[1] auto[0] auto[1] 55 1 T54 1 T157 1 T159 1
all_values[1] auto[1] auto[1] auto[1] 25 1 T54 1 T58 1 T157 1
all_values[2] auto[0] auto[0] auto[0] 55 1 T54 1 T58 2 T157 2
all_values[2] auto[0] auto[0] auto[1] 21 1 T160 1 T159 1 T158 1
all_values[2] auto[0] auto[1] auto[0] 34 1 T54 4 T58 3 T157 1
all_values[2] auto[0] auto[1] auto[1] 19 1 T54 1 T158 1 T162 1
all_values[2] auto[1] auto[0] auto[1] 47 1 T54 1 T157 1 T160 3
all_values[2] auto[1] auto[1] auto[1] 36 1 T58 2 T158 1 T161 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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