Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100286678	1			T1	5		T2	4		T56	8
all_values[1]	100286678	1			T1	5		T2	4		T56	8
all_values[2]	100286678	1			T1	5		T2	4		T56	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591041

1

T1

9

T2

6

T56

8

auto[1]

300268993

1

T1

6

T2

6

T56

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299330715

1

T1

12

T2

12

T56

15

auto[1]

1529319

1

T1

3

T56

9

T124

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	198557	1			T2	1		T56	1		T63	1
all_values[0]	auto[0]	auto[1]	2198	1			T56	1		T124	3		T125	2
all_values[0]	auto[1]	auto[0]	99578348	1			T1	4		T2	3		T56	4
all_values[0]	auto[1]	auto[1]	507575	1			T1	1		T56	2		T124	2
all_values[1]	auto[0]	auto[0]	189181	1			T1	4		T2	2		T56	1
all_values[1]	auto[0]	auto[1]	1559	1			T1	1		T56	1		T124	1
all_values[1]	auto[1]	auto[0]	99587724	1			T2	2		T56	4		T63	1
all_values[1]	auto[1]	auto[1]	508214	1			T56	2		T124	4		T125	1
all_values[2]	auto[0]	auto[0]	197686	1			T1	3		T2	3		T56	1
all_values[2]	auto[0]	auto[1]	1860	1			T1	1		T56	3		T124	4
all_values[2]	auto[1]	auto[0]	99579219	1			T1	1		T2	1		T56	4
all_values[2]	auto[1]	auto[1]	507913	1			T124	1		T140	3		T153	4