Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326838 |
1 |
|
|
T4 |
620 |
|
T5 |
18 |
|
T6 |
140 |
auto[1] |
367371 |
1 |
|
|
T5 |
166 |
|
T18 |
352 |
|
T10 |
376 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174038 |
1 |
|
|
T4 |
138 |
|
T5 |
49 |
|
T6 |
40 |
lower_val |
172211 |
1 |
|
|
T4 |
157 |
|
T5 |
40 |
|
T6 |
38 |
zero_val |
1976 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254889 |
1 |
|
|
T4 |
308 |
|
T5 |
66 |
|
T6 |
70 |
lower_val |
254856 |
1 |
|
|
T4 |
312 |
|
T5 |
52 |
|
T6 |
70 |
zero_val |
184464 |
1 |
|
|
T5 |
66 |
|
T18 |
186 |
|
T15 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40513 |
1 |
|
|
T4 |
69 |
|
T5 |
3 |
|
T6 |
23 |
higher_val |
higher_val |
auto[1] |
23137 |
1 |
|
|
T5 |
17 |
|
T18 |
17 |
|
T10 |
19 |
higher_val |
lower_val |
auto[0] |
40681 |
1 |
|
|
T4 |
69 |
|
T5 |
4 |
|
T6 |
17 |
higher_val |
lower_val |
auto[1] |
23229 |
1 |
|
|
T5 |
6 |
|
T18 |
19 |
|
T10 |
22 |
higher_val |
zero_val |
auto[0] |
106 |
1 |
|
|
T16 |
1 |
|
T22 |
1 |
|
T71 |
1 |
higher_val |
zero_val |
auto[1] |
46372 |
1 |
|
|
T5 |
19 |
|
T18 |
39 |
|
T10 |
47 |
lower_val |
higher_val |
auto[0] |
40693 |
1 |
|
|
T4 |
79 |
|
T5 |
3 |
|
T6 |
22 |
lower_val |
higher_val |
auto[1] |
22749 |
1 |
|
|
T5 |
9 |
|
T18 |
28 |
|
T10 |
26 |
lower_val |
lower_val |
auto[0] |
40348 |
1 |
|
|
T4 |
78 |
|
T5 |
2 |
|
T6 |
16 |
lower_val |
lower_val |
auto[1] |
22632 |
1 |
|
|
T5 |
11 |
|
T18 |
25 |
|
T10 |
23 |
lower_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T15 |
1 |
|
T87 |
1 |
|
T71 |
1 |
lower_val |
zero_val |
auto[1] |
45697 |
1 |
|
|
T5 |
15 |
|
T18 |
53 |
|
T10 |
45 |
zero_val |
higher_val |
auto[0] |
543 |
1 |
|
|
T5 |
1 |
|
T17 |
1 |
|
T20 |
1 |
zero_val |
higher_val |
auto[1] |
167 |
1 |
|
|
T71 |
3 |
|
T72 |
3 |
|
T155 |
1 |
zero_val |
lower_val |
auto[0] |
593 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T19 |
1 |
zero_val |
lower_val |
auto[1] |
171 |
1 |
|
|
T33 |
1 |
|
T72 |
3 |
|
T155 |
1 |
zero_val |
zero_val |
auto[0] |
285 |
1 |
|
|
T18 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
zero_val |
auto[1] |
217 |
1 |
|
|
T32 |
3 |
|
T155 |
2 |
|
T42 |
1 |